JP2723909B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a sense circuit for reading signals from the semiconductor memory, and more particularly to a high-speed, high-stability suitable for a high-speed, highly integrated DRAM and SRAM. It relates to a sense circuit.

[Conventional technology]

As a sense circuit of a conventional memory, a configuration as shown in FIG. 2 is generally used. A method to improve it is the IEE International Solid State Circuit Conference (1986).
Years) 262 to 263 (IEEE, International Solid-
State Circuits Conference 1986, pp.262-263).

[Problems to be solved by the invention]

The conventional sense circuit has a configuration as shown in FIG. Here, the sense circuit of the dynamic memory will be described.
By placing a memory cell of a static memory in place of the memory array and the sense amplifier, a sense circuit can be similarly configured.

In the figure, 1 is a dynamic memory cell array, 2
Is a CMOS sense amplifier, 3 is a column switch, 4 is an address designation signal for turning on / off the gate of the column switch 3, 5 is a decoder for selecting an address, and 6A and 6B are I / O lines for transmitting signals. (Input / output lines), 8 and 20 are I / O lines 6A and 6
A load element for applying the potential of B, 9 and 10 are load capacitors generated parasitically on the I / O lines 6A and 6B, and 12 is a voltage amplifier for amplifying the signal voltage difference between the I / O lines 6A and 6B.

In a conventional sense circuit, the load 20, 8 is driven by a sense amplifier serving as a signal source, and a signal voltage difference appearing between the I / O line pair 6A and 6B is amplified to a large voltage difference by the voltage amplifier 12. The information read out by one sense amplifier is amplified and output.

FIG. 3 shows operation waveforms when different addresses are successively read out by switching addresses in the conventional example. In the figure, τ ₁ is the time from when the address is switched to when the signal voltage on the I / O line crosses, and τ ₂ is the time from when the signal voltage on the I / O line crosses until the signal output appears on the output of the amplifier 12. Shows the time.

In the conventional memory, since the method of amplifying the voltage amplitude of the I / O line is adopted, it is necessary to increase the voltage amplitude of the I / O line (> 200 mV). Therefore, when reading different signals, the time τ until the voltages of the I / O lines cross
₁ has increased, leading to an increase in the time required for reading information. τ ₁ is the impedance of the I / O line (R ₁
A parallel resistance of R ₂₎ And the load capacity C _L. As the integration of memory elements increases, the wiring resistance and wiring capacitance increase.
Signal delay tau ₁ at O line had become a major obstacle to high-speed memory LSI realized. For example, depending on the magnitude of the operating current, tau ₁ value extends to 70% of the total of the delay τ _{1 +} τ ₂ values.

Further, when a different signal is read, a signal voltage corresponding to the previous read information remains on the I / O line, so that an operation defect that information of the sense amplifier is inverted is likely to occur. Therefore, the W / L ratio (gate width to gate length ratio) of the transistor of the column switch is changed to the W / L ratio of the transistor of the sense amplifier.
It could not be larger than the L ratio, which was a major obstacle to high speed and circuit operation margin.

Means for increasing the operating speed of the I / O line sensing circuit are discussed in the aforementioned document, IEE International Solid State Circuit Conference (1986), pp. 262 to 263. Have been. In this example, a small voltage change of the I / O line is amplified.However, since the voltage gain is as low as 35, the signal voltage of the I / O line is required to obtain a voltage amplitude of 5V. Requires a value of about 140 mV. Although this value is slightly lower than that of the conventional sense circuit described above, it is a value that is not much different from that of the conventional sense circuit, and it cannot be expected that the signal delay is significantly improved.

[Means for solving the problem]

In order to solve the above problems, the present invention provides a mechanism for stabilizing the potential of an I / O line transmitting a signal, and a mechanism for converting a signal current flowing through the I / O line to a signal voltage. A voltage conversion mechanism was used as a signal amplifying means.

(Operation)

The current-voltage conversion mechanism of the present invention operates to stabilize the potential of the I / O line. Thus, the potential of the I / O line has a substantially constant value regardless of the information. Therefore, the delay until the voltages of the I / O lines cross when different information is read can be significantly reduced. Further, since the potential difference between the I / O line pair is almost 0 V, the operation margin for reading different information can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a sense circuit of a dynamic memory will be described. However, in a static memory, a sense circuit can be similarly configured by placing a memory cell of the static memory in place of the memory array and the sense amplifier.

FIG. 1 shows an embodiment of the present invention. In FIG.
1 is a memory cell array of a dynamic memory, and 2 is a sense amplifier for amplifying information read from the memory cell. The memory cell array 1 itself is
Since the configuration is the same as that of a well-known device, a detailed description thereof will be omitted, but a plurality of dynamic memory cells each including an information storage capacitor and a selection MIS transistor, The capacitor is composed of a plurality of data lines to be connected via the selection MIS transistor and a plurality of word lines to which the gate of the selection MIS transistor is connected. In the figure, adjacent data lines of a memory cell array are paired with each other, and as shown in FIG.
Connected to. In FIG. 1, reference numeral 3 denotes a column switch for reading information amplified by a sense amplifier to an I / O line (input / output line) and writing information from the I / O line to a memory cell;
5 is an address decoder for selecting one of a plurality of sense amplifiers, 4 is its output line, 6A and 6B are I / O lines (input / output lines) for transmitting signals, and 9 and 10 are I / O lines. Line parasitic capacitance, 8 is a write circuit, 11 is an I / V converter (current-voltage converter), 1
3, 14 are amplifiers, 15, 16 are feedback circuits, 7A, 7B are I /
The output of the V converter, 12 indicates a voltage amplifier, and 17 and 18 indicate differential amplifiers, respectively.

Hereinafter, the operation of this embodiment will be described with reference to FIG. The information read from the memory cell is amplified by the sense amplifier 2. Then, by the column switch 3,
The sense amplifier 2 is connected to the I / O line pair 6A, 6B. At this time, the sense amplifier 2 tries to drop one of the I / O line pairs to the low voltage side according to the information read from the memory cell. That is, this is equivalent to a state in which a signal current source is connected to one of the I / O line pairs. Next, the I / V converter 11
The signal current on the / O line pair is detected, and the proportional voltage is
Output to A and 7B. At the same time, the I / V converter 11
A, 7B) to the input side (6A, 6B) feedback circuit 15,
By applying negative feedback through 16, the potential of the I / O line pair 6A and 6B is stabilized.

FIG. 4 shows waveforms at various points during the signal read operation. Since almost no potential difference appears in the I / O lines, the time τ ₁ required for the potentials of the I / O lines to cross when reading different information can be extremely reduced. The time τ _c required for the output voltage of the I / V converter to cross is represented by I / V in FIG.
It is determined by the time during which the outputs 7A and 7B of the converter are charged and discharged by the amplifiers 13 and 14. Since the load capacity of the outputs 7A and 7B is sufficiently smaller than the capacity of the I / O line, the delay τ _c has an extremely small value. As a result, the total delay τ ₁ + τ _c + τ ₂ can be significantly reduced as compared with the conventional case.

Here, the I / V converter which is the greatest feature of the present invention will be described in detail. As described above, the role of the I / V converter is (1) to convert the signal current on the I / O line into a voltage, and (2) to stabilize the potential of the I / O line. Hereinafter, embodiments of the I / V converter will be described.

[First Embodiment of I / V Converter] FIG. 5 shows a first embodiment of the I / V converter. In the figure, 41A and 41B are I / V converters connected to the I / O lines 6A and 6B, respectively. Each I / V converter includes N-channel MIS transistors 42 to 44, P-channel MIS transistors 45 and 46, and a resistor 47. I / O by transistors 42-46
An input line 6A and the reference voltage V _R, form a differential amplifier to output 7A. The differential amplifier is connected to the amplifiers (13, 14) of FIG. 1, and the resistor 47 is connected to the feedback circuit (1) of FIG.
5,16) respectively.

Hereinafter, the operation of the present embodiment will be described. The output signal voltage v _o of the I / V converter is expressed as v _o = R _c · i _i by the signal current i _i of the I / O line. Here, R _c is a resistance value of 47. Thus while a constant potential of I / O lines by setting the value of R _c appropriately, it is possible to obtain a signal voltage proportional to the signal current i _i to the output.

Second Embodiment of I / V Converter FIG. 6 shows a second embodiment of the I / V converter. In the figure, 51A and 51B are I / V converters connected to the I / O lines 6A and 6B, respectively. 56 is a P-channel MIS transistor, 57 is a current source, and 56 and 57 constitute a bias circuit of an inverter included in the I / V converter. Each I / V converter includes N-channel MIS transistors 52 and 53, a P-channel MIS transistor 54, and a load 55. 52 and 54 constitute an inverter having the I / O line 6A as input and 7A as output, and 53 and 55 constitute a voltage controlled current source driven by the output of the inverter. The inverter corresponds to the amplifier (13, 14) in FIG. 1, and the voltage controlled current source corresponds to the feedback circuit (15, 16) in FIG.

Hereinafter, the operation of the present embodiment will be described. The inverter is biased so that a constant current flows. Therefore, when a potential V _cs of 50 is applied, the potential of the I / O line 6A becomes V _cs + V _th
The voltage of the output 7A is determined so as to be (52). The output voltage V (7A) is expressed as V (7A) = _Vcs + _Vth (52) + _Vth (53). Here, V _th (52) and V _th (53) are N
It shows the threshold voltages of the channel MIS transistors 52 and 53. Let the signal voltage of the I / O line be v _i , and the signal current of the I / O line be i _i , I /
Assuming that the output signal voltage of the V converter is _vo It is expressed as Here g _m is the transconductance of the transistor 53, G denotes a voltage gain of the inverter. Thereby, the voltage amplitude of the I / O line becomes 1 / G of the output voltage amplitude. Therefore, in order to obtain an output voltage amplitude> 200 mV, for example, it is possible to easily set G to a value of about 50, and the voltage amplitude of the I / O line may be about 4 mV.

As a result, after stabilizing the potential of the I / O line, a signal voltage proportional to the signal current of the I / O line can be obtained at the output.

Third Embodiment of I / V Converter FIG. 7 shows a third embodiment of the I / V converter. In the figure, 61A and 61B are I / V converters connected to the I / O lines 6A and 6B, respectively. Each I / V converter includes N-channel MIS transistors 62 to 65, P-channel MIS transistors 66 and 67, and a load 68. Transistors 62, 63,
By 64,66,67 inputs the I / O line 6A and the reference voltage V _R, form a differential amplifier to output 7A, by 63 and 68, a voltage controlled current driven by the output of the differential amplifier Make up the source. The differential amplifier is the amplifier in Fig. 1 (13,14)
First, the voltage-controlled current source is connected to the feedback circuit (1) shown in FIG.
5,16) respectively.

Since in this embodiment uses a differential amplifier may be a voltage equal to the voltage of the I / O line to a reference voltage V _R. That has the feature that the potential of the I / O line can be set freely by the control of the V _R. Further, since the potential of the I / O line is constant irrespective of the value of the operation current of the differential amplifier, a circuit with a large operation margin can be provided.

Fourth Embodiment of I / V Converter FIG. 8 shows a fourth embodiment of the I / V converter. In the figure, 70A and 70B are I / V converters connected to the I / O lines 6A and 6B, respectively. Each I / V converter has N-channel MIS transistors 71 to 73, P-channel MIS transistors 74 to 76,
And a load 77. Transistors 71, 7
The 2,73,75,76, inputs the I / O line 6A and the reference voltage V _R, form a differential amplifier to output 7B, by 74 and 77, a voltage which is driven by the output of the differential amplifier It constitutes a control current source. The differential amplifier is the amplifier in Fig. 1 (13,14)
First, the voltage-controlled current source is connected to the feedback circuit (1) shown in FIG.
5,16) respectively.

Unlike the previous embodiment, since the P-channel MIS transistor is used as the voltage-controlled current driving element, it has a feature that the power supply efficiency is high. That is, the output voltage of the I / V converter, to become a low voltage relative to the voltage V _R of I / O lines, it is possible to set a high V _R to a value close to the supply voltage V _cc.

In each of the embodiments described above, the inverting type (the phase is reversed between the input 6A and the output 7A) and the non-inverting type (the phase is not reversed between the input 7A and the output 6A). Was used to provide negative feedback. The feedback circuit of this embodiment is a P-channel MIS
Because of the use of transistors, it is an inversion type. Therefore, the amplifier is of a non-inverting type.

[Fifth Embodiment of I / V Converter] FIG. 9 shows a fifth embodiment of the I / V converter. In the figure, 70A and 70B are I / V converters connected to the I / O lines 6A and 6B, respectively. The difference from the previous embodiment is that the N-channel MIS
That is, the transistor 78 is added. The previous example,
Since the I / O line is connected to the drain of the P-channel MIS transistor 74, the impedance is high, and the response when the signal current flows transiently has some difficulty. On the other hand, in the present embodiment, a diode-connected N-channel MIS transistor 78 is connected in parallel with the P-channel MIS transistor 74.
Is added to reduce the impedance of the I / O line and improve the transient response. In addition, I /
Since the voltage of the O line becomes V _cc −V _th (V _th is the threshold voltage of the N-channel MIS transistor), a voltage of V _cc −V _th is generated by the N-channel MIS transistor 79, and the reference voltage V _R

Next, a data write operation will be described. FIG. 10 shows an embodiment of the write circuit (8 in FIG. 1), and FIG. 11 shows waveforms of respective parts during the write operation. In the figure, D _in is the data input terminal, 8
0 is a data input buffer, 81 and 82 are inverters, 83 and 84 are N-channel MIS transistors, which are connected to I / O lines 6A and 6B. Data input from the D _in is latched by the data input buffer. Write timing signal φ
_{While W} is at a low potential, it is in a read state,
The voltage stabilization mechanism of the I / V converter works, and I / O lines 6A and 6B
Are almost at the same potential. phi _W is the transistor 83 and 84 is turned on in a high potential, 6A, true each input data to the 6B, complement signal is written. That is, one of 6A and 6B has a high potential and the other has a low potential according to the input data. This data is written to the selected memory cell through the column switch 5 and the data line. When the φ _W is a low potential, 6A, 6B return to almost the same potential.

Note that it is desirable to stop the operation of the I / V converter during the writing operation in terms of power consumption. For this purpose, for example, a signal having a phase opposite to that of the write signal phi _W 5 (or FIG. 7, FIG. 8, FIG. 9) may be the phi _E of.

In the above embodiments, the memory sense circuit using the complementary MIS transistor has been described. However, means for stabilizing the voltage of the I / O line and means for outputting a voltage related to the signal current of the I / O line The present invention can be similarly applied as long as the above is provided. For example, the sense circuit can be similarly configured by using a single-polarity MIS transistor, a combination thereof, or another circuit method.

In particular, by using MIS transistors for memory arrays and bipolar transistors for I / O line sensing circuits,
Extremely high-speed, highly integrated memory LS utilizing element performance
I can also provide.

〔The invention's effect〕

According to the present invention, a delay in a sense circuit portion of a dynamic memory or a static memory can be reduced, so that a higher-speed semiconductor memory can be provided.
Further, since an operation failure when reading different information can be prevented, a highly reliable semiconductor memory can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sense circuit diagram of one embodiment of the present invention, FIG. 2 is a conventional sense circuit diagram, FIG. 3 is a signal timing diagram showing the operation of the conventional sense circuit, FIG. FIG. 11 and FIG. 11 are signal timing diagrams showing the operation of one embodiment of the present invention, and FIGS.
FIGS. 7, 7, 8 and 9 show an embodiment of the present invention.
FIG. 10 is a diagram showing a specific configuration of the I / V converter, and FIG. 10 is a diagram showing a specific configuration diagram of the write circuit in the embodiment of the present invention. 5. Description of reference numerals 1 ... Dynamic memory cell array, 2 ... Sense amplifier, 3 ... Column switch, 4 ... Address designating signal, 5 ... Address decoder, 6A, 6B ... I / O line , 8 ... write circuit, 11 ... I / V converter, 12 ... voltage amplifier.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoo Ito 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shinichi Ikenaga 1-280 Higashi Koikekubo Kokubunji City, Tokyo Hitachi, Ltd. (56) References JP-A-57-150185 (JP, A) JP-A-1-3111497 (JP, A) JP-A-1-155589 (JP, A)

Claims (9)

(57) [Claims] A plurality of word lines; a plurality of pairs of data lines provided to intersect the word lines; and a plurality of memory cells provided at intersections of the data lines and the word lines. A memory cell array; a pair of common lines; a decoder for selecting an address; and a plurality of pairs of data lines provided between the plurality of pairs of data lines and the pair of common lines of the memory cell array. A column switch operated by the output of the decoder so as to connect the pair of data lines to be connected to the pair of common lines; and information from the memory cell transmitted to the common line via the column switch. A current-to-voltage converter for converting a corresponding signal current into a voltage, wherein the current-to-voltage converter uses one of the pair of common lines and the other signal of the pair of common lines as an input of the pair. With one amplifier The first input to each Negate Eve off Eid put back consists of a feedback circuit the first signal corresponding to said information from the memory cell of the pair of amplifiers
A semiconductor memory obtained from the output of the amplifier. 2. The first amplifier according to claim 1, wherein said first amplifier comprises a first inverter which receives one signal of said common line and a second inverter which receives another signal of said common line. The circuit comprises: a first feedback circuit for applying negative feedback to an input of the first inverter; and a second feedback circuit for applying negative feedback to an input of the second inverter. 2. The semiconductor memory according to item 1, wherein 3. The first and second inverters each have a first conductivity type MIS transistor that receives an input at a gate and outputs an output signal from a drain, and the first feedback circuit includes a first inverter. The MIS transistor receives the output of the second inverter at its gate and outputs a signal to be fed back to the input of the first inverter to its source. The second feedback circuit receives the output of the second inverter at its gate. 3. The semiconductor memory according to claim 2, further comprising: an MIS transistor that outputs a signal to be fed back to an input of said second inverter to a source thereof. 4. The first amplifier includes a first differential amplifier having one signal of one of the pair of common lines as one input and a reference voltage as the other input, and the other of the pair of common lines. And a second differential amplifier having the reference signal as one input and the reference voltage as the other input, wherein the feedback circuit comprises a first differential amplifier for applying a negative feedback to the one input of the first differential amplifier.
2. The semiconductor memory according to claim 1, further comprising a feedback circuit configured to apply negative feedback to said one input of said second differential amplifier. 5. The first and second differential amplifiers each have a first MIS of one conductivity type whose gate is the one input.
A transistor, a second MIS transistor of one conductivity type whose gate is the other input, and a second MIS transistor of one conductivity type connected to a common connection point of the first and second MIS transistors.
A third MIS transistor, a fourth MIS transistor of the other conductivity type connected to the first MIS transistor, and a second MIS transistor.
A fifth MIS transistor of the other conductivity type connected to the transistor, and the first MIS transistor and the fifth MIS transistor
The connection point with the 4MIS transistor is used as an inverted output terminal, and the first feedback circuit is provided between the inverted output terminal of the first differential amplifier and the one input of the first differential amplifier. The second feedback circuit includes a resistor provided between the inverting output terminal of the second differential amplifier and the one input of the second differential amplifier. The semiconductor memory according to claim 4, comprising an element. 6. The first and second differential amplifiers each include a first conductive type first MIS having a gate as the one input.
A transistor, a second MIS transistor of one conductivity type whose gate is the other input, and a second MIS transistor of one conductivity type connected to a common connection point of the first and second MIS transistors.
A third MIS transistor, a fourth MIS transistor of the other conductivity type connected to the first MIS transistor, and a second MIS transistor.
A fifth MIS transistor of the other conductivity type connected to the transistor, and the first MIS transistor and the fifth MIS transistor
The connection point with the 4MIS transistor is used as an inverted output terminal. The first feedback circuit has a gate connected to the inverted output terminal of the first differential amplifier, and a source connected to the first differential amplifier. The second feedback circuit comprises a MIS transistor connected to one input, and the second feedback circuit has a gate connected to the inverted output terminal of the second differential amplifier, and a source connected to the one of the second differential amplifier. 5. The semiconductor memory according to claim 4, comprising a MIS transistor connected to an input. 7. The first and second differential amplifiers each have a first MIS of one conductivity type whose gate is the one input.
A transistor, a second MIS transistor of one conductivity type whose gate is the other input, and a second MIS transistor of one conductivity type connected to a common connection point of the first and second MIS transistors.
A third MIS transistor, a fourth MIS transistor of the other conductivity type connected to the first MIS transistor, and a second MIS transistor.
A fifth MIS transistor of the other conductivity type connected to the transistor, wherein the second MIS transistor and the fifth MIS transistor are connected to each other;
The connection point with the 5MIS transistor is used as a non-inverting output terminal. The first feedback circuit has a gate connected to the non-inverting output terminal of the first differential amplifier, and a drain connected to the first differential amplifier. Connected to one of the above inputs
The second feedback circuit includes an S-transistor, a gate of which is connected to the non-inverting output terminal of the second differential amplifier, and a drain of which is connected to the one input of the second differential amplifier.
5. The semiconductor memory according to claim 4, comprising an S transistor. 8. The memory cell according to claim 1, wherein said memory cell is a memory cell constituting a dynamic memory, and said pair of data lines is provided with a sense amplifier for amplifying information read from said memory cell. The semiconductor memory according to any one of claims 1 to 7, wherein: 9. A writing circuit connected to the common line and writing the information in the memory cell, wherein the operation of the first amplifier is stopped when the writing circuit performs a writing operation. The semiconductor memory according to any one of claims 1 to 9, wherein: