JP2724134B2 - Sample and hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit suitable for a monolithic IC. 2. Description of the Related Art As shown in FIG. 3, a conventional sample-and-hold circuit has two transistors Q ₁₃ and Q ₁₄ connected to an emitter, one of the transistors Q ₁₃ and Q ₁₄ is connected to an input, and the other is connected to a diode to form a constant current. A connection to a source (IA / 2) has been used for bipolar monolithic ICs. This is described in, for example, ISSC, Dissertation, T.P.M. 14.1 (1983), pp. 178 to 179 (ISSCC, Digest of Technical
Papers, THPM 14.1, pp 178-179 (198
3)). This method is characterized in that the input is the base of a transistor, the input impedance is higher than the method using a diode bridge, and the circuit is simpler. [0003] [0006] The above prior art, transistor diode-connected evening requires a constant current source as a load of Q _14, forced ze use pnp transistor for the constant current source Absent. However, when a monolithic IC is used, a high-speed pnp transistor cannot be obtained, which is an obstacle to speeding up the sample-and-hold circuit. The present invention has been made with the development of a high-speed sample-and-hold circuit suitable for a bipolar monolithic IC without using elements such as a pnp transistor which is an obstacle to high-speed operation. Prior to the present invention, the inventors of the present invention disclosed a high-speed sample-and-hold circuit having a sample state mode and a hold state mode as an input transistor Q1 and a pair of diode-connected output transistors in the hold state mode. We studied a method to eliminate the flow of current into and out of the hold capacitor by interrupting the current flowing to Q2. However, in this method, the input transistor Q1 and the output transistor Q2 are both non-conductive in the hold state mode, but a parasitic capacitance exists between the base and emitter terminals of each transistor Q1 and the transistor Q2. The problem that a part of the input signal propagates to the hold capacitor via the parasitic capacitance has been clarified by the study of the present inventors. That is, a so-called "field-through error" occurs in which a part of the input appears at the output or the output signal changes in accordance with the input signal in the hold state mode. The problem is to reduce. Accordingly, an object of the present invention is to provide a sample / sample which can reduce such a field-through error.
An object of the present invention is to provide a hold circuit. The above object is achieved by reducing the impedance of a common emitter terminal of an input transistor (Q1) and an output transistor (Q2) in a hold state mode by a control means (Q8). Is achieved. In the hold mode, the impedance of the common emitter terminal of the input transistor (Q1) and the output transistor (Q2) is reduced by the control means (Q8), so that the input and output signals are supplied from the input terminal (IN). The signal propagated through the parasitic capacitance between the base and the emitter of the power transistor is attenuated by the low impedance of the control means (Q8) of the common emitter terminal of the input transistor (Q1) and the output transistor (Q2). It is possible to sufficiently reduce the amount of propagation signal to the capacitor for use. FIG. 1 is a block diagram showing a sample and hold circuit according to an embodiment of the present invention. FIG. 1 shows a configuration in which a control circuit Q8 for making the common emitter of the input transistor Q1 and the output transistor Q2 of the sample and hold circuit low impedance in the hold mode is added. In the figure, first, in the sample state mode, the normal phase clock CLK which is a control signal is at the "H" level, the negative phase clock / CLK is at the "L" level, Q4 and Q6 are "on", while Q5 and Q5 are on. , Q7 is turned off. At this time, Q
Since a current flows through 1 and Q2 and the base-emitter voltage V _BE of both transistors is substantially equal, the voltage of the holding capacitor CH becomes substantially equal to the input voltage. At this time, a current I1 flows through Q6, and a voltage drop of R2 · I1 occurs in the resistor R2. Therefore, Vcc-R2 / I1 is changed to the input voltage V _IN
If lower, the emitter follower transistor Q8 of the control circuit will be non-conductive. At this time, the current I2 changes to Q1 and Q2.
Although it will be added to IE and flows, if I2≪IE is selected, I2 can be ignored, and otherwise, the value of IE can be selected in consideration of I2, so that there is no effect on the input signal. Next, in the hold state mode, the normal phase clock CLK which is a control signal is at "L" level and the negative phase clock / C
LK goes to the “H” level, Q4 and Q6 are turned “off”, and Q5 and Q7 are turned “on.” At this time, the emitter follower transistor Q8 of the control circuit becomes conductive, so that Q1, Q2, Q8 The emitter potential becomes Vcc- _VBE , which is kept higher than the input voltage and the voltage of the hold capacitor.
1, Q2 becomes non-conductive. Therefore, the emitter follower transistor Q8 of the control circuit is in a conductive state.
The impedance Ze of the emitter of Q8 is given by the following equation. ## EQU1 ## Where gm = qI ₂ / KT and β
Is the current amplification factor of Q8. For example, when I ₂ = 100 μA, β = 100, and R2 = 1 kΩ, Ze becomes about 270Ω. Therefore, the input signal propagated through the capacitance between the base-emitter of Q1 in the "off" state is greatly attenuated by the low impedance Ze of the common emitter terminal before the base-emitter of Q2 is turned on. The voltage is transmitted to the hold capacitor CH via the gap, and the output voltage of the sample / hold circuit does not fluctuate. In the embodiment shown in FIG. 1, care is taken so that the positive-phase clock and the negative-phase clock are not transmitted directly to the hold capacitor in the hold state mode via the parasitic capacitance of Q2. The potential is set by an intermediate level VB between the high level and the low level of the positive phase clock CLK and the negative phase clock / CLK. Next, still another embodiment is shown in FIG. This embodiment differs from the embodiment of FIG. 1 in the connection form between Q1, Q2 and Q4, Q5, and the supply of the positive-phase clock CLK and the negative-phase clock / CLK to Q4, Q5, Q6, Q7. Emitter follower transistor of control circuit in hold state mode
The operation of lowering the impedance of the common emitter of Q1 and Q2 by the conduction of Q8 is exactly the same. According to these embodiments, the leakage of the input signal to the hold capacitor in the hold state mode of the sample and hold circuit can be reduced by simply adding the emitter follower transistor of the simple control circuit, and the accuracy can be improved. Has the effect. As described above, according to the present invention, it is possible to provide a sample and hold circuit capable of reducing a field through error.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a sample and hold circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing a sample and hold circuit according to a second embodiment of the present invention. FIG. 3 is a diagram showing a conventional example. [Explanation of Signs] Q1: input transistor, Q2: output transistor, R1: load resistance, Q4, Q5, switch transistor, CH: hold capacitor, 10: buffer circuit.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Toshihiko Shimizu               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshito Neneko               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kenji Asashima               1-280 Higashi Koikebo, Kokubunji-shi, Tokyo                 Central Research Laboratory, Hitachi, Ltd.

Claims (1)

(57) [Claims] A first differential pair transistor including a first transistor to which an input signal is input to a base, and a second transistor having an emitter connected to the emitter of the first transistor; A load circuit comprising a third transistor having an emitter connected to the collector of the second transistor, and a first resistor connected between the collector and base of the third transistor and an operating potential point; A capacitor connected to the collector of the second transistor of the first differential pair transistor and an emitter connected to each other, and a conductive signal and a non-conductive signal which are differentially turned on and off by a control signal; Transistor and Fifth
And a collector of one of the fourth and fifth transistors is connected to the interconnected emitters of the first and second transistors of the first differential pair transistor. A second differential pair transistor, and a current source connected to the interconnected emitters of the fourth and fifth transistors of the second differential pair transistor, The output signal of the capacitor is fed back to the base of the second transistor, and the one of the fourth and fifth transistors of the second differential pair transistor is turned on by the control signal. By bringing the other transistor out of the fourth and fifth transistors into a non-conductive state, the first transistor is turned off. A sample state mode in which a voltage corresponding to the input signal input to the base of the second differential pair transistor is supplied to the capacitor; A hold state mode for holding the voltage supplied to the capacitor in the sample state mode by causing one of the transistors to be in a non-conductive state and the other of the fourth and fifth transistors to be in a conductive state. A sample and hold circuit configured to execute the first and second transistors of the first differential pair transistor in the hold state mode in response to the control signal. And further comprising control means for making the interconnected emitters low impedance. Sample-and-hold circuit, wherein the door. 2. The control means includes a base responsive to the control signal,
An emitter includes an emitter follower transistor connected to the interconnected emitters of the first and second transistors of the first differential pair transistor, and responsive to the control signal in the hold state mode. When the one of the fourth and fifth transistors of the second differential pair transistor is turned off, the emitter follower transistor of the control means responds to the control signal. 2. The sample and hold circuit according to claim 1, wherein the sample and hold circuit is controlled to a conductive state.