JP2726596B2 - Frame synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit, and more particularly, to a frame synchronization circuit in a high-speed data exchange service suitable for connection between local area networks.

As one of high-speed data exchange services capable of connecting LANs without impairing the high-speed performance of existing local area networks (LANs), SMDS (Switt)
ched Multimegabit Data Service) is known. This SMDS provides a connectionless data exchange service of the megabit / second class, and provides a transmission line and a reception line separately as specified by the Institute of Electrical and Electronics Engineers (IEEE) 802.6 in the United States. A double-bus access protocol is used as a basic protocol.

In this SMDS, DS1 and DS3 are defined as line interfaces. In the case of DS1, as shown in FIG. 3A, user data having 192 bits and 1-bit frame bit F is composed of 24 stages. One octet (one octet is 8 bits) constitutes one multiframe.
The framing octets A1 and A2 having a predetermined fixed pattern are input to the DS1 line interface section of the line interface of the network at a transmission speed of ms, as shown in FIG.
Path overhead identification octet POHI and PLCP
(Physical layer convergence protocol) A total of four octets of the path overhead octet POH are added as headers to the user's data called L2-PDU of 53 octets, and received by the terminal in 8-bit parallel.

As shown in FIG. 4, one multi-frame has a header consisting of 4 octets and a 53-octet L2-PDU of 10 stages (10 frames), and a 576 octet to which a 6-octet trailer is added. It consists of. Here, as shown in FIG. 4, the octet POHI is composed of a frame number and a parity represented by P9 to P0 to identify the octet of the 10 stages (10 frames), and the octet POI.
H is growth octet (fixed to 0) Z4 to Z1, PLC
P path user channel F1, bit inverted parity B1, PLCP path status G1, SIP level 1 control information M2, M1,
And a cycle / stuff counter C1.

[0005] In a terminal receiving received data of a multi-frame format as shown in FIG. 4, it is necessary to detect octets A1 and A2 in a short time in a frame synchronization circuit in order to perform accurate data reception. .

[0006]

2. Description of the Related Art A conventional frame synchronizing circuit, when octets A1 and A2 of each frame in received data input in the format shown in FIG. The position is recognized, and the POHI, which is the frame number, is sequentially taken in. If this octet POHI comes in a sequential order, it is considered that the synchronization is confirmed.

For example, in the frame format of FIG.
If octets A1 and A2 of the first and second frames are detected respectively, the conventional frame synchronization circuit
Octets POH, such as P8, P7, etc. from the third frame
If POHI is detected in a sequential order by taking in I, it is considered that the synchronization is confirmed.

[0008]

However, in the above-mentioned conventional frame synchronization circuit, octets A1 and A2 are set to two.
Since frame synchronization is performed depending on whether the value of the octet POHI, which is the frame number, comes in a sequential order after detecting frames consecutively and recognizing the position of the frame, it takes at least three frames to establish frame synchronization. It takes time to establish synchronization. Also, after the false detection of octets A1 and A2, there is no return to the initial state unless there is one frame.

The present invention has been made in view of the above points,
An object of the present invention is to provide a frame synchronization circuit that solves the above-mentioned problem by detecting the order of frame numbers in parallel with the detection of the frame synchronization signal.

[0010]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in the figure, in the present invention, data is input in units of one frame in which a frame synchronization signal, a frame number, and an error detection code are respectively added to information data, and the frame synchronization signal is input for two consecutive frames. A first detector 11 for detecting that the frame numbers in the input data are input in order without waiting for a detection result of the first detector 11; A second detection unit 12 for performing error detection using the error detection code, and a detection result of the first detection unit 11
And a determination unit 13 for determining a frame synchronization establishment condition based on the detection result of the detection unit 12.

[0011]

According to the present invention, the second detecting section 12 does not wait for the first detecting section 11 to detect the frame position.
Frame order detection and error detection can be performed in parallel with the detection operation of the first detection unit 11.

[0012]

FIG. 2 is a block diagram showing an embodiment of the present invention. In this embodiment, the PLC of the SMDS shown in FIG.
A frame synchronization circuit for detecting the presence / absence of synchronization establishment with respect to received data having a P frame structure, comprising an A1, A2 octet check unit 20, a POHI check unit 30, and an establishment condition determination unit 40. A1, A2 octet check part 2
0 corresponds to the first detection unit 11 and includes an A1 and A2 octet detection circuit 21, a timing adjustment circuit 22, a 57-ary counter 23, and a comparator 24.

The A1, A2 octet detection circuit 21 detects the octet A1 which is a frame synchronization signal from the received data.
(Value is "F6" in hexadecimal) and octet A2 (value is 1
"28") in hexadecimal. The timing adjustment circuit 22 generates a signal (latch signal) for latching the octet POHI. 57-base counter 2
3 is enabled by the output detection signal of the A1, A2 octet detection circuit 21 and starts counting clocks having a frequency equal to the 1-octet transmission frequency. Comparator 24 is 5
When an output signal is input from the 7-base counter 23, A
It is determined whether a detection signal is input from the 1,2 octet detection circuit 21 or not.

The POHI check unit 30 corresponds to the second detection unit 12 and includes a POHI latch circuit 31, a sequential number check circuit 32, and a parity check circuit 33. The POHI latch circuit 31 latches the octet POHI from the received data according to the latch signal from the timing adjustment circuit 22.

Sequential number check circuit 32
Checks whether the frame numbers in consecutive POHIs are sequential. Parity check circuit 3
3 performs a parity check in the POHI. Further, the establishment condition determination unit 40 corresponds to the determination unit 13 and the comparator 2
4. Based on the output results of the sequential number check circuit 32 and the parity check circuit 33, the presence / absence of synchronization establishment is determined. When the result of the synchronization establishment determination is not obtained, the 57-base counter 23 and the sequential number check circuit 32 are respectively set. Reset and return to the initial state.

Next, the operation of this embodiment will be described. The received data is A1, A2 octet detection circuit 21 and PO
Each is supplied to the HI latch circuit 31. The A1 and A2 octet detection circuit 21 detects the same fixed pattern data as A1 and A2 in the received data as A1 and A2 octets, and outputs a detection signal to the timing adjustment circuit 22, the 57-ary counter 23 and the comparator 24, respectively. .

The timing adjustment circuit 22 generates a latch signal at the timing within the input period of the octet POHI following the octet A2 in response to the input of the detection signal, and
The data is supplied to the I-latch circuit 31 to latch the input data, and the enable signal is supplied to the sequential number check circuit 32 to make it operable. As a result, the octet POH is
After I is latched, it is supplied to a sequential number check circuit 32 and a parity check circuit 33.

The octet POHI has a frame number and a parity, and the parity check is performed by the parity check circuit 33 using the parity. The parity check result is supplied to the establishment condition determination unit 40. When the parity is NG, it is determined that the synchronization establishment condition is not satisfied, the 57-ary counter 23 and the sequential number check circuit 32 are reset, and the A1 and A2 octets are detected. State. When the parity is OK, the establishment condition determination unit 40 determines that the synchronization is established only when both of the other two detection results are OK.

On the other hand, the A1, A2 octet detection circuit 21
When the parity check result of the POHI octet after the detection of the first A1 and A2 octets is OK, the operation of the comparator 24 and the sequential number check circuit 32 is performed. That is, the 57-ary counter 23 enabled by the detection signal starts counting clocks having a frequency equal to the octet transmission frequency of the received data, and outputs a count signal to the comparator 24 when 57 clocks have been counted. From the detection of the A1 and A2 octets, the counting signal output time is 57 points from the detected A1 and A2 octets.
This is the point in time when the A1 and A2 octets of the next frame after the octet are input.

When the detection signal from the A1, A2 octet detection circuit 21 is input, the comparator 24 again outputs A1, A2 when the count signal is input from the 57-base counter 23.
It is determined whether the A2 octet detection signal is input from the A1 and A2 octet detection circuit 21, and when the A1 and A2 octet detection signals are input again, the A2 octet detection signal is input for two consecutive frames.
It is determined that 1, A2 octets have been detected, and a detection signal is supplied to the establishment condition determination unit 40. When the A1 and A2 octet detection signals are not input at the time when the counting signal is input, the comparator 24 supplies an NG signal to the establishment condition determination unit 40.

The sequential number check circuit 32 checks whether the frame number in the octet POHI of the next frame input again from the POHI latch circuit 21 has a predetermined sequential relationship with the previously input frame number. . Also, the POHI circuit 3
Octet PO of the next frame latched again by 1
Parity check circuit 33 based on parity in HI
, The parity check is performed again.

The establishment condition judging section 40 includes the parity check circuit 33 and the sequential number check circuit 3 described above.
Only when a detection signal indicating that both of the detection results from the comparator 2 and the comparator 24 are OK is input, it is determined that synchronization has been established, and a synchronization establishment signal is output. If any one is NG, the 57-base counter 23 and the sequential number check circuit 32 are reset, respectively, to return to the initial state of waiting for detection of octets A1 and A2. Hereinafter, the same operation as described above is repeated.

Therefore, according to this embodiment, for example, A of the first frame (first stage) in the multi-frame configuration diagram of FIG.
If the first and A2 octets are detected, the parity check of the octet POHI of the same frame and reading of the frame number P9 are performed, and if the parity is OK, the A1 and A2 of the second frame (second stage) are successively obtained. When the octet is detected, the parity check of the octet POHI of the same second frame is performed, and the sequential check of the frame number P8 and the previous frame number P9 is performed. Therefore, in the present embodiment, it is possible to determine the establishment of synchronization in a minimum of two frames.

[0024]

As described above, according to the present invention, frame order detection and error detection are performed in parallel without waiting for the result of whether or not a frame synchronization signal has been detected for two consecutive frames. Thus, it is possible to determine the establishment of synchronization in the shortest frame, which has been impossible in the past, and thus, it is possible to greatly reduce the synchronization pull-in time as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram of one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a frame.

FIG. 4 is a diagram showing a multi-frame configuration.

[Description of Signs] 11 First detection unit 12 Second detection unit 13 Judgment unit 20 A1, A2 octet check unit 21 A1, A2 octet detection circuit 22 Timing adjustment circuit 23 57-base counter 24 Comparator 30 POHI check unit 31 POHI latch circuit 32 sequential number check circuit 33 parity check circuit 40 establishment condition determination unit

Claims (2)

(57) [Claims] 1. A method for detecting that a frame synchronization signal, a frame number, and an error detection code are input in units of one frame added to information data, and that the frame synchronization signal is input for two consecutive frames. 1 detection unit (1
1) detecting, without waiting for a detection result of the first detection unit (11), that the frame numbers in the input data are input in order, and detecting the error detection code in the input data. A second detection unit (12) for performing error detection based on the first and second detection units; and a frame synchronization establishment condition determination based on the detection result of the first detection unit (11) and the detection result of the second detection unit (12). A frame synchronization circuit, comprising: a determination unit (13) for performing the determination. 2. The method according to claim 1, wherein the determining unit determines whether the first and second detection units receive a predetermined detection result from at least one of the first detection unit and the second detection unit. 2. The frame synchronization circuit according to claim 1, wherein each of said two detectors is reset.