JP2727615B2 - Logic simulation equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation apparatus, and more particularly to a multiprocessor logic simulation apparatus.

[Conventional technology]

Recent advances in VLSI technology have increased the scale of integrated circuits,
With the increase in density, verification work of logic and timing before manufacturing an actual integrated circuit is becoming indispensable in terms of development period and cost.

Initially, the logic simulation was realized by software, but with the increase in the scale and the functionality of the circuit to be verified, a dedicated engine for executing the logic simulation by hardware has been developed and partially put into practical use. These dedicated engines generally employ a multiprocessor system using a plurality of general-purpose 8- to 32-bit microprocessors. The simulation is performed by dividing the circuit under test into a plurality of partial circuits to improve the processing speed. I have.

In the logic simulation method as described above, to improve the processing speed, only the elements whose state values of the input terminals have changed in the circuit under test are evaluated, and the state values are connected only when the output state values change. The selective tracing method propagating to the front is adopted as a simulation algorithm.

[Problems to be solved by the invention]

In the above-described conventional logic simulation apparatus, evaluations are performed in the order of propagation of state values. Therefore, when evaluating a circuit including bidirectional elements, elements must be evaluated until the state values converge, resulting in a large amount of calculation. Needs time. Also, even if a simulation is executed with the evaluation priority added to each element, inter-processor communication occurs asynchronously depending on how circuit data is allocated to each processor,
Each processor has to synchronize each time, and there is a disadvantage that the dead time of each processor increases and the simulation speed decreases.

[Means for solving the problem]

The logic simulation apparatus according to the present invention comprises: means for assigning an evaluation priority to the element according to a delay value of an element constituting the circuit under test; Means for dividing into circuits;
Means for allocating the partial circuit to a processor group for executing a simulation, means for managing a simulation time, means for performing event communication between processors at each time at the time of simulation execution, and means for processor synchronization, Means for evaluating the device according to the priority order.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a logic simulation apparatus according to the present invention. In FIG. 1, a logic simulation apparatus 10 has a processor group 1, a shared memory 2, and a common bus 3, and is connected to a general-purpose computer 20.

The general-purpose computer 20 downloads the circuit data of the circuit to be verified and the input pattern data to the processor group 1, inputs the simulation result from the processor group 1, and stores it in the main memory.

The shared memory 2 is a multi-port memory that can be accessed from any processor in the processor group 1.
The processor group 1 stores flags for synchronization. The common bus 3 is a communication path through which the general-purpose computer 20 and the processor group 1 or any two of the processor group 1 communicate with each other. The processor group 1 inputs the partial circuit group obtained by dividing the circuit to be verified and the input pattern, performs inter-processor communication at each time to simulate the partial circuit group, and sends the result to the general-purpose computer 20.

FIG. 2 is a flowchart showing the operation of the above logic simulation apparatus. In the figure, evaluation priority assigning means 21
Are the elements constituting the circuit under test (1) zero delay element,
Priorities are assigned in the order of (2) bidirectional elements and (3) delay elements.

The means for dividing into sub-circuits 22 divides the circuit under test at the output terminal of the delay element to generate a plurality of sub-circuit data.

The means 23 for allocating the partial circuit to each processor downloads the generated partial circuit data to the processor group 1.

The simulation time management means 24 manages the time when the simulation is executed, and terminates the simulation when the simulation has advanced to the simulation end time. Otherwise, the time is incremented by one unit, and the process is continued.

The communication and synchronization means 25 between the processors monitors the output end of the delay element and determines whether or not a change occurs in the time currently being processed. When a change occurs, communication between processors is performed when the connection destination of the delay element is replaced by another processor. Then, after evaluating the output terminals of all the delay elements, the flag assigned to the own processor in the shared memory 2 is turned on to notify that the inter-processor communication processing has been completed, and the flag assigned to the other processor is set. all
Wait for it to turn ON.

The means 26 for performing element evaluation in accordance with the priority at each time is such that after all the flags assigned to the respective processors in the shared memory 2 are turned on, a change in the state value at the input terminal of the element having a higher priority is performed. The evaluation is performed in order from a certain element, and the output state value is calculated. When a change occurs in the output state value, the state value is propagated to the connection destination.

 The above processing is repeated until there are no more elements to be evaluated.

〔The invention's effect〕

Since the logic simulation apparatus of the present invention assigns priorities to the elements constituting the circuit to be verified and evaluates them in order of priority, it is possible to simulate the circuit including the bidirectional elements without performing unnecessary evaluation. Further, since the synchronization between the processors occurs at most once at each time, there is an effect that the dead time of each processor can be reduced and the simulation speed can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a logic simulation apparatus according to the present invention, and FIG. 2 is a flowchart showing a processing operation. DESCRIPTION OF SYMBOLS 1 ... Processor group, 2 ... Shared memory, 3 ... Common bus, 10
... Logic simulation device, 20 ... General-purpose computer, 21 ... Evaluation priority assigning means, 22 ... Division into partial circuits, 23
... means for allocating a partial circuit to each processor, 24 ... means for managing simulation time, 25 ... means for communication and synchronization between processors, 26 ... means for evaluating elements in accordance with priority at each time.

Claims (1)

(57) [Claims] 1. A means for assigning evaluation priorities to said elements in accordance with delay values of elements constituting a circuit to be verified, and dividing said circuit to be verified into a plurality of partial circuits at an output terminal of said element having a delay value. Means for allocating the partial circuit to a processor group for executing simulation, means for managing simulation time, means for performing processor-based event communication between processors at each time of simulation execution, Means for evaluating the element in accordance with the priority at each time.