JP2727697B2 - Method for manufacturing multilayer printed circuit board - Google Patents
Method for manufacturing multilayer printed circuit boardInfo
- Publication number
- JP2727697B2 JP2727697B2 JP28696889A JP28696889A JP2727697B2 JP 2727697 B2 JP2727697 B2 JP 2727697B2 JP 28696889 A JP28696889 A JP 28696889A JP 28696889 A JP28696889 A JP 28696889A JP 2727697 B2 JP2727697 B2 JP 2727697B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- multilayer printed
- hole
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 〔概 要〕 多層プリント基板の製造方法に関し、 内層導体と多層プリント基板表面の導体層とを接続す
る表面IVH(表面Interstitial Via Hole)が精度良くそ
の深さを制御できて孔開けできる方法を目的とし、 多層プリント基板に表面IVHを形成する方法であっ
て、 多層プリント基板の製品領域と成る以外の領域に予め
モニタ用導体層を中間層基材に形しておき、前記多層プ
リント基板表面より深さの異なる孔を複数個設け、該開
口した孔の深さ方向の先端部が、前記モニタ用導体層を
切断した時点での限界点(Z点)を検知し、 該検知情報に基づいて前記製品領域に表面IVHを孔開
けすることで構成する。DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a method for manufacturing a multilayer printed circuit board, a surface IVH (Interstitial Via Hole) connecting an inner layer conductor and a conductor layer on the surface of the multilayer printed circuit board can accurately control the depth. A method of forming a surface IVH on a multi-layer printed circuit board, in which a monitoring conductor layer is previously formed on an intermediate layer base material in an area other than a product area of the multi-layer printed circuit board. A plurality of holes having different depths from the surface of the multilayer printed board are provided, and a tip end in the depth direction of the opened hole detects a limit point (point Z) at the time of cutting the monitor conductor layer. A surface IVH is formed in the product area based on the detection information.
本発明は多層プリント基板の製造方法に係り、特にIV
H(表面Interstitial Via Hole)を孔開けする時に、孔
の深さが精度良く得られる方法に関する。The present invention relates to a method for manufacturing a multilayer printed circuit board,
The present invention relates to a method for accurately obtaining the depth of a hole when drilling a surface H (Interstitial Via Hole).
多層プリント基板を製造する際、第4図に図示するよ
うに、エポキシ樹脂のような熱硬化性樹脂の基材1の両
面、或いは片方の面にパターンを形成した銅箔2を設け
て中間層基材3を形成し、これらの中間層基材の両面に
プリプレグ4を介在させた状態で表面層銅箔5を設け、
これら中間層基材、プリプレグおよび表面層銅箔をプレ
スにて積層した後、これら表面層銅箔の表面より中間層
基材に設けた銅箔パターンよりなる内層導体に到る表面
IVH6、或いは積層した基材、プリプレグおよび表面層銅
箔を貫通するビアホール7等をドリルにて孔開けした
後、上記表面IVHおよびビアホール等の孔開けした孔内
に無電解銅メッキ層、および電解銅メッキ層よりなる導
体を設けて形成している。When manufacturing a multilayer printed circuit board, as shown in FIG. 4, a copper foil 2 having a pattern formed on both sides or one side of a thermosetting resin substrate 1 such as an epoxy resin is provided and an intermediate layer is formed. A base material 3 is formed, and a surface layer copper foil 5 is provided with a prepreg 4 interposed on both surfaces of the intermediate layer base material,
After laminating these intermediate layer base material, prepreg and surface layer copper foil by pressing, the surface from the surface of these surface layer copper foils to the inner layer conductor composed of the copper foil pattern provided on the intermediate layer base material
After drilling a via hole 7 or the like penetrating the IVH6 or the laminated base material, the prepreg, and the surface layer copper foil, an electroless copper plating layer, It is formed by providing a conductor made of a copper plating layer.
その後、第5図に示すようにこれらの形成した多層プ
リント基板8は、その後所定の寸法に切断して8Aを製品
領域としている。Thereafter, as shown in FIG. 5, the formed multilayer printed circuit board 8 is then cut into a predetermined size to make the product area 8A.
ところで従来、表面IVHをドリルにて孔開けする際に
は、内層導体が形成されているプリント基板の領域に表
面より該内層導体に到らない程度の浅目の孔を孔開けし
た後、徐々に孔の深さを深くした状態でドリルにて孔開
けし、該孔開けしたプリント基板の開口部を肉眼にて目
視して孔開けされた孔の先端部の状態を観察する。そし
て上記孔開けされた孔の先端部が内層銅箔に到達して、
該内層導体の銅箔がドリルにて切断された状態を観察し
て、上記孔の先端部が内層導体に到達しているか否かを
検知して孔開けすべき孔の深さを決定している。By the way, conventionally, when drilling a hole on the surface IVH, after drilling a shallow hole so as not to reach the inner layer conductor from the surface in a region of the printed circuit board where the inner layer conductor is formed, gradually. A hole is formed with a drill while the depth of the hole is deepened, and the state of the tip of the hole is observed by visually checking the opening of the printed circuit board with the hole. And the tip of the perforated hole reaches the inner layer copper foil,
Observe the state where the copper foil of the inner layer conductor is cut by a drill, determine whether the tip of the hole has reached the inner layer conductor and determine the depth of the hole to be drilled. I have.
そして上記ドリルの先端部が内層導体を削った時点
を、ドリルの移動の限界点としてドリルの移動寸法を設
定して、この設定した寸法で表面IVHを孔開するように
している。Then, the time when the tip of the drill cuts the inner layer conductor is set as the limit point of the movement of the drill, and the movement size of the drill is set, and the surface IVH is perforated with the set size.
然し、このような従来の方法では、徐々に孔の深さを
深くしながらドリルにて繰り返し孔開けして、所定の孔
の深さを決定していたので、表面IVHの孔の深さの決定
に多大の手間を要する難点がある。However, in such a conventional method, the hole is repeatedly drilled while gradually increasing the depth of the hole, and the predetermined hole depth is determined. There are difficulties that require a lot of effort to make a decision.
またこのような孔開けする試し孔は、第5図に示すよ
うな多層プリント基板の製品領域8Aに開口していたの
で、製品領域が損傷して製品歩留まりが低下する問題が
ある。Further, since such a trial hole is formed in the product area 8A of the multilayer printed circuit board as shown in FIG. 5, there is a problem that the product area is damaged and the product yield is reduced.
本発明は上記した問題点を除去し、製品領域が損傷し
ないような表面IVHの孔開け方法を目的とする。The present invention is directed to a method of perforating the surface IVH so as to eliminate the above-mentioned problems and not damage the product area.
また一度の孔開け作業で容易に所定の深さの表面IVH
の孔の深さが決定できるようにした多層プリント基板の
製造方法の提供を目的とする。In addition, the surface IVH of a predetermined depth can be easily formed by a single drilling operation.
It is an object of the present invention to provide a method for manufacturing a multilayer printed circuit board in which the depth of the hole can be determined.
上記目的を達成する本発明の多層プリント基板の製造
方法は、多層プリント基板に表面IVHを形成する方法で
あって、 多層プリント基板の製品領域と成る以外の領域に予め
モニタ用導体層を中間層基材に形成しておき、前記多層
プリント基板表面より深さの異なる孔を複数個設け、該
開口した孔の深さ方向の先端部が、前記モニタ用導体層
を切断した時点での限界点(Z点)を検知し、該検知情
報に基づいて前記製品領域に表面IVHを孔開けする。A method of manufacturing a multilayer printed board according to the present invention that achieves the above object is a method of forming a surface IVH on a multilayer printed board, wherein a monitoring conductor layer is previously formed in an intermediate layer in an area other than a product area of the multilayer printed board. A plurality of holes having different depths from the surface of the multilayer printed circuit board are formed on the base material, and the tip of the opened hole in the depth direction is a critical point at the time of cutting the monitoring conductor layer. (Z point) is detected, and a surface IVH is perforated in the product area based on the detection information.
本発明の方法は、プリント基板の製品領域となる以外
の中間層基材の周辺領域にモニタ用導体層を予め形成し
た後、ドリルを用いて、該プリント基板の周辺部に多数
個の表面IVHを一個一個の孔につき、それぞれ孔の深さ
を異ならした状態で孔開けする。The method of the present invention comprises, before forming a monitor conductor layer in a peripheral region of an intermediate layer base material other than a product region of a printed circuit board, and using a drill to form a plurality of surfaces IVH on a peripheral portion of the printed circuit board. Are drilled for each hole with the depth of each hole being different.
このようにして、中間層基材の表面に設けたモニタ用
導体層をドリルの先端部が削る状態の時のドリルの限界
点を検知する。そしてこの検知したドリルの限界点を基
にして製品領域の表面IVHの孔開けをする。このように
すると製品領域内に多数の試し孔が孔開けされることが
無いので、高歩留りの製品が得られる。In this way, the limit point of the drill when the tip of the drill cuts the monitoring conductor layer provided on the surface of the intermediate layer base material is detected. Then, a hole is drilled in the surface IVH of the product area based on the detected limit point of the drill. In this way, a large number of test holes are not formed in the product area, and a product with a high yield can be obtained.
そして更に、上記表面IVHを孔開けする際、ドリルを
ボール盤に多数個設け、この多数個のドリルの各々を、
NC制御装置を用いて一度に深さの異なる孔を孔開けする
ようにすれば、孔開け作業が一回で済み、工程が更に短
縮される。Further, when drilling the surface IVH, a plurality of drills are provided on the drilling machine, and each of the plurality of drills is
If the holes having different depths are formed at once by using the NC control device, the hole forming operation can be performed only once, and the process can be further shortened.
以下、図面を用いて本発明の実施例につき詳細に説明
する。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第1図(a)、および第1図(a)のI−I′線断面
図に示すように、中間層基材3の製品領域8Aとなる以外
の領域、即ち、該中間層基材の周辺領域3Aに予め表面IV
Hを孔開けするためのモニタとなるモニタ用導体層11を
形成して置く。このモニタ用導体層は前記した第4図の
基材の周辺部に銅箔2Aを所定のパターンにエッチングし
て形成すると良い。As shown in FIG. 1 (a) and a cross-sectional view taken along the line II ′ of FIG. 1 (a), a region other than the product region 8A of the intermediate layer base material 3, that is, the intermediate layer base material Surface IV in the surrounding area 3A in advance
A monitor conductor layer 11 serving as a monitor for drilling H is formed and placed. This monitoring conductor layer is preferably formed by etching the copper foil 2A into a predetermined pattern on the periphery of the base material shown in FIG.
そして第4図に示すように、このモニタ用導体層11を
有する中間層基材3の両面にプリプレグを挟んだ状態で
表面層銅箔を上下に設置した後、上記中間層基材3、プ
リプレグおよび表面層銅箔を加圧積層して多層プリント
基板8とする。Then, as shown in FIG. 4, after the surface layer copper foil is placed up and down with the prepreg sandwiched on both surfaces of the intermediate layer base material 3 having the monitor conductor layer 11, the intermediate layer base material 3, the prepreg Then, the surface layer copper foil is laminated under pressure to form a multilayer printed circuit board 8.
このようにして積層された多層基板の周辺部には、前
記した製品領域に於いて内層導体(所定パターンの銅箔
2)が形成されている位置迄の深さにlに該当する位置
にモニタ用導体層11が形成されている。The peripheral portion of the multilayer substrate thus laminated is monitored at a position corresponding to 1 at a depth up to the position where the inner layer conductor (copper foil 2 of a predetermined pattern) is formed in the product area. Conductor layer 11 is formed.
次いで第2図(a)、および第2図(a)のII−II′
線に示すように、このモニタ用導体層11が形成されてい
る上よりドリルを用い、該ドリルの下方向の移動方向の
寸法を順次大にし、表面より孔の先端部迄の深さを順次
深くした状態でドリルにて孔の深さの異なる孔12A,12B,
12C……を穿孔し、この孔を穿孔した部分を肉眼、或い
は顕微鏡を用いて観察して、前記ドリルの先端部がモニ
タ用導体層を切断した最適の状態の深さの位置を検知
し、この時のドリルの移動限界点即ちZ点を検知する。Next, FIG. 2 (a) and II-II 'of FIG. 2 (a)
As shown by the line, a drill is used from above the monitor conductor layer 11 is formed, the size of the drill in the downward moving direction is sequentially increased, and the depth from the surface to the tip of the hole is sequentially reduced. Holes 12A, 12B,
12C .... perforated, and visually observed the portion perforated with this hole or using a microscope, to detect the position of the depth of the optimal state where the tip of the drill cut the monitoring conductor layer, At this time, the movement limit point of the drill, that is, the Z point is detected.
そしてそのZ点迄移動できるようにドリルの移動方向
を設定したドリルを用いて製品領域内の多層基板に孔開
けを行う。Then, a hole is made in the multilayer substrate in the product area by using a drill in which the direction of movement of the drill is set so as to move to the Z point.
このようにすれば、従来の方法に於けるような多数の
試し孔を孔開けする必要が無くなり、製品領域が試し孔
の孔開けによって損失する欠点が除去でき、プリント基
板の製品歩留まりが向上する。In this way, it is not necessary to form a large number of test holes as in the conventional method, and the disadvantage that the product area is lost due to the formation of the test holes can be eliminated, and the product yield of the printed circuit board is improved. .
またその他の実施例として、第3図(a)および第3
図(a)のIII−III′断面図の第3図(b)、および第
3図(a)のIV−IV′線断面図の第3図(c)に示すよ
うに、上記モニタ導体層は、表面よりそれぞれ深さを
l1,l2のように異ならせて形成した導体層11A,11Bを形成
場所を異ならせて二列、或いはそれ以上の複数列設ける
ようにすると、製品領域で表面より深さの異なる内層導
体を有する多層基板に応用できる。FIG. 3 (a) and FIG.
As shown in FIG. 3 (b) in a sectional view taken along the line III-III 'in FIG. 3 (a) and FIG. 3 (c) in a sectional view taken along the line IV-IV' in FIG. Is the depth from the surface
l 1, conductor layer 11A which different allowed formed as l 2, two rows at different 11B forming location, or more when such a plurality of rows provided, different inner conductor depths from the surface in the product region of Can be applied to a multilayer substrate having
またボール盤に前記ドリルを複数個設け、この各々の
ドリルをそれぞれ深さの異なるようにNC制御装置等を用
いて制御して、孔を開口すると更に能率的にドリルで内
層導体迄孔開けすべき孔の深さ方向の寸法が短時間で決
定できる。In addition, a plurality of the drills are provided on a drilling machine, and each of the drills is controlled by using an NC control device or the like so as to have different depths, and when the holes are opened, the drills should be more efficiently drilled up to the inner conductor. The size of the hole in the depth direction can be determined in a short time.
〔発明の効果〕 以上の説明から明らかなように本発明によれば、表面
層より内層導体迄の表面IVHが所定の深さに精度良く制
御されて孔開けでき、従来のように試し孔の孔開けによ
って製品領域が不良となる問題が除去され、多層プリン
ト基板の製造歩留まりが向上する効果がある。[Effects of the Invention] As is clear from the above description, according to the present invention, the surface IVH from the surface layer to the inner layer conductor can be accurately drilled to a predetermined depth to form a hole. The problem that the product area becomes defective due to the perforation is eliminated, and the production yield of the multilayer printed circuit board is improved.
第1図(a)および第1図(b)は、本発明の方法に用
いる多層プリント基板の平面図および断面図、 第2図(a)および第2図(b)は、本発明の工程を示
す平面図および断面図、 第3図(a)、第3図(b)および第3図(c)は本発
明の方法の他の実施例を示す平面図および断面図、 第4図は多層プリント基板の製造方法の説明図、 第5図は従来の方法に於けるプリント基板の平面図であ
る。 図において、 1は基材、2,2Aは銅箔、3は中間層基材、3Aは周辺領
域、4はプリプレグ、5は表面層銅箔、6は表面IVH
(中間層ビアホール)、7はビアホール、8は多層プリ
ント基板、8Aは製品領域、11,11A,11Bはモニタ用導体
層、12A,12B,12C,12Dは孔を示す。1 (a) and 1 (b) are a plan view and a sectional view of a multilayer printed board used in the method of the present invention, and FIGS. 2 (a) and 2 (b) are steps of the present invention. FIGS. 3 (a), 3 (b) and 3 (c) are plan and sectional views showing another embodiment of the method of the present invention, and FIG. FIG. 5 is an explanatory view of a method for manufacturing a multilayer printed circuit board, and FIG. 5 is a plan view of a printed circuit board in a conventional method. In the figure, 1 is a substrate, 2, 2A is a copper foil, 3 is an intermediate layer substrate, 3A is a peripheral region, 4 is a prepreg, 5 is a surface layer copper foil, and 6 is a surface IVH
(Intermediate layer via hole), 7 is a via hole, 8 is a multilayer printed circuit board, 8A is a product area, 11, 11A and 11B are monitor conductor layers, and 12A, 12B, 12C and 12D are holes.
Claims (1)
法であって、 多層プリント基板(8)の製品領域(8A)と成る以外の
領域に予めモニタ用導体層(11)を中間層基材(3)に
形成しておき、前記多層プリント基板(8)表面より深
さの異なる孔(12A,12B,12C,12D…)を複数個設け、該
開口した孔の深さ方向の先端部が、前記モニタ用導体層
(11)を切断した時点での限界点(Z点)を検知し、 該検知情報に基づいて前記製品領域(8A)に表面IVHを
孔開けすることを特徴とする多層プリント基板の製造方
法。1. A method for forming a surface IVH on a multilayer printed circuit board, the method comprising: forming a monitor conductor layer (11) in an area other than a product area (8A) of the multilayer printed circuit board (8) in advance; (3), a plurality of holes (12A, 12B, 12C, 12D...) Having different depths from the surface of the multilayer printed circuit board (8) are provided. Detecting a limit point (Z point) at the time of cutting the monitor conductor layer (11), and forming a hole on the surface IVH in the product area (8A) based on the detected information. Manufacturing method of printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28696889A JP2727697B2 (en) | 1989-11-02 | 1989-11-02 | Method for manufacturing multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28696889A JP2727697B2 (en) | 1989-11-02 | 1989-11-02 | Method for manufacturing multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03148197A JPH03148197A (en) | 1991-06-24 |
| JP2727697B2 true JP2727697B2 (en) | 1998-03-11 |
Family
ID=17711291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28696889A Expired - Fee Related JP2727697B2 (en) | 1989-11-02 | 1989-11-02 | Method for manufacturing multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2727697B2 (en) |
-
1989
- 1989-11-02 JP JP28696889A patent/JP2727697B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03148197A (en) | 1991-06-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |