JP2727856B2 - Large-scale memory configuration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for constructing a large-scale memory for improving the yield of large-scale memories by improving the utilization rate of blocks in a RAM chip and for constructing a large-scale memory with high reliability. It is.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing a basic unit of a memory for exchanging and recording serial data with an external system. 10, 7 is a shift register, 8 is an input / output terminal, 9-1 to 9-N are flip-flops constituting the shift register, 11 is a chip group, 12-
A1 to 12-KN are RAM (random access memory)
It is a chip. In the chip group 11, chips belonging to the same row (eg, 12-A1 to 12-AN) are connected to the same address line. Therefore, when a certain address is given, the corresponding R of each column (column 1 to column N)
AM chips are selected and accessed concurrently.

First, a case where data is read from the chip group 11 will be described. For example, if the chip 12-A1 is selected by the supplied address,
The 1-bit data at the designated address of A1 is taken out to the corresponding flip-flop 9-1 of the shift register 7. Similarly, the other chips 12-A2, 12-A3,...
1-bit data is also extracted from the 12-AN to the corresponding flip-flop.

[0004] When data is available in the flip-flops 9-1 to 9-N, the shift register 7 is operated so that the data of each flip-flop is shifted toward the input / output terminal 8. That is, data extracted in parallel (in parallel) from each chip is serially extracted from the input / output terminal 8 (arrow B).

When writing data to the chip group 11, data to be written is input serially from the input / output terminal 8 as indicated by an arrow A, bit by bit. Then, every time one bit is input, the shift register 7 is operated so that data is sent to the front flip-flop. When the data is prepared in each flip-flop, the data is simultaneously written to the corresponding chip selected by the address line.

FIG. 12 is a diagram showing a basic configuration of a conventional memory unit. The reference numerals correspond to those in FIG.
7-M is a shift register, and 11-1 to 11-M are chip groups. The memory unit is composed of a number of basic units as described above. In particular, when configuring a large-scale memory, the number of basic units is enormous.

By the way, in the stage of manufacturing a memory on a silicon wafer, a defective portion may be generated for some reason. This cannot be avoided at the current technology level. At the defective portion, data recording is not performed as instructed (eg, when “1” can be written, “1” is not correctly written in the memory cell). In the case of a small-scale memory, it is also possible to use the remaining normal portion without using the defective portion of the wafer.

However, when a large-scale memory (a form such as a wafer-scale memory in which one functional module is constituted by a whole silicon wafer) is to be manufactured, a defective portion is inevitably included in the area. Become. Therefore, the most important thing in manufacturing a large-scale memory is to execute a marching pattern test or the like to find a defective portion and configure a memory circuit while avoiding the defective portion. Then, in order to improve the yield at the time of manufacturing, it is desired to reduce as much as possible the normal part that is wasted by the way when taking the avoidance measures.

(Prior Art for Avoiding Defects) FIG. 9 shows an example of a method for configuring a large-scale memory according to the prior art. The reference numerals correspond to those in FIG. 10, Y is a spare chip, and H-1 and H-2 are a group of row chips. The number of RAM chips arranged in an array is 3 per chip group in a row.
A redundant configuration of −out of −4 (a configuration in which an extra one is added where three are required to provide a total of four). Chips containing defects are indicated by crosses in the figure, but they are separated by selecting a path at the time of manufacturing or shipping test of the memory unit, and only normal chips are actually wired and operated.

That is, a row chip group (for example, H-1) including one defective chip is switched to a spare chip group by switching by a path shift as shown. The row chip group H-2 including two defective chips cannot provide the three chips required in this case, so that the entire row chip group H-2 is bypassed.

According to this method, defects can be separated only in chip units. Therefore, when a chip is composed of 1 M bits, only 1 M bit causes all 1 M bits to be wasted, resulting in an overall yield. It has the drawback that it is difficult to go up. In addition, the process of switching the route by shifting or bypassing becomes complicated, which increases the cost.

FIG. 11 is a diagram showing another configuration method of a large-scale memory according to the prior art. Reference numerals correspond to those in FIG. 9, 10A is a chip data selection circuit, and 12-1 to 12-.
3 is a chip, 15 is a block, 16 is a defective block, L
Is a data line. Each chip 12- in the chip group 11
, Y are divided into blocks each having a fixed size (for example, 1 Kbyte). Then, the block containing the defect is replaced with a corresponding normal block of the spare chip as indicated by an arrow. At the time of reading or writing at an address indicating a defective block,
The chip data selection circuit 10A switches and connects the data line L to the spare chip Y.

In this method, as compared with the method of FIG. 9 described above, defects can be avoided in units of blocks, which are finer units than chips, so that wasted RAM capacity is reduced and the yield is improved. However, if there are more defective blocks than the number of spare chips (one in FIG. 11) in the same row (eg, the fifth row from the top in FIG. 11)
Cannot be replaced.

[0014]

[Problems to be Solved] (Problems) The above-mentioned conventional large-scale memory configuration method has the following problems. The first problem is that when two or more defective blocks are included in a certain word-length block group, the entire word-length block group is cut off. The point is that the number is wasted. A second problem is that since the configuration at the basic unit stage is not a redundant configuration, if one basic unit fails for any reason, the entire large-scale memory becomes unusable.

(Explanation of Problems) First, the first problem will be described with reference to FIG. FIG.
FIG. 3 is a diagram illustrating a RAM. The reference numerals correspond to those in FIG.
12-4 to 12-6 are chips, and 17 is a word-length block group. Since there are two defective blocks in the word-length block group 17, the entire word-length block group 17 is separated as unusable. At this time, the four normal blocks belonging to this group are also separated by being accompanied. I will be. If the word length is long, the number of wasteful normal blocks also increases. For example, if the word length is 32 bits,
If there are two defective blocks (corresponding to 2 bits), the remaining 30 normal blocks are also cut off at the same time.

Next, as a second problem, a large-scale memory is composed of many basic units as shown in FIG. Therefore, if the configuration at the basic unit stage is not a redundant configuration, even if a certain basic unit fails, there is no substitute for it. A basic unit failure occurs when a defective block exceeding the number of spare blocks is included, or when a shift register for input / output is defective, and so the entire large-scale memory cannot be used due to the cause alone. . An object of the present invention is to solve the above problems.

[0017]

In order to solve the above-mentioned problems, in a large-scale memory configuration method according to the present invention, a large-scale memory is composed of a plurality of memory groups having a K-out-of- (K + 1) redundant configuration. A single memory group is composed of a plurality of chips and a shift register having a loop structure having a redundant structure for inputting / outputting to / from each chip, and address distribution switching in which a defective block in the chip can be arbitrarily weighted. After that, the defective block is replaced with a block of a spare chip after being distributed to a block group having a different address.

[0018]

[Operation] When a large-scale memory is configured, a large-scale memory is configured by assembling a plurality of memory groups each including a plurality of chips and a shift register for performing input / output to each chip. By constructing the shift register in a loop, the shift direction at the time of writing / reading becomes the same, the circuit constituting the shift register is simplified, and the encoder / decoder of the SEC-DED code is used as shown in FIG. The multiplexer required to connect the
There is a merit that it can be configured in one direction (in FIG. 13, (a) shows the case of decoding, (b) shows the case of coding, 7 is a shift register, 8 is an input / output terminal, 9
-1, 9-2 are flip-flops, 10-1, 10-2
Is a gate, 12-1 and 12-2 are chips, 40 is an encoder / decoder, 41 is an adder, and 42 and 43 are multiplexers). Another advantage is that a configuration having a spare shift register can be easily adopted.

Then, those memory groups are replaced with K-out-of having one extra spare memory group.
-(K + 1) redundant configuration. Further, in each memory group, the shift register has a redundant configuration (for example, K-out).
-Of- (K + 1) redundant configuration).

Further, in each chip of the memory group, the address distribution switching which can arbitrarily assign a weight is performed.
Defective blocks are cleverly distributed to different addresses and replaced with blocks from spare chips.

When a large-scale memory is configured in this manner, the components are divided into several layers, and a redundant configuration is adopted in each layer. Therefore, a large-scale memory (eg, a wafer-scale memory) ) It can prevent the whole from becoming unusable. Further, the number of normal blocks wasted due to the separation of the defective block can be reduced.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a diagram showing a wafer to which the present invention is applied. Typically, memories are formed using a fraction of a single silicon wafer, but larger memories have larger areas. As the largest, it is considered that one wafer is used as one large-scale memory (wafer scale integration file memory system). FIG. 2 illustrates such a wafer-scale memory. 2, 1 is a wafer, 2 is a memory unit, 3 is a loop unit, 4 is a control unit, 4-1 is an input / output control circuit, 4-2 is a redundant configuration switching circuit, 4-3 is a test control circuit, 7 Is a shift register, and 12 is a chip.

The input / output control circuit 4-1 controls input / output of data to / from the memory unit 2. The test control circuit 4-3 includes:
This is a circuit for detecting a defective portion, and tests the operation of each storage unit of the memory unit 2 to check whether or not it is defective. The redundant configuration switching circuit 4-2 is a circuit for performing switching when using the redundant unit in the memory unit 2 employing the redundant configuration. The redundant configuration is shown in FIGS.
Will be described later.

FIG. 1 is a diagram showing a basic unit of a memory according to the present invention for recording data in word units. In FIG. 1, 7 is a shift register, 8 is an input / output terminal, 9-1, 9-2, 9-3, 9-N are flip-flops, 10-1, 10-2, 10-N are gates, 11 is Chip group, 12-1, 12-2, 12-3, ..., 12-N
Denotes a RAM (random access memory) chip.

First, a case where data is read from the chip group 11 will be described. One-bit data is supplied from the chip 12-1 to the flip-flop 9 through the gate 10-1.
-1 is taken out. Similarly, 1-bit data is taken out from another chip to the corresponding flip-flop. When the data is available in the flip-flops 9-1 to 9-N, the shift register 7 is shifted so that the data of each flip-flop is shifted toward the input / output terminal 8.
To work. That is, data extracted in parallel (in parallel) from each chip is extracted from the input / output terminal 8 in the form of a series (arrow B).

When data is to be written to the chip group 11, data to be written is input from the input / output terminal 8 as shown by an arrow A one bit at a time in a series. Then, every time one bit is input, the shift register 7 is operated so that data is sent to the front flip-flop. When data is collected in each flip-flop, the data is written to the corresponding chip through the corresponding gate.

FIG. 3 is a diagram showing an example of a redundant configuration of the memory unit employed in the present invention. In FIG. 3, 7-1 and 7-
2, 7Y is a shift register, 11-1 and 11-2 are chip groups, and 13-1, 13-K and 13Y are groups.
In this method, a wafer (large-scale memory) is made into a memory group (hereinafter simply referred to as a “group”), which is a group of several chip groups, and a plurality of these collectively constitute a large-scale memory (wafer-scale memory). And take a redundant configuration at the group level.

In the present invention, basically, K-out of- (K
+1) Adopt a redundant configuration. That is, if K components are required, (K + 1) components are prepared, and one extra
It is configured so that there is one. In FIG. 3, Y (preliminary) is included in the code.
Those marked with are provided extra for redundancy.

First, focusing on the group 13-1, since it is composed of two chip groups of the chip groups 11-1 and 11-2, the shift registers are also 7-1 and 7-.
Two is enough. However, a shift register 7Y is provided so that if one of the shift registers fails, the replacement can be performed. Similarly, one extra shift register is provided for each group.

When the entire wafer (large-scale memory) is configured, an extra group 13Y is provided in addition to the groups 13-1 to 13-K that exhibit the capacity and performance that this wafer aims at. . If group 13-
In the case of 1 to 13-K alone, if any of the groups fails, the entire wafer will not exhibit the desired capacity and performance, and the use of this wafer must be abandoned. However, if the spare group 13Y is provided, it is possible to replace the failed group by that, and the whole wafer is not wasted.

FIG. 5 is a diagram showing an application example of the error correction code in the basic unit of the memory. 7 is a shift register, 8 is an input / output terminal, 9 is a flip-flop, 10 is a gate, 12 is a chip, 12Y-1 to 12YZ are spare chips, 18 is a word length block group, and 19 is an information bit chip. A group 20 is a chip group for inspection bits. The chips 12Y-1 to 12Y-Z are, as described below,
This is a chip provided for a redundant configuration.

When the word length is 32 bits, the information bit chip group 19 is essentially composed of 32 chips.
However, an extra chip is provided for some of the chips (for example, 8 chips). For example, chip 12Y
-1 for some chips to the left
It is provided for redundancy. The range of chips provided can be determined by observing the connection with the gate 10. The chip 12Y-1 is connected to all the gates 10 corresponding to the chip 12 on the left. From this, it can be seen that these are provided for the chips 12.

If there is a defect in the block 21 of the leftmost chip, the block 22 belonging to the same horizontal row as the block 21 among the blocks of the redundant chip 12Y-1
Is used as an alternative. Specifically, when the block 21 is accessed, an alternative is made by switching the connection line to access the block 22.

The check bit chip group 20 is equivalent to an error correction code.
A DED code (single error correction double error detection code) can be adopted. The SEC-DED code is used to relieve a soft error by alpha rays when operating a large-scale memory and to relieve an overlap defect described later. Note that a soft error is an error in which information retained by a memory cell is affected by the energy of alpha rays emitted from a radioactive substance or the like contained in a very small amount in a package of a memory chip, and information is inverted. .

The chips 12Y-Z are used as spares when any one of the chips 12 of the test bit chip group 20 fails. The number of bits of the inspection bit chip group 20 (chip 12
) Depends on the number of bits (number of chips 12) of the information bit chip group 19. For example, when the number of information bits is 32, the number of check bits is 7 bits. The redundant configuration and the defect relief in the basic unit are performed as described above.

However, in the block replacement method as described above, as described with reference to FIG. 4, two or more in the horizontal row direction (word length direction) in a chip group covered by one redundant chip. If there is a defect, all normal blocks belonging to the same column are sacrificed. Therefore, in the present invention, when accessing the memory, a special address distribution switching is performed so that apparently the number of defects contained in one horizontal row is reduced to 1 or less as much as possible. Next, it will be described.

(Address Distribution Switching) FIG. 7 shows a RAM in which address distribution switching is to be performed. In FIG. 7, C _{0 to} C _Y are chips, 15 is a normal block, 16 is a defective block, 31 is an adder, and W _{0 to} W
_Y is the weight to be added to the address given for access. The chip _CY is a spare chip provided for a redundant configuration. As shown in FIG. 7, it is assumed that the address of the RAM is set to “0” in the address of the bottom horizontal row, and increases as going to the upper row.

The address given for access (given from the lower left in FIG. 7) is applied to an adder 31 provided for each chip, where weights W _{0 to} W _Y appropriately determined are added. Is added. Then, the address block obtained by the addition is accessed. Therefore,
Even if an instruction is issued to access a certain address, an address different from the instruction is changed for each chip depending on the added weight. That is, the addresses are switched in a distributed manner.
This will be described in detail with reference to FIG.

FIG. 8 is a diagram for explaining the mechanism of the address distribution switching. The reference numerals correspond to those in FIG. It is assumed that the weight given to each chip is 0, 1, 2, 3, 4, 5 as shown in the figure. FIG. 8A shows the state before the address distribution switching, and FIG. 8B shows the state after the address distribution switching.

First, FIG. 8A will be described. Assuming that "2" is given as an address to be accessed,
Since the weight is 0 in the chip C ₀ , the block of the address 2 is accessed by 2 + 0 = 2. However, since the weight in the chip C ₁ is 1, 2 + 1 = 3, block address 3 is accessed. That is, as indicated by the dotted arrows, blocks having different addresses by the weight are accessed. The other chips are similarly accessed. In the chips C ₄ and C _Y , as shown by a block surrounded by a dotted line, the data overflows beyond the actual highest address “5”, but in that case, it jumps back to the lowest address “0” and overflows. Treat them as if they were going forward.

FIG. 8B shows a case where blocks to be actually accessed are rearranged into one horizontal row when weighting is performed. Incidentally, the block at the tip of the dotted arrow in FIG.
Are aligned in columns. That is, the blocks belonging to each address are apparently as shown in FIG. In this way, in FIG. 8A, the block belonging to address 4 has four defective blocks, but in FIG. 8B, three of them are distributed to other addresses. It was done.

Conventionally, when two defective blocks are included, all the blocks in one horizontal row are cut off.
By performing the address distribution switching, one of the two can be changed to a column that can be corrected by one spare block by transferring one of the two columns to another column that does not include any defect. ). Thus, the number of wasteful normal blocks can be reduced. After the address distribution switching, if one defective block is included in one horizontal row (one word), the defective block is regarded as a chip C.
_Replace with a normal block belonging to _Y. For example, chip C
₁ defective block 33, the chip C _Y normal block 3
Replaced with 4.

[0043] However, when only the block belonging to the chip C _Y contains defects, does not do any of the replacement process. In this case, the defective block is relieved by the above-described SEC-DED code using the check bit chip group of FIG. Actually, when data is written in a word including a defective block, correct data is not stored in the defective block, but the check bits generated by the SEC-DED encoder are stored in the check bit chip group. By decoding this at the time of reading, the data of the defective block portion is also correctly restored and read.

In the present invention, when performing the address distribution switching, the value of the weight is not fixed to some specific value, but can be arbitrarily changed. Then, if it is not possible to perform a certain weighting, and try again with another weighting, a combination of weights such that the defective blocks are dispersed as desired is obtained,
Address distribution switching is performed by the weight. This is performed by the address distribution switching control circuit shown in FIG. The address distribution switching control circuit is the redundant configuration switching circuit 4- in FIG.
2 included.

In FIG. 6, 30 is a defect map address generation circuit, 31 is an adder, 32 is a defect map, 33 is a control circuit, 34 is a weight pattern map, 35 is a weight counter, 36 is a weight pattern map address generation circuit, 37
Is an address distribution switching checker.

The clock applied to the control circuit 33 is for synchronizing the operation. When the start signal is supplied, an instruction to generate an address is issued to the defect map address generation circuit 30 and the weight pattern map address generation circuit 36. Defect map address generation circuit 30
Generates an address for input from the lower left of FIG. The weight pattern map address generation circuit 36 generates an address for selecting a weight to be used this time from the weights stored in the weight pattern map 34 in advance.

The weights W _{0 to} W _{Y of} FIG. 7 are provided from the weight pattern map 34. The address R obtained by adding the two by the adder 31 is used to perform address distribution switching.
Access AM. Then, apparently, the state after the defective blocks are dispersed (that is, the state of FIG. 8B).
Is recorded in the defect map 32.

The weight counter 35 counts the number of defective blocks included in one horizontal row (word) of the defect map.
The address distribution switching checker 37 checks whether the number of defective blocks existing in one horizontal row is 1 or less. If all the values are 1 or less, the weight used at that time is sufficient, and if it is not good, it is necessary to start over with another weight. The result of the check is reported to the control circuit 33. When the number of spare chips is one, the number of defective blocks that can be included is "1 or less". If there are two spare chips, it is "2 or less".

After performing the address distribution switching as described above,
By relieving defective blocks by the block replacement method described above, the number of uselessly discarded normal blocks can be reduced.

[0050]

As described above, according to the large-scale memory configuration method of the present invention, the components are divided into several layers, and a redundant configuration is adopted in each layer. The entire scale memory (eg, wafer scale memory) is not disabled. Further, the number of normal blocks wasted due to the separation of the defective block is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic unit of a memory according to the present invention.

FIG. 2 shows a wafer to which the present invention is applied.

FIG. 3 is a diagram showing an example of a redundant configuration of a memory unit employed in the present invention;

FIG. 4 is a diagram showing a RAM;

FIG. 5 is an application example of an error correction code in a basic unit of a memory.

FIG. 6 is an address distribution switching control circuit.

FIG. 7 is a RAM for performing address distribution switching
Figure showing

FIG. 8 is a diagram for explaining a mechanism of address distribution switching;

FIG. 9 shows a method of configuring a large-scale memory according to the related art.
Figure showing an example

FIG. 10 is a diagram showing a basic unit of a conventional memory.

FIG. 11 is a diagram showing another configuration method of a large-scale memory according to the related art.

FIG. 12 is a diagram showing a basic configuration of a conventional memory unit.

FIG. 13 shows a basic unit of the memory of the present invention and SEC-
Diagram showing connection between DED code and encoder / decoder

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Memory part, 3 ... Loop part, 4 ... Control part, 4-1 ... Input / output control circuit, 4-2 ... Redundant structure switching circuit, 4-3 ... Test control circuit, 7, 7-1 , 7-2: shift register, 8: input / output terminal, 9, 9-1, 9-2,
9-3, 9-N... Flip-flop, 10, 10-1,
10-2, 10-N gate, 11, 11-1, 11-
2, a chip group, 12, 12-1, 12-2, 12-3,
12-N: chip, 13-1, 13-K: group, 1
3Y: spare group, 14: RAM, 15: block,
16: defective block, 17, 18: word length block group

Claims (1)

(57) [Claims] 1. A large-scale memory is stored in K-out-of- (K
+1) A single memory group is configured by a plurality of memory groups having a redundant configuration, and a single memory group is configured by a shift register having a redundant configuration configured to perform input / output to / from each chip. A large-scale memory configuration method, comprising : distributing defective blocks within a group of blocks having different addresses by address distribution switching in which weighting can be arbitrarily performed; and replacing the defective block with a block of a spare chip.