JP2727866B2 - Frequency synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer comprising a monolithic semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, with the development of cordless telephones, mobile communication, and the like, semiconductor integrated circuits of frequency synthesizers constituting tuners, down converters, and the like of the above-described writing apparatus have been developed.

[0003] This type of frequency synthesizer includes a frequency divider that divides an oscillation signal of a voltage controlled oscillator (VCO) at a predetermined frequency division ratio, and a phase locked loop (PLL). In general, the frequency division ratio of the frequency divider depends on the system used. For example, for a certain system, the oscillation signal from the VCO is frequency-divided to about 1/6,
Output as the local oscillation signal of the next stage down converter,
Further, the local oscillation signal is frequency-divided to about 1/10 to obtain an input signal of the PLL. 1/6 and 1 / of the above dividing ratio
10 differs depending on the target system.

When this type of conventional frequency synthesizer is constituted by a monolithic semiconductor integrated circuit, a circuit design for realizing a desired frequency division ratio and a block design corresponding to a system to be used are performed each time. In manufacturing a semiconductor integrated circuit, a photoresist mask used in a diffusion step and a wiring step has been created.

In recent years, in particular, in order to diversify systems, diversify required performance and functions, etc., a variety of frequency synthesizers have been required.

[0006]

The conventional frequency synthesizer described above has a drawback that the development period is lengthened and the development cost is increased because it is necessary to perform from circuit design to mask design for each target system. Was.

[0007]

Frequency synthesizer of the present invention, in order to solve the problem] in the frequency synthesizer comprising a monolithic semiconductor integrated circuit, a phase locked loop circuit and the high-speed blow
Tsu each level shift circuit of at least one high-speed operation for the D-type flip-flop and the high-speed operation for click, slow
At least one D type for low speed operation for each block
Flip-flop and T-type flip-flop for medium speed operation
An integrated circuit substrate in which a base circuit having a low-speed operation level shift circuit and a logic configuration NOR circuit is generated in advance, the phase-locked loop circuit and the high-speed operation D-type flip-flop on the integrated circuit substrate during a wiring process And said low speed
The circuit includes an operation D-type flip-flop, the T-type flip-flop, and a wiring layer generated by designating a connection between the level shift circuit and the NOR circuit.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the frequency synthesizer according to the present invention.

As shown in FIG. 1, the frequency synthesizer of this embodiment includes a high-speed block 101 including a preamplifier PA1, D-type flip-flops DFF1 to DFF3 for high-speed operation, and level shift circuits LS1 to LS3. D-type flip-flops DFF4 to DFF6 for operation
A low-speed block 102 composed of level shift circuits LS4 to LS6, NOR circuits N1 to N4 for logic configuration, T-type flip-flops TFF1 to TFF4 for medium speed operation, and a buffer amplifier A1, and a phase locked loop circuit P
LL1 and a power supply circuit REG for supplying power to each of the above circuits
And an integrated circuit substrate 1 that generates a PLL block 103 composed of

Next, the operation of this embodiment will be described.

The D-type flip-flops DFF1 to DFF3 of the high-speed block 101 are high-speed circuit blocks that consume relatively large current because they handle relatively high-speed signals in the first stage. These D-type flip-flops DFF1 to DFF3
Returns the output to the input inside the block,
It can be used as a high-speed T-type flip-flop. When the input signal is fixedly divided into 1/2, 1/4, 1/8, etc., D-type flip-flops DFF1 to DFF3
Are used as T-type flip-flops. The T-type flip-flop performs 1/2 frequency division per stage. At this time, since the output level needs to be shifted for connection to the next stage, the level shift circuits LS1 to LS3 are used.

The D-type flip-flops DFF4 to DFF6 of the low-speed block 102 and the T-type flip-flop TFF
1 to TFF4 are low-speed circuit blocks that consume relatively little current to handle relatively low-speed signals divided by the D-type flip-flops DFF1 to DFF3 of the high-speed block 101. Similarly to the high-speed block 101, the D-type flip-flops DFF4 to DFF6 can be used as T-type flip-flops by feeding back outputs to inputs inside the block. At this time, since the connection to the next stage requires a shift of the output level, the level shift circuits LS4 to LS6 are used. In order to select an arbitrary frequency division ratio, the logic is formed by NOR circuits N1 to N4. To prevent the feedback signal line from becoming long, the NOR circuits N1 to N4
Are arranged adjacent to the D-type flip-flops DFF4 to DFF6. If further frequency division is required, T-type flip-flops TFF1 to TFF4 are used.

FIG. 2 is a block diagram showing an example of a circuit of the frequency synthesizer constituted by connecting the components of each block of FIG.

In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. Also, in FIG. 1, solid arrows indicate signal flows.

This frequency synthesizer converts the input signal to 1
It comprises a 1/6 frequency divider 11 for frequency division to / 6 and a 1/13 frequency divider 12 for frequency division to 1/13. 1 /
The 6-frequency divider 11 includes D-type flip-flops DFF1 to DF
F3, a level shift circuit LS1, and a buffer amplifier A1. The 1/13 divider 12 is NO
R circuits N1 to N3 and D flip-flops DFF4
DFF5 and T-type flip-flops TFF1 to TFF4
It is comprised including.

The input signal IN is first supplied to the preamplifier PA1.
Amplified by Next, the frequency is divided by 1/6 by the three-stage D-type flip-flops DFF1 to DFF3 of the 1/6 frequency divider 11. The output of the D-type flip-flop DFF3 is level-shifted by the level shift circuit LS1, and
13 is supplied to the frequency divider 13 and the buffer amplifier A
1 and output as an output signal OUT.

The signal A input to the 1/13 frequency divider 12 is
The frequency is divided by 1/13 by D-type flip-flops DFF4 and DFF5 and T-type flip-flops TFF1 and TFF2. The output B of the 1/13 frequency divider 12 is input to the phase locked loop PLL1. The phase locked loop PLL1 is
The phase comparison with the reference frequency signal R is performed and output to the loop filter via the loop filter outputs F1 and F2.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

The present embodiment is different from the first embodiment in that the high-speed block 101 is replaced by the 1/8 frequency divider 13 instead of the 1/6 frequency divider 11 and 1/13 frequency divider 12. In addition, the low-speed block 102 is configured in the 1/11 frequency divider 14, respectively.

The 1/8 frequency divider 13 has D flip-flops DFF1 to DFF3 connected to T flip-flops, and uses level shift circuits LS1 to LS3 between stages.

The 1/11 frequency divider 14 outputs the outputs of the D-type flip-flops DFF4 to DFF6 to the level shift circuit LS
4 to a T-type flip-flop TFF1.

The configuration examples of the two frequency dividers have been described above. However, it is clear that other frequency division ratios can be realized by combining the components of the high-speed block and the low-speed block.

[0024]

As described above, in the frequency synthesizer of the present invention, the connection between the above-mentioned constituent circuit elements and the integrated circuit substrate in which the base circuit having the constituent circuit elements of the frequency divider is formed in advance in the wiring process is established. By providing the designated and generated wiring layer, the design process from circuit design to mask design for each target system becomes unnecessary, so that the development period is shortened and the development cost is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a frequency synthesizer according to the present invention.

FIG. 2 is a block diagram illustrating an example of a frequency synthesizer according to the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the frequency synthesizer of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Integrated circuit board 11 1/6 frequency divider 12 1/13 frequency divider 13 1/8 frequency divider 14 1/11 frequency divider 101 High speed block 102 Low speed block 103 PLL block A1 Buffer amplifier N1-N4 NOR circuit DFF1 To DFF6 D-type flip-flop LS1 to LS6 Level shift circuit TFF1 to DFF4 T-type flip-flop PA1 Preamplifier PLL1 Phase locked loop

Claims (1)

(57) [Claims] 1. A monolithic in the frequency synthesizer comprising a semiconductor integrated circuit, a phase locked loop circuit and each of the at least one high-speed operation for the D-type flip-flop and a level shift circuit for high-speed block, each at least for low-speed block
D-type flip-flops for low-speed operation, T-type flip-flops for medium-speed operation , level shift circuits, and N for logic configuration
An integrated circuit board in advance produce a base circuit having an OR circuit, the said phase-locked loop circuit of the integrated circuit substrate when the wiring step and the high-speed operation for the D-type flip-flop low
A frequency synthesizer comprising a D-type flip-flop for high-speed operation, the T-type flip-flop, and a wiring layer generated by designating a connection between the level shift circuit and the NOR circuit.