JP2728958B2 - Arithmetic processing device and method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing apparatus and a method for sequentially performing a predetermined multiplication operation and an addition operation, and particularly to greatly simplify the configuration thereof. .

[Conventional technology]

In general, when calculating new data M from four digital data A, B, J, and K based on the following equation (1), M = J × A + K × B (1) It is clear from equation (1). Thus, two multiplication operations and one addition operation are required.

Further, when such arithmetic processing is performed in real time using sequentially changing data A, B, J, and K, time-division processing of two multiplication operations by one multiplier is required for the calculation time. If this is not possible, two multipliers and one adder for multiplying J × A and K × B in parallel are required, and such a digital processing device is shown in FIG. The one shown was known.

That is, as shown in the figure, this digital arithmetic processing device multiplies and adds 3-bit digital data J and A, K and B, respectively, to obtain M (= m ₆ , m ₅ , m ₄ , m).
₃ , m ₂ , m ₁ , m ₀ ), a first multiplier (101) for performing a J × A multiplication process and a second multiplier (for a K × B multiplication process) 102) and an adder (103) for performing an addition process on the operation output of each multiplier (101, 102).

Each of the multipliers (101) and (102) has nine AND circuits (hereinafter referred to as "AND circuits") (104 to 104) as shown in the figure.
112, 113 to 120) and adders (121, 122) for adding the outputs of the respective AND circuits with predetermined weights. Each of the AND circuits performs a logical AND operation of J × A and K × B.

Further, a latch circuit (1) is provided in the first multiplier (101).
The digital data A is supplied via the latch circuit (124), the digital data J is supplied via the latch circuit (124), and the digital data J is supplied to the second multiplier (102) via the latch circuit (125). The other digital data B
Is supplied, and digital data K is supplied via a latch circuit (126).

Next, the operation of the digital arithmetic processing device having the above configuration will be described.

First, the operation of the first multiplier (101) will be described. By the respective AND circuits (104 to 112) of the multiplier (101), the 3-bit data A (a ₂ , a ₁ , a) is obtained. ₀ ) and J
Perform a logical AND operation with (j ₂ , j ₁ , j ₀ ).

That is, the one input terminal of each of the AND circuits (104 to 106) of the first group (101a) constituted by the AND circuits (104 to 106) has bit data of the most significant digit (2 ² ) of the multiplier J. (j ₂₎
Is supplied, and the respective bit data (a ₂ , a ₁ , a ₀ ) of the multiplicand A are supplied, and the logical product of these is performed.

Thereby, each AND circuit (104) of the first group (101a)
To 106) outputs the logical product of J ₂ a ₂ , J ₂ a ₁ , and J ₂ a ₀ .

Hereinafter, the second group (1) composed of AND circuits (107 to 109)
0b) performs an AND operation of the bit data (j ₁ ) of the second digit (2 ¹ ) of the multiplication J and the multiplicand A, and the AND circuit (1b)
Each of the AND circuits of the third group (101c) composed of 10 to 112) performs a logical AND operation of the bit data (j ₀ ) of the least significant digit (2 ⁰ ) of the multiplier J and the multiplicand A.

As a result, the second group (101b) and the third group (101b)
From each AND circuit _{c) (107~112), j 1} a 2, j 1 a 1, j 1 a 0, j
₀ Each logical product of _{a 2, j 0 a 1,} j 0 a 0 is output.

The AND operation by these AND circuits (104 to 112) is a multiplication of three-digit numbers, that is, This corresponds to the operation of the X part in the operation.

Next, the respective ANDs obtained as described above are subjected to an addition operation corresponding to the Y portion in the above equation (2) by the adder (121), and S ₅ , S ₄ , S ₃ , S ₂ , S ₁ and S ₀ are obtained.

As the adder (121), for example, as shown in FIG. 6, a plurality of half adders (128 to 130) and a full adder (13
1-133).

On the other hand, the second multiplier (102) is also the first multiplier as described above.
Operates in the same manner as the multiplier (101), the number of multiplications with the AND circuits (113-121) of the first group (102a) to the third group _{(102c) B (b 2,} b 1, b ₀ ) and the multiplier K (k ₂ , k ₁ , k ₀ ), and an addition operation is performed using the adder (122), whereby the addition output (multiplication result) t ₅ , t ₄ ,
t ₃ , t ₂ , t ₁ , t ₀ are obtained.

Then, the addition output S ₅ calculated by the above-described operation is calculated.
SS ₀ , t ₅ tt ₀ are supplied to the adder (103) to perform an addition operation, whereby M (m ₆ , m) calculated by the above equation (1)
_{5, m 4, m 3,} m 2, m 1 m 0) obtained.

[Problems to be solved by the invention]

As described above, when the arithmetic processing of the above-described equation (1) is performed at a sufficiently high speed using the conventional technique, two multipliers (101, 102) and one adder (103) are required. Inevitably needed.

For this reason, there is a problem that the circuit scale of this type of digital arithmetic processing device becomes large, which causes a cost increase, and that the reliability is reduced because the number of elements constituting the circuit is extremely large.

[Means (and action) for solving the problem]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has a small circuit scale, a small number of constituent elements, can reduce costs, and can reduce a processing speed. It is an object to provide an arithmetic processing device.

The present invention is an arithmetic processing device that has a plurality of pairs of a multiplier and a multiplicand as a plurality of inputs and outputs a value obtained by adding up the multiplication result of each pair, and a control signal generated based on each of the multipliers. A selecting means for selecting and outputting one of a multiplicand, an addition result of two or more multiplicands, and a zero value, and an adding means for performing predetermined weighting on a plurality of outputs output from the selecting means and adding the outputs. It is characterized by becoming.

Further, the present invention is an arithmetic processing method having a plurality of pairs of a multiplier and a multiplicand as a plurality of inputs and outputting a value obtained by adding the multiplication result of each pair, wherein each control signal is generated based on each multiplier, One of a multiplicand, an addition result of two or more multiplicands, and a zero value is selectively output, and a plurality of output selection results are subjected to predetermined weighting and added.

[Action]

According to the present invention, by using a selector that can be appropriately switched by a control signal using a multiplier, the circuit scale is significantly reduced as compared with a conventional arithmetic processing device, the number of constituent elements is reduced, and furthermore, Processing time is reduced.

〔Example〕

Hereinafter, a preferred embodiment of an arithmetic processing apparatus and method according to the present invention will be described in detail with reference to FIG.

The arithmetic processing device according to the present embodiment includes digital data (multiplicands) A (a ₂ , a ₁ , a ₀ ) and B (b ₂ , b ₁ , b ₀ ) of 3 bits each.
And 3-bit digital data (multiplier) J (j ₂ , j
₁ , j ₀ ) and K (k ₂ , k ₁ , k ₀ ), and is a digital operation processing device that executes the operation processing as represented by the above equation (1), and includes first to third selectors (201, 202, 203) ) And the first
And a second adder (205, 204).

That is, the input terminal (206) has one of the multiplicands A
Is supplied, and each bit data (a ₂ , a ₁ ,
a ₀ ) is latched by a latch circuit (207) and timing-controlled, and then each selector (201-2) is connected via a bus line.
03) is supplied to one input terminal ("10").

Similarly, the other input terminal (208) is supplied with the other multiplicand B, and the bit data (b ₂ , b ₁ ,
b ₀ ) is latched by the latch circuit (209) and is controlled so as to be synchronized with the latch output timing of the multiplicand A, and then is input to another input terminal (“0”) of each of the selectors (201 to 203).
1 ").

The multiplicands A and B are also supplied to an adder 205, where A and B are added. In this embodiment, it is assumed that the convenience A + B <2 ³ description. By doing so, the output of the adder 205 can be represented by 3 bits, and this is represented by G (g ₂ , g ₁ , g ₀ ).
And This G is latched by a latch circuit (214) and is controlled so as to be synchronized with the latch output timing of the multiplicand A, and then the remaining input terminals ("1
1 "). Each bit data (a ₂ , a ₁ , a ₀ ) of the multiplicands A and B and the addition result G of the multiplicands A and B,
The weights of (b ₂ , b ₁ , b ₀ ) and (g ₂ , g ₁ , g ₀ ) are (2 ² , 2 ¹ , 2 ⁰ )
It has become.

On the other hand, the multiplier J (j ₂ , j ₁ ,
j ₀ ) and the multiplier K (k ₂ , k ₁ , k ₀ ) are supplied to the input terminal (212) and sent to each selector via the latch circuit (211,213). The weight of each bit data of these multipliers J and K is also (2 ² , 2 ¹ , 2 ⁰ ).

In the multiplier of the present invention, all the bit data of the multiplier are directly used as control signals of the selectors (201, 202, 203). However, bit data having the same weight is supplied to the same selector. In this embodiment, two bits of j ₂ k ₂ are used as the first selector (201), two bits of j ₁ k ₁ are used as the second selector (202), and two bits of j ₀ k ₀ are used as the third selector. (203).

Each selector selects a selector input terminal (“10”) when the supplied control signal is “10”, a selector input terminal (“01”) when “01”, and a selector input terminal (“01”) when “11”. Selects the selector input terminal ("11") and outputs the value supplied to the input terminal. If the control signal is "00", the value 0 is output without selecting anything. However, if an input terminal ("00") for virtually inputting the value 0 is provided and selected and output, You may think.

As described above, each of the selectors (201 to 203) determines the value (“00”, “1”) of the supplied control signal (j ₂ k ₂ , j ₁ k ₁ , j ₀ k ₀ ).
0, "01" or "11") to selectively output a zero value or a multiplicand A, B or G (= A + B). Therefore, the output value of the first selector (201) is as shown in the table below according to the value of the control signal (j ₂ k ₂ ).

Therefore, when this is represented by a general formula, j ₂ ▲ ▼ × A + ▲ ▼ ・ k ₂ × B + j ₂・ k ₂ × (A +
B) (3), and the relationship between the value of the expression (3) and the control signal (j ₂ , k ₁ ) is as shown in the following table.

Therefore, the output value of the selector (201) is expressed by Expression (3) = j ₂ × A + k ₂ × B. Similarly, the second and third selectors (202, 20)
Each output value of 3) is represented by j ₁ × A + k ₁ × B (4) j ₀ × A + k ₀ × B (5)

Then, each data d ₄ , d ₃ , d ₂ , e ₃ , which is output from each selector (201 to 203) and is expressed by the equations (3) to (5),
The e ₂ , e ₁ , f ₂ , f ₁ , and f ₀ are subjected to predetermined weighting by an adder (204) at the subsequent stage, and are subjected to addition processing.

That is, the control signal _{(j 2 k 2, j 1} k 1, j 0 k 0) weighting for is set to, as described previously (2 ^2, 2 ^1, 2 ^0), the selectors (201 -203) are weighted with respect to the supplied bit data.

Thus, each output value in consideration of the weights of the first to third selectors (201 to 203) _{^{are, 2 2 × (j 2 ×}} A + k 2 × B) ... (6) Equation _{^{2 1 × (j 1 × A}} + k 1 × B) ... (7) equation _{^{2 0 × (j 0 × a}} + k 0 × B) ... (8) can be expressed by the equation of formula, the output value of the selector _{(d 4, d 3, d} 2 The subscripts of () (e ₃ , e ₂ , e ₁ ) (f ₂ , f ₁ , f ₀ ) correspond to the weighting coefficients.

The output values thus weighted are added by an adder (204), and a 6-bit operation output M (m ₅ ,
m ₄ , m ₃ , m ₂ , m ₁ , m ₀ ) are output.

The configuration of the adder (204) is the same as the adder (121, 122) used in the multiplier of the conventional example (FIG. 5), that is, the adder of FIG.

The operation output M in the digital operation processing device having the above configuration is the sum of the above expressions (6), (7) and (8), as is clear from the above description.

That, M = (6) where + (7) + (8) _{^{= (2 2 · j 2 +2}} 1 · j 1 +2 0 · j 0) × A + (2 2 · k 2 +2 1 ·
k ₁ +2 ⁰ k ₀ ) × B, and in the above equation, 2 ² · j ₂ +2 ¹ · j ₁ +2 ⁰ · j ₀ = J,
Because it is ^{_{2 2 · k 2 +2 1 ·}} k 1 +2 0 k 0 = K, the M = J × A + K × B.

Therefore, a desired operation result can be obtained by the digital operation processing device having the configuration shown in FIG.

As described above, according to the digital arithmetic processing device according to the present embodiment, the result of adding the multiplicands A and B in advance and performing the arithmetic processing as in the above equation (1) and the bit data of the multipliers A and B , And adding the selected outputs, it is not necessary to provide two independent multipliers as in the conventional example. Therefore, according to the present embodiment, the circuit scale and the number of components of this kind of digital operation processing device can be greatly reduced and simplified.

Further, the processing time of the adder (205) in the above-described embodiment is different from the processing time of the subsequent adder (10) in the conventional example shown in FIG.
The processing time of 3) is shorter because the number of bits in the adder (205) of this embodiment is smaller than that of the conventional example.

Therefore, according to the present embodiment as described above, the processing time can be reduced.

 FIG. 2 shows a second embodiment of the present invention.

The configuration of FIG. 2 is different from the configuration of FIG.
5) and the latch circuit (214) for latching the added output are removed, and the first to third selectors (201, 202, 203) having a reduced number of inputs are added to the AND-OR circuits (301, 302, 303) having the configuration shown in FIG. It has been changed. The contents of the processing performed in the second embodiment are the same as those in the above equation (1). However, the following condition is assumed between the multiplicands A and B (each 3-bit data).

A + B = 2 ³ -1 = 7 (9) Since the addition result of A and B is always 7 depending on the above conditions, it is not necessary to add A and B.

Therefore, the first adder (205) and the latch circuit (214) for latching the output thereof in FIG. 1 can be eliminated.

Next, since the data is Expressed in three bits 111 ₂ of 7, accept the selector (201, 202, 203) in FIG. 1, all of these selectors (201,202,20
By supplying "1" to the input terminal ("11") of 3), the desired operation can be performed. However, when the relationship between the control signal and the output of the selector and the relationship between A and B are arranged, The selectors (201, 202, 203) in FIG. 1 can use the configuration shown in FIG. That is, the selector control signal and the output have the relationship shown in the table below, Since A + B = 7, _ai = ▲ (i = 0, 1, 2), and therefore, the same function can be realized by the AND-OR circuit shown in FIG.

Therefore, equation (1) under the condition of equation (9) can be calculated by the digital processing unit having the configuration shown in FIG.

By the way, when the expression (1) under the condition of the expression (9) is modified, it becomes as follows.

Here, R in the equation (10) ^{7 (A + B = 2 3} -
1).

What the above equation (10) physically means is that the signals J and K are That is, a signal obtained by mixing at the ratio and multiplying by R is output to M, and such a processing circuit is very effective in a mixing circuit.

In the present embodiment, the case where A + B = 2 ⁿ -1 (n = 3) has been described. However, it is also possible to apply A + B = arbitrary set value.

As described above, according to the digital arithmetic processing device according to the present embodiment, the circuit scale required for performing the arithmetic processing as shown in the above equation (10) requires the multiplier 1 in the conventional example shown in FIG.
And the circuit can be greatly reduced and simplified.

Further, by simplifying the configuration in this way, the operation processing time can be reduced. That is, in the conventional example shown in FIG. 6, it is necessary to add the multiplied outputs of the respective multipliers in the adder (103) in the subsequent stage. However, in the present embodiment, since the subsequent adder is not required, the operation time can be reduced by that much.

 FIG. 4 shows a third embodiment of the present invention.

In the figure, reference numeral 501 denotes a first multiplicand A (a ₂ , a ₁ , a ₀ ), 5
02 is the second multiplicand B (b ₂ , b ₁ , b ₀ ), 503 is the third multiplicand H (h ₂ , h ₁ , h ₀ ), and 504 is the first multiplier J (j ₂ , j ₁ , j ₀ ), 505
Is the second multiplier K (k ₂ , k ₁ , k ₀ ), and 506 is the third multiplier L (l ₂ ,
l ₁ , l ₀ ), and 507, 508, 509 are A
And B, A and H, and an adder for adding B and H.
511, 512, 513 are A, B, H, A + B, A + H, B + H, A + B + C, 0
Selector 514 to select and output any one of
Is an adder for adding the outputs of the selectors (511, 512, 513), and 215 is a terminal for outputting the operation result.

In this embodiment, the following operation is performed using the above-described circuit.

M = J × A + K × B + L × H (11) The operation will be described below.

The data of the three multiplicands A, B, and H input from the terminals 501, 502, and 503 are distributed and supplied to the terminals of the selectors (511, 512, and 513), and are also supplied to the adders (507, 508, 509, and 510). Adders 507, 508, 509 are A and B, respectively.
A and H, B and H are added, and the result is added to selectors 511, 512,
Supply 513. The adder 510 adds A to the value B + H output from the adder 509, outputs a value A + B + H, and supplies it to the selectors 511, 512, 513.

On the other hand, the terminals 504, 505, and 506 have three multipliers J (j ₂ , j ₁ ,
j ₀ ), K (k ₂ , k ₁ , k ₀ ) and L (l ₂ , l ₁ , l ₀ ) are input, and their bit data are divided into bits having the same weight, and the first selector ( the _{511) j 2 k 2 l 2} , the second selector _{(512) j 1 k 1 l} 1, the third selector (513) j ₀ k _0
10 is supplied as a control signal.

To each selector, seven data A, B, H, A + B, A + H, B + H, A + B + H are supplied to data input terminals, and three bits j, k, l are given as control signals for selecting them. I have. The relationship between the control signal and the selected output signal is determined as shown in the following table.

When the control signal is 0 in all three bits, 0 is output without selecting any of the above seven data (in other words, it can be said that 0 is selected and output).

The output value of such a selector can be expressed by an equation using multiplicands A, B, H and control signals j, k, l. The output values of the first to third selectors will be described below in order.

j ₂ × A + k ₂ × B + l ₂ × H (12) j ₁ × A + k ₁ × B + l ₁ × H (13) j ₀ × A + k ₀ × B + l ₀ × H (14) The output value of each selector is The adder performs a predetermined weighting and adds processing. Each output value in consideration of the _{^{weighting, 2 2 × (j 2 ×}} A + k 2 × B + l 2 × H) ... (15) 2 1 × (j 1 × A + k 1 × B + l 1 × H) ... (16) 2 0 × (J ₀ × A + k ₀ × B + 1 ₀ × H) (17), and the subsequent adder (514) adds the above three values to obtain M (m ₅ , m ₄ , m ₃ , m ₂ , m ₁ , m ₀ ). Therefore M = (15) where + (16) + (17) _{^{= (2 2 · j 2 +2}} 1 · j 1 +2 0 · j 0) × A + (2 2 · k 2 +2 1 ·
In ^{_{k 1 +2 0 · k 0)}} × B + (2 2 · l 2 +2 1 · l 1 +2 0 · l 0) × H above ^{_{equation, 2 2 · j 2 +2 1}} · j 1 +2 0 · j 0 = J , _² 2 · k 2 +
^{_{2 1 · k 1 +2 0 ·}} k 0 = K, 2 2 · l 2 +2 1 · l 1 +2 0 · since l is ₀ = L a M = J × A + K × B + L × H.

As described above, according to the embodiment of the present invention, when the arithmetic processing of the equation (11) is performed, three multipliers and two adders for adding the multiplication result were conventionally required. It can be realized with a circuit scale equivalent to four and one multiplier.

Also, as seen in the second embodiment, the multiplicands A, B, H
Can be further reduced under the condition that the sum of the constants is constant.

In each of the above-described embodiments, the present invention is applied to a digital arithmetic processing device. However, it goes without saying that the present invention may be applied to an analog arithmetic processing device.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, for example, when an operation of M = J × A + K × B is performed on four digital data A, B, J, and K, conventionally, there are two multipliers. Although one adder is required, according to the present invention, it can be realized with a circuit scale equivalent to one multiplier and one adder.

Therefore, according to the present invention, it is possible to reduce the circuit scale of this type of arithmetic processing device and the number of constituent elements, thereby achieving cost reduction.

Further, according to the present invention, the processing speed can be reduced by reducing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an arithmetic processing circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram showing an arithmetic processing circuit according to a second embodiment of the present invention, and FIG. , A block diagram showing the configuration of an AND-OR circuit, FIG. 4 is a block diagram showing an arithmetic processing circuit of a third embodiment of the present invention, FIG. 5 is a block diagram showing a conventional example, and FIG. FIG. 3 is a block diagram showing a configuration of an adder inside a multiplier used in the drawing. 206 and 208 are terminals for inputting 3-bit multiplicands A and B, 210 and 212 are terminals for inputting 3-bit multipliers J and K, 215 is a terminal for outputting a 6-bit operation result, and 201, 202 and 203 are two multiplicands A and B. And their sum (A + B)
A selector 205 selects and outputs one of them, 205 is an adder for adding A and B, and 207, 209, 211, 213, and 214 are latch circuits for latching 3-bit data.

Claims (2)

(57) [Claims] An arithmetic processing device having a plurality of pairs of a multiplier and a multiplicand as a plurality of inputs and outputting a value obtained by adding a multiplication result of each pair, wherein each multiplicand is controlled by a control signal generated based on the multiplier. A selection means for selecting and outputting any one of the addition result of the two or more multiplicands and a zero value, and an addition means for weighting a plurality of outputs output from the selection means and adding the weighted outputs. An arithmetic processing device characterized by the above-mentioned. 2. An arithmetic processing method having a plurality of pairs of a multiplier and a multiplicand as a plurality of inputs and outputting a value obtained by adding the multiplication result of each pair, wherein each multiplicand is controlled by a control signal generated based on the multiplier. An arithmetic processing method characterized by selectively outputting any one of an addition result of two or more multiplicands and a zero value, performing predetermined weighting on a plurality of output selection results, and adding them.