JP2729670B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology that is effective when applied to a semiconductor device, for example, a technology that is effective when used for a plastic pin grid array type semiconductor device. It is.

[Prior Art] With the high integration of semiconductor devices, a so-called plastic pinlit array (P-PGA) type semiconductor device in which lead pins are erected on the back surface of a plastic substrate is often used. It has become.

FIG. 3 shows an example of this plastic pinlit array type semiconductor device.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate made of, for example, glass epoxy.
A large number of lead pins 8 are provided vertically on the back surface. The lead pins 8 are not shown, but the plastic substrate 1
The head protrudes from the surface, and the inner end of the head of the lead pin 8 extends to the vicinity of the semiconductor chip 5 disposed substantially at the center of the surface of the plastic substrate 1.
For example, a wiring 2 made of Cu is provided continuously. This wiring 2
Bonding pad portions (not shown) are formed on the inner end of the semiconductor chip 1 and on the semiconductor chip 1, respectively, and these bonding pad portions are connected by bonding wires 6. A solder resist film 13 for protecting the wiring 2 is coated on all portions of the wiring 2 outside the banding pad portion. Inner than the innermost lead pin among the lead pins 8 (including the innermost lead pin)
In a position where the bonding pad portion of the wiring 2 is included therein and the solder resist film 13 is also included therein, the dam 4 serving as a stopper for the below-described gel 7 to flow to the lead pin 8 is provided. The dam 4 is filled with a gel 7 made of, for example, silicon gel.

As described above, in the above-described semiconductor device, the solder resist film 13 on the plastic substrate 1 is formed on all portions of the wiring 2 outside the bonding pad portion. 4, the wiring in the dam 4 is covered with two types of protective films, the solder resist film 13 and the gel 7.

[Problems to be Solved by the Invention] However, the above-described semiconductor device has the following problems.

That is, the relative dielectric constant of the solder resist film 13 is about 4-5.
Is relatively high, the inter-line capacitance of the wiring 2 arranged at high density in the dam 4 and covered with the solder resist film 13 becomes large, crosstalk occurs, and a malfunction occurs. There is.

In particular, recently, there has been a tendency to increase the number of pins (about 400 pins or more), and the density of wiring in the dam 4 has increased due to the increase in the number of pins. is there. When this problem occurs, the number of simultaneous switching is limited, and this is a problem particularly in a high-speed signal transmission type semiconductor device.

Further, since the thermal expansion coefficients of the plastic substrate 1, the wiring 2 and the solder resist 13 are considerably different, when a thermal change occurs, stress concentrates on the wiring 2 below the inner end of the solder resist 13 and the wiring 2 In addition, there is a problem that cracks occur in the plastic substrate 1 and reliability is impaired.

The present invention has been made in view of the above problems, and provides a semiconductor device in which the capacitance between wirings of a package is reduced, malfunction is prevented, substrate cracks are prevented from occurring, and reliability is improved. It is intended to be.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a plurality of lead pins vertically provided on the back surface of the substrate, a semiconductor chip disposed substantially at the center of the surface of the substrate, and an inner end extending to the vicinity of the semiconductor chip while being connected to the lead pins. A plurality of wirings provided on the surface of the existing substrate, a bonding wire for electrically connecting a bonding pad at an inner end of the wiring to a bonding pad on the semiconductor chip, and a bonding pad for the wiring A solder resist film serving as a protective film covering a portion outside the portion, and a position on the substrate surface that is inside the innermost one of the lead pins and that includes the bonding pad portion of the wiring therein. In a pinglit array type semiconductor device comprising a dam as a flow stopping means disposed in the and a gel filled in the dam, The innermost end of the serial solder resist film, in which so as to be positioned at the bottom of the dam.

[Operation] According to the above-described means, since the solder resist film is not formed inside the dam, the wiring arranged at a high density in the dam becomes a gel having a relative dielectric constant lower than that of the solder resist film. Due to the effect of being in direct contact, the capacitance between the wirings of the package is reduced, so that crosstalk is prevented, and the above-described object of preventing malfunction is achieved.

According to the above-described means, since the innermost end of the solder resist film is located at the lower part of the dam, the dam can fix the stepped portion that has become a crack occurrence site, by the effect that it can be fixed. The occurrence of substrate cracks is prevented, and the above-described object of improving reliability is achieved.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

1 and 2 show an embodiment of a semiconductor device according to the present invention. The outline is as follows.

The semiconductor device of this embodiment is a plastic pinlit array type semiconductor device. Reference numeral 1 denotes a semiconductor substrate made of, for example, glass epoxy, and a large number of lead pins 8 are provided on the back surface of the plastic substrate 1. ing. Although not shown, the head of the lead pin 8 protrudes from the surface of the plastic substrate 1. The head of the lead pin 8 extends to the vicinity of the semiconductor chip 5 disposed substantially at the center of the surface of the plastic substrate 1. An interconnect 2 made of, for example, Cu is extended from the inner end thereof. Bonding pad portions (not shown) are formed on the inner end of the wiring 2 and the semiconductor chip 1, respectively. These bonding pad portions are connected to each other by bonding wires 6 made of, for example, aluminum. A solder resist film 3 for protecting the wiring 2 is coated on the wiring 2, and is formed so that the innermost end thereof is located below a dam 4 described later. At a position inside the lead pin 8 (including the lead pin at the innermost circumference) and including the bonding pad portion of the wiring 2 inside the lead pin 8, the lead pin of the gel 7 described later is placed. The dam 4 serving as a stop for the flow to 8 is formed by applying, for example, silicon rubber in a ring shape, and the dam 4 is filled with a gel 7 made of, for example, silicon gel.

As described above, in the present embodiment, the solder resist film 3 is not formed inside the dam 4, that is, the wiring inside the dam 4 has a relative dielectric constant lower than the relative dielectric constant (4 to 5) of the solder resist. (2-3), which are in direct contact with the silicon gel 7 and the solder resist film 3
Is located below the dam 4 and is fixed by the dam 4.

According to the semiconductor device configured as described above, the following effects can be obtained.

That is, since the solder resist film 3 is not formed inside the dam 4, the wirings arranged at high density in the dam 4 are in direct contact with the gel 7 having a relative dielectric constant lower than that of the solder resist film 3. , The capacitance between the wirings of the package is reduced, so that crosstalk is prevented, and malfunction is prevented.

In addition, since the innermost end of the solder resist film 3 is located below the dam 4, the dam 4 can fix the step where the crack has occurred, thereby generating the substrate crack. Is prevented, and the reliability is improved.

In addition, the silicon gel has better adhesion than the solder resist and has a high sealing effect, so that a leak path between the wirings 2 is further prevented.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

For example, in the above embodiment, the gel 7 is a silicon gel, but any gel having a relative dielectric constant smaller than that of the solder resist film 3 may be used.

The present invention is also applicable to a semiconductor device in which a sealing cap is adhered to the substrate 1 of the semiconductor device of the above embodiment.

The present invention is particularly effective to be applied to a high-speed signal transmission type semiconductor device because it reduces the capacitance between wirings and prevents crosstalk. Needless to say, it can be applied even if it is not a high-speed signal transmission type.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a plurality of lead pins vertically provided on the back surface of the substrate, a semiconductor chip disposed substantially at the center of the surface of the substrate, and an inner end extending to the vicinity of the semiconductor chip while being connected to the lead pins. A plurality of wirings disposed on the surface of the existing substrate; a bonding wire for electrically connecting a bonding pad on the inner end of the wiring to a bonding pad on the semiconductor chip; A solder resist film as a protective film covering a portion outside the pad portion; and the substrate surface inside the lead pin and inside the lead pin, and including the bond pad portion of the wiring inside the lead pin. In a pinglit array type semiconductor device comprising a dam as a flow stopping means disposed at the position of and a gel filled in the dam, Since the innermost end of the solder resist film is located at the lower part of the dam, the wiring arranged at high density in the dam directly contacts the gel having a relative dielectric constant lower than that of the solder resist film. Become like As a result, the capacitance between wirings of the package is reduced, crosstalk is prevented, and malfunction is prevented.

Further, according to the present invention, since the innermost end of the solder resist film is located below the dam, it is possible to fix the step portion where the dam is a crack occurrence site. As a result, the occurrence of substrate cracks is prevented, and the reliability is improved.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged view of a portion A in FIG. 1, and FIG. 3 is a longitudinal sectional view of a semiconductor device according to the prior art. DESCRIPTION OF SYMBOLS 1 ... plastic substrate, 2 ... wiring, 3 ... solder resist film, 4 ... dam, 5 ... semiconductor chip, 6 ... bonding wire, 7 ... gel, 8 ... lead pin.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor, Yoshiyuki Shirai 2326, Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor, Takayuki Okinaga 5--20, Josuihoncho, Kodaira-shi, Tokyo 1 Hitachi Ultra LSE Engineering Co., Ltd. (72) Inventor Takashi Emata 5-20-1, Kamizuhoncho, Kodaira City, Tokyo Hitachi Ultra LSE Engineering Co., Ltd. (56 References: Japanese Utility Model, Sho 62-10499 (JP, U)

Claims (2)

(57) [Claims] A plurality of lead pins provided vertically on a back surface of the substrate; a semiconductor chip provided substantially at the center of the front surface of the substrate; and a semiconductor chip connected to the lead pins and having an inner end portion connected to the semiconductor chip. A plurality of wirings provided on the surface of the substrate extending to the vicinity; a bonding wire for electrically connecting a bonding pad at an inner end of the wiring to a bonding pad on the semiconductor chip; A protective film covering a portion outside the bonding pad portion of the substrate, and a protective film disposed at a position on the substrate surface that is inside the innermost one of the lead pins and that includes the bonding pad portion of the wiring therein. In a Pinglit array type semiconductor device comprising: a flow stopper provided, and a gel filled in the flow stopper, the innermost end of the protective film is Wherein a which is located below the flow stopping means. 2. The semiconductor device according to claim 1, wherein said gel is a silicon gel.