JP2734268B2 - Clock wiring design equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for designing a clock wiring such as an LSI or PWB.

[0002]

2. Description of the Related Art FIGS. 4 and 5 show a conventional example. In FIG. 4, clock drivers 201 to 203, flip-flops 204 to 206, and gates 207 to 211 are shown.
Are arranged, and then the clock nets 212 to 214 and the respective nets on the paths 215 and 216 are wired (the clock nets 212 to 214 are wired with equal lengths, the clock skew is 0, and the 2
15 and 216 are also wired by the shortest route. According to the result of the delay analysis, it is assumed that the path 215 has the delay time of 10 [ns], is the worst case path with the smallest delay time margin, and the delay time of the path 216 at the next stage is 6 [ns]. . FIG. 5 shows input terminals H01, H of flip-flops 205, 206 when the clock cycle is 10 [ns].
02 and the flip-flop 204
6 is a timing chart showing waveforms of clocks at clock input terminals CK1 to CK3 of FIG.

In this conventional example, layout design and wiring are performed in an automatic layout tool for the purpose of reducing clock skew and shortening the path length of the worst case path to shorten the path delay time. It was common to design and not modify the clock wiring especially after the layout was completed. Especially when it is necessary to shorten the clock cycle, instead of correcting the clock net wiring, techniques such as placement correction and wiring correction to reduce the worst case path length manually are taken. Was.

[0004]

In the conventional clock wiring design apparatus described above, it is basically assumed that the clock skew is reduced. Therefore, when the clock cycle is reduced, the delay time of the worst case path is reduced. There is a need to. However, since the clock cycle defines the delay time of the worst case path, there is a disadvantage that the clock cycle cannot be made shorter (improve the performance) than the delay time. Furthermore, there is the disadvantage that the work to reduce the delay time of the worst-case path requires a lot of man-hours when it is performed manually, and in particular, as the size of the circuit increases, the work to correct them for performance improvement also increases. The inconvenience that the number of man-hours rapidly increases with the tendency.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock wiring design apparatus which can solve the above-mentioned disadvantages of the prior art and, in particular, can quickly correct a circuit.

[0006]

According to the present invention, LSI, P
In a layout wiring design apparatus such as a WB, delay analysis means for obtaining delay time margins of all paths, worst case path detection means for detecting a path having the worst delay time margin among delay time margins, Clock skew adjustment time for finding the difference between the delay time margin of the secondary worst case path having the worst delay time margin and the delay time margin of the worst case path in the next stage of the worst case path Extracting means; and additional delay time calculating means for obtaining an optimum delay time to be added to a clock net connected to the clock input terminal on the end point side of the worst case path within the range of the obtained clock skew adjustment time. The delay time calculated by the additional delay time calculation means is connected to the clock input terminal on the end point side of the worst case path. That way is added to the clock net is equipped with delay gate insertion means for performing logical changes of inserting a delay gate in the middle of the clock net, and employs a configuration that. This aims to achieve the above-mentioned purpose.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In the embodiment shown in FIGS. 1 to 3, in a layout wiring design apparatus such as an LSI and a PWB, a layout result and delay analysis information after connection and wiring processing, including connection information and clock net wiring, are completed. Input means for inputting, and delay analysis that performs comprehensive delay analysis for all paths, such as calculating the path delay time margin considering the difference between the path delay time and clock cycle and the delay time of those paths in consideration of clock skew Means and a worst-case path detection means for detecting a path having the worst delay time allowance (hereinafter referred to as a worst-case path) among the delay time allowances obtained by the delay analysis means.

Further, the delay time margin of a path having the worst delay time margin among paths following the worst case path detected by the worst case path detection means (hereinafter referred to as a secondary worst case path) is described. A clock skew adjustment time extracting means for obtaining a difference from the delay time margin of the worst case path detected by the worst case path detecting means, and a clock skew adjusting time obtained by the clock skew adjusting time extracting means, The optimum delay time to be added to the clock net connected to the clock input terminal of the flip-flop on the end point side of the worst case path (generally, the clock skew adjustment time of 1)
/ 2) is provided.

The delay time calculated by the additional delay time calculation means is added to the clock net connected to the clock input terminal of the flip-flop on the end point side of the worst case path so as to be added in the middle of the clock net. A delay gate inserting means for performing a logic change such as inserting a delay gate, an arrangement of the delay gate added by the delay gate inserting means, and an arrangement and wiring correcting means for wiring a net connected thereto; Delay analysis result updating means for recalculating the delay time margin and updating the delay analysis result with respect to the path in which the clock skew has changed due to the placement and routing correction of the delay gate and the clock net, and an output for outputting the layout result after the change Means, and control means for controlling each of the above means.

The operation of the embodiment shown in FIG. 1 will be described in relation to the above-described conventional example. First, using conventional methods, clock drivers 201 to 203, flip-flops 204 to 206, and gates 207 to 211 are arranged as shown in FIG. 4, and then clock nets 212 to 214 and paths 215, 216 This will be described using an example in which nets are wired. Here, it is assumed that the clock nets 212 to 214 are wired with the same length, the clock skew is “0”, and a layout result is obtained in which the paths 215 and 216 are also wired with the shortest path. According to the result of the delay analysis, the path 215 has a delay time of 10 [n
s], it is assumed that the path is the worst case path having the smallest delay time margin, and the delay time of the path 216 at the next stage is 6 [ns]. In the example of FIG. 4, in the conventional method, the clock skew is already “0” and cannot be reduced any further, and the path length of the worst case path cannot be further reduced. Therefore, the clock cycle cannot be shortened to 10 [ns] or less.

FIG. 5 shows a result of the conventional method, in which the flip-flop 20 when the clock cycle is 10 [ns] is used.
5 is a timing chart showing data waveforms at input terminals H01 and H02 of H.5, 206 and clock waveforms at clock input terminals CK1 to CK3 of flip-flops 204 to 206. For simplicity, here, it is assumed that there is no delay time in the circuit in the flip-flop and no rounding of each waveform, and the flip-flop operates at the rising edge of the clock. As is apparent from this figure, the clock cycle cannot be shortened to 10 [ns] or less.

In the clock wiring design apparatus of this embodiment, after the layout in the conventional method as shown in FIG. 4 is completed, first, the input means 102 shown in FIG. 1 inputs the layout result, connection information, and delay analysis information. Next, the delay analysis means 103 shown in FIG. 1 performs an exhaustive delay analysis at a clock cycle of 10 [ns] in the example, and obtains the delay time margin of all the paths. Based on the analysis result, the worst case path detecting means 104 shown in FIG.
The path 215 having the worst delay time margin of “[ns]” is detected as the worst case path.

Next, the clock skew adjustment time extracting means 105 shown in FIG.
Worst case path 216 having the worst delay time margin in the next stage path (here, only path 216)
Delay time margin of 4 [ns] and worst case path 2
Difference 4 [ns] from the delay margin “0 [ns]” of 15
Is extracted as the clock skew adjustment time. Then, the additional delay time calculating means 106 shown in FIG. 1 sets the end-point side flip-flop 20 of the worst case path 215 within the clock skew adjustment time 4 [ns].
The delay time to be added to the clock net 213 connected to the clock input terminal CK2 of No. 5 is 1/4 of 4 [ns] in the example.
It is calculated as 2 [ns].

Next, the delay gate inserting means 107 shown in FIG. 1 has a delay gate 217 having an additional delay time of 2 [ns] in the middle of the clock net 213.
And the clock net 213 is connected to the delay gate 21
7 is divided into two clock nets 218 and 219. Next, the arrangement of the delay gate 217 and the clock net 21 are adjusted by the arrangement and wiring correcting means 108 shown in FIG.
8, 219, and new clock nets 218, 2 sandwiching the delay gate 217 as shown in FIG.
Nineteen wiring paths are required. This is an example of the wiring path of the clock net that can shorten the target clock cycle.

Then, the delay time margin of the path 215 and the path 216 is updated by the delay analysis result updating means 109 shown in FIG. 1, and both become 2 [ns]. At this point, the worst value (minimum value) of the delay time margin of all paths
Is 2 [ns], the clock cycle is set to 8
[Ns], the clock skew is buffered and the input terminals H01, H0 of the flip-flops 205, 206
2 and the flip-flops 204-2
FIG. 3 is a timing chart showing the waveforms of the clocks at the clock input terminals CK1 to CK3 of FIG. 6, which shows that the circuit operates normally.

The above processing is repeated for the worst-case paths that are updated one after another to increase the delay margin, thereby shortening the clock cycle by the delay margin of the worst-case path. become able to.

[0017]

As described above, according to the present invention, the clock cycle can be shortened (improved performance) from the delay time of the worst-case path by intentionally utilizing the clock skew, and the future circuit can be used. This makes it possible to provide an unprecedented superior clock wiring design device that can reduce the time required for circuit correction work.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a layout result in which each net to be specifically applied to FIG. 1 is wired;

FIG. 3 is an explanatory diagram showing the timing of the operation in FIG. 2;

FIG. 4 is an explanatory diagram showing a conventional example.

FIG. 5 is an explanatory diagram showing the operation of FIG. 4;

[Explanation of symbols]

 Reference Signs List 102 input means 103 delay analysis means 104 worst case path detection means 105 clock skew adjustment time extraction means 106 additional delay time calculation means 107 delay gate insertion means 108 placement and wiring correction means 109 delay analysis result update means 110 output means

Claims (2)

(57) [Claims] In a layout wiring design device such as an LSI or a PWB, a delay analysis means for obtaining a delay time margin of all paths, and a worst case for detecting a path having the worst delay time margin among the delay time margins Path detection means;
A clock skew for calculating a difference between the delay time margin of the secondary worst case path having the worst delay time margin among the paths at the next stage of the detected worst case path and the delay time margin of the worst case path. Adjusting time extracting means, and additional delay time calculating means for obtaining an optimum delay time to be added to a clock net connected to the clock input terminal on the end point side of the worst case path within the range of the obtained clock skew adjusting time. And a logic change for inserting a delay gate in the middle of the clock net so that the delay time obtained by the additional delay time calculating means is added to the clock net connected to the clock input terminal on the end point side of the worst case path. A clock wiring designing apparatus, comprising a delay gate inserting means for performing the following. 2. In a layout wiring design device such as an LSI or a PWB, a delay analysis means for obtaining delay time margins of all paths, and a worst case for detecting a path having the worst delay time margin among the delay time margins. Path detection means;
A clock skew for calculating a difference between the delay time margin of the secondary worst case path having the worst delay time margin among the paths at the next stage of the detected worst case path and the delay time margin of the worst case path. Adjusting time extracting means, and additional delay time calculating means for obtaining an optimum delay time to be added to a clock net connected to the clock input terminal on the end point side of the worst case path within the range of the obtained clock skew adjusting time. And a logic change for inserting a delay gate in the middle of the clock net so that the delay time obtained by the additional delay time calculating means is added to the clock net connected to the clock input terminal on the end point side of the worst case path. Equipped with a delay gate inserting means for performing Placement and routing correction means for laying out the delay gates and routing the nets connected to the delay gates, and recalculating the delay time margin for the path whose clock skew has been changed by the placement and routing correction of the delay gate and clock net by the placement and routing correction means. And a delay analysis result updating means for updating the delay analysis result and an output means for outputting the changed layout result.