JP2736247B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which an electrical connection between an electrode on a semiconductor chip and an inner lead and an electrical connection between an outer lead and a wiring pattern on a printed wiring board are achieved. More particularly, the present invention relates to a method for manufacturing a semiconductor device in which wiring intervals for electrical connection are minute.

[0002]

2. Description of the Related Art When a semiconductor device is manufactured, electrical connection is established between electrode pads on a semiconductor chip and inner leads, between outer leads and a wiring pattern on a printed wiring board, and the like. There are many places. Conventionally, for example, electrical connection between an electrode pad on a semiconductor chip and an inner lead is usually performed by A
Metal bonding using u wire or Al wire, TAB
This is performed by metal bonding using a tape (Tape Automate Bonding), ohmic contact by metal-metal bonding between a bump electrode such as a flip chip, and a lead, or the like.

[0003]

In the connection by wire bonding, the shortest distance between adjacent wires is restricted by the outer shape of a bonding capillary (needle) to be used.
It is difficult to reduce the size to about 0 μm or less. In addition, it is necessary to apply a physical load such as heating, pressurization, ultrasonic vibration, and the like to the metal connection between the Au ball or the Al wire and the aluminum pad on the semiconductor chip. May damage itself.

On the other hand, when a TAB tape or a flip chip is used, the metal connection between the Au bump and the solder bump and the inner lead is performed, and the temperature may be higher than that of the wire bonding connection. May leave physical damage. In this case, the pad spacing can be reduced to about 80 μm, but there is a limit in reducing the bump size due to metal bonding. In addition, since connection at a large number of locations is performed collectively, as the number of connection locations such as bump heights and connection conditions increases, it becomes more difficult to obtain connection stability, and it is necessary to stabilize process conditions.

[0005] The above-mentioned problem is caused not only by the electrical connection between the pads or bumps on the semiconductor chip and the inner leads, but also by the electrical connection between the outer leads and the wiring pattern on the printed wiring board. It can also occur in cases such as

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described circumstances, and has as its object to reduce the distance between portions to be electrically connected to each other as compared with the prior art and to reduce the electrical connection. It is an object of the present invention to provide a method of manufacturing a semiconductor device having high reliability without causing physical damage such as heating and pressurization.

[0007]

According to a method of manufacturing a semiconductor device of the present invention, a semiconductor chip is attached to a lead made of a conductive material in a state where a predetermined position of the lead and an electrode formed on the surface of the semiconductor chip are brought close to each other. And a step of forming a metal plating layer that electrically connects the predetermined position of the lead and the electrode of the semiconductor chip by immersing the two in an electrolytic plating solution. .

Further, the method of manufacturing a semiconductor device according to the present invention comprises the steps of preparing a semiconductor chip having electrodes formed on the surface thereof, and preparing a TAB tape having leads having end portions formed on an insulating film. Adhering the TAB tape to the semiconductor chip using an adhesive so that the electrodes on the surface of the semiconductor chip and the tips of the leads are in close proximity to each other; and bonding the TAB tape and the semiconductor chip to each other. Forming a metal plating layer for electrically connecting the tip of the lead and the electrode of the semiconductor chip by dipping in an electrolytic plating solution.

Further, according to the method of manufacturing a semiconductor device of the present invention, there is provided a step of preparing a semiconductor chip having electrodes formed on a surface thereof, wherein a lead comprising an inner lead and an outer lead is formed on an insulating film, and a tip of the inner lead is formed. TAB with insulating film formed on most surface except for parts
A step of preparing a tape; and a step of attaching the TAB tape to the semiconductor chip using an adhesive so that the electrodes on the surface of the semiconductor chip and the tips of the inner leads are in close proximity to each other; Dipping the TAB tape and the semiconductor chip in an electroplating solution to form a metal plating layer that electrically connects the tip of the inner lead and the electrode of the semiconductor chip.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The connection between a lead frame and a semiconductor chip electrode or the lead frame and a wiring pattern on a wiring board which must be electrically connected to each other, metal plating or conductive adhesive and metal By performing the combined use with the plating, a sufficient ohmic contact can be formed between the connections and a sufficient mechanical strength can be provided. Moreover, a plurality of locations can be connected collectively, and heating and pressurizing are not required at the time of connection.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device manufactured by the method according to the first embodiment of the present invention.
FIG. 2 shows a partial configuration of the device when the connection between the electrode pads on the semiconductor chip and the inner leads is made by plating, and FIG. 2 is a cross-sectional view showing almost the entire configuration.

In FIG. 1, reference numeral 11 denotes a semiconductor chip on which active elements such as transistors and passive elements such as resistors and capacitors are formed. The lower layer is formed by a metal layer 12 made of, for example, aluminum (Al), and the upper layer is formed by a metal layer 13 including at least one nickel (Ni) layer all around the main surface of the semiconductor chip 11. A plurality of electrode pads 14 are arranged in a line at a fixed interval. The semiconductor chip 11 is covered with an insulating surface protection film 15 such as a silicon oxide film at positions other than the positions where the electrode pads 14 are formed. Further, the semiconductor chip 11 is adhered to a predetermined portion of a TAB tape 17 with an epoxy adhesive 16.

As shown in FIG. 1, the TAB tape 17 is made of a resin such as an epoxy resin or a polyimide resin and has a thickness of, for example, about 75 μm on an organic film substrate 18 having a thickness of, for example, about 35 μm. Then, a wiring pattern including a plurality of inner leads 19 to be connected to the plurality of electrode pads 14 and an outer lead (not shown) connected to each of the inner leads 19 is selectively formed by a selective etching technique. It is constituted by forming. The surface on which the wiring pattern is formed is adhered to the semiconductor chip 11 by the adhesive 16.

Also, the TAB tape 17 is provided with a semiconductor chip.
When attaching 11, the positioning is performed in such a state that the electrode pads 14 are located near the end surfaces of the tip portions of the plurality of inner leads 19 exposed. And
Each electrode pad 14 and inner lead 19 on the semiconductor chip 11
Are electrically connected to each other via a metal plating layer 20 made of, for example, nickel (Ni).

FIG. 3 is a sectional view showing the detailed structure of each of the electrode pads 14. As shown in FIG. The metal layer 13 formed on the metal layer 12 made of aluminum (Al) is composed of at least two metal layers. That is, the lower layer in contact with the metal layer 12 made of aluminum is made of, for example, a titanium (Ti) layer 31 having a thickness of 1000 angstroms, and the upper layer is made of, for example, a nickel (Ni) layer 32 having a thickness of 3000 angstroms. Here, the upper nickel layer 32 is provided to enable the metal plating layer 20 made of nickel to be formed on the electrode pad 14, and the lower titanium layer 31 serves as a barrier metal. Have.

FIG. 4 shows the plurality of electrode pads 14 and TAB
FIG. 4 is a plan view showing a connection state with a plurality of inner leads 19 formed on a tape 17, in which a hatched area indicates a metal plating layer 20.

In the above-described semiconductor device, the electrode pads 14 on the semiconductor chip 11 and the inner leads 17 are connected by using the metal plating layer 20, so that the bonding for wire bonding, TAB connection, etc. Eliminates the need for capillary and TAB tool jigs. Therefore, the interval between the electrode pads 14 can be reduced to 100 μm or less, for example, to about 50 μm. Further, when the electrode pads 14 and the inner leads 17 are electrically connected, no physical pressure is applied to the semiconductor chip 11, so that the reliability is not reduced due to the damage of the pressure. And since many connection parts can be performed collectively and on the same conditions, the reliability of connection improves. In addition, there is no need to heat when connecting, so semiconductor chips
It is also possible to prevent a decrease in reliability due to thermal stress caused by a mismatch between the thermal expansion coefficients of the layers constituting the layer 11.

By the way, the formation of the metal plating layer for electrically connecting the electrode pads and the inner leads is performed as follows. That is, as shown by the TAB tape in FIG. 5, after laminating a conductive layer such as copper on the organic film base material 18, the inner lead and the outer lead connected to the inner lead are formed by a selective etching technique. A plurality of lead electrodes 41 are formed for each semiconductor device. At this time, at the same time, a common electrode 42 for connecting the whole of the plurality of lead electrodes 41 is formed around each semiconductor device, and all the common electrodes 42 are also connected in common. In FIG. 5, reference numeral 43 denotes the organic film substrate 18
It is an opening formed in the hole.

FIG. 6 shows one example of the TAB tape shown in FIG.
FIG. 4 is an enlarged plan view showing a portion of one semiconductor device. In FIG. 6, the semiconductor chip 11 is adhered to a TAB tape in a state where the semiconductor chip 11 is positioned so as to be located in a region indicated by a chain line. At this time, as described above, each electrode pad on the semiconductor chip is located near the end face of each of the tips of the plurality of inner leads.

Thereafter, the TAB tape is immersed in a nickel plating bath together with the plating electrodes. The nickel plating bath is generally called a Watt bath, and includes a bath composed of nickel sulfate, nickel chloride, an additive and the like. After immersing both in the watt bath, a predetermined DC voltage is applied between the two so that the common electrode 42 has a positive polarity and the plating electrode has a negative polarity, and electroplating is performed for a predetermined time. For example, the applied DC voltage is 2 V, and the current flowing between them is 60 V.
When the plating time was set at 10 mA, the nickel plating layer having a thickness of 10 μm was obtained as the metal plating layer 20. The nickel plating layer initially grows from each end face of the tip of the inner lead. When this comes into contact with the electrode pad on the chip, a plating layer grows on the electrode pad thereafter, and finally both are electrically connected by the plating layer. After the plating, the substrate is washed with pure water to remove contaminants attached to the surface during plating.

In addition, most of the surface of each of the lead electrodes 41 including the inner lead and the outer lead except for the tip of the inner lead is coated with, for example, an epoxy insulating film called a green coat. Thereby, a plating layer can be formed only on a necessary portion, and the plating time can be reduced.

By the way, in the semiconductor device of FIG. 1 described above, the case where the electrode pads are arranged in a line at regular intervals on the main surface of the semiconductor chip has been described. However, as shown in FIG. 14 may be arranged in a staggered manner. Note that the same reference numerals are given to the portions corresponding to FIG. 4 and the description is omitted. Also, as shown in FIG. 8, the present invention can be implemented in a so-called free access pad layout system in which electrode pads on a semiconductor chip are randomly arranged on the entire surface of the chip.

As described above, the method of the present invention can be applied to any method regardless of the arrangement of the electrode pads on the chip. Next, another embodiment of the present invention will be described.

FIG. 9 is a sectional view showing the configuration of a semiconductor device according to a second embodiment in which the method of the present invention is applied to the connection between the outer leads of the lead frame and the wiring pattern on the printed wiring board. In the figure, 11 is a semiconductor chip, and 17 is a TAB tape. In the case of this embodiment,
Tip of inner lead of TAB tape and semiconductor chip
The electrode pads on 11 are electrically connected by the metal plating layer 20 as in the case of the above embodiment. Further, in the apparatus according to this embodiment, the metal plating layer 20 is formed between the wiring pattern 52 formed on the printed wiring board 51 and the outer lead of the TAB tape so as to achieve electrical connection. ing.

As described above, the method of the present invention can be applied not only to the connection between the inner lead of the lead frame and the electrode pad on the semiconductor chip, but also to the connection between the outer lead and the wiring pattern on the printed wiring board. And the same effect can be obtained. Further, the present invention can be applied to an electrical connection between the liquid crystal display device and the TAB tape.

FIG. 10 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention in which the method of the present invention is applied to the connection between the inner leads of the lead frame and the electrode pads on the semiconductor chip. is there. In the case of this embodiment, the lead frame is obtained by stamping a metal thin film made of, for example, an alloy called "alloy" or copper or the like by a press. The electrode pads 14 on the chip 11 are electrically connected using a conductive adhesive 54 and a metal plating layer 55 formed in the same manner as the metal plating layer 20. In the case of the embodiment using the TAB tape, the metal plating layer can be formed after the semiconductor chip is fixed on the TAB tape in advance by an adhesive. However, even when using a lead frame obtained by stamping a metal thin film, an adhesive 54 is formed in advance on each of the electrode pads 14 by a screen printing method, and after bonding to the lead frame with these adhesives, By forming a plating layer by the same method as described above, both can be electrically connected.

The present invention is not limited to the above embodiments, and it goes without saying that various other modifications are possible. For example, in each of the above embodiments, the case where the metal plating layer is a nickel plating layer has been described, but a gold (Au) plating layer, a copper plating layer, or the like can also be used.

Further, in the above-described embodiment, a case has been described in which an insulating film is previously applied to most of the surface of the inner lead except for the tip portion. However, when performing the electroplating, the plating layer grows only to a thickness of about 1/10 or less of the tip of the inner lead at a portion other than the tip of the inner lead, so that the application of the insulating coating may be omitted. . Further, in the above embodiment, the case where the plating layer is formed by the electroplating method has been described, but this may be formed by the electroless plating method.

[0029]

As described above, according to the present invention,
Manufacture of a highly reliable semiconductor device that can reduce the interval between portions to be electrically connected to each other as compared with the related art, and does not cause physical damage such as heating and pressing when making an electrical connection. A method can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device manufactured by a method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a substantially entire configuration of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view showing a detailed configuration of each electrode pad in FIG. 1;

4 is a plan view showing a connection state between a plurality of electrode pads in FIG. 1 and a plurality of inner leads formed on a TAB tape.

FIG. 5 is a plan view showing a TAB tape used in FIG. 1;

FIG. 6 is an enlarged plan view showing a portion of one semiconductor device of the TAB tape of FIG. 5;

FIG. 7 is a plan view showing another example of an arrangement state of electrode pads on a semiconductor chip.

FIG. 8 is a plan view showing still another example of an arrangement state of electrode pads on a semiconductor chip.

FIG. 9 is a sectional view showing a configuration of a semiconductor device according to a second embodiment;

FIG. 10 is a sectional view showing a configuration of a semiconductor device according to a third embodiment;

[Explanation of symbols]

 11: Semiconductor chip, 12, 13, Metal layer, 14: Electrode pad, 15: Insulating surface protective film, 16: Epoxy adhesive, 17: TAB tape, 18: Organic film substrate, 19: Inner lead , 20 ... metal plating layer.

Claims (13)

(57) [Claims] 1. A step of attaching a semiconductor chip to a lead made of a conductive material in a state in which a predetermined position of the lead is made close to an electrode formed on the surface of the semiconductor chip; Forming a metal plating layer for electrically connecting a predetermined position of the lead and an electrode of the semiconductor chip by immersion. 2. A step of preparing a semiconductor chip having electrodes formed on its surface, and a step of forming a lead having a tip on an insulating film.
Preparing an AB tape, and using an adhesive to form the TAB so that the electrodes on the surface of the semiconductor chip and the tips of the leads are close to each other.
Attaching a tape to the semiconductor chip; forming a metal plating layer for electrically connecting the tip of the lead and the electrode of the semiconductor chip by immersing the TAB tape and the semiconductor chip in an electroplating solution; And a method of manufacturing a semiconductor device. 3. A plurality of said electrodes are formed on a surface of said semiconductor chip, and a plurality of said leads are formed on said insulating film, and said plurality of leads are electrically connected to a common electrode. 3. The method according to claim 2, wherein a predetermined potential is supplied to the common electrode when the metal electrodes are connected to each other. 4. An electrode formed on the surface of the semiconductor chip is composed of three metal layers, a lowermost first layer is composed of an Al layer, an intermediate second layer is composed of a Ti layer, 3. The method according to claim 2, wherein the uppermost third layer comprises a Ni layer.
13. The method for manufacturing a semiconductor device according to item 5. 5. The method according to claim 1, wherein the electroplating solution is a Watt bath containing nickel sulfate and nickel chloride. 6. The step of forming the metal plating layer is performed by applying a potential difference between the common electrode and the plating electrode so that the common electrode has a positive polarity and the plating electrode has a negative polarity. The method for manufacturing a semiconductor device according to claim 3, wherein: 7. The step of forming the metal plating layer is performed by applying a potential difference of 2 V between the common electrode and the plating electrode and flowing a current of 60 mA between both electrodes for 10 minutes. The method for manufacturing a semiconductor device according to claim 6. 8. A step of preparing a semiconductor chip having electrodes formed on a surface thereof, wherein a lead comprising an inner lead and an outer lead is formed on an insulating film, and the lead is formed on most of the surface excluding the tip of the inner lead. A step of preparing a TAB tape on which an insulating coating is formed; and bonding the TAB tape to the semiconductor chip using an adhesive so that the electrodes on the surface of the semiconductor chip and the tips of the inner leads are in close proximity. Attaching the TAB tape and the semiconductor chip to an electroplating solution to form a metal plating layer that electrically connects the tip of the inner lead and the electrode of the semiconductor chip. A method of manufacturing a semiconductor device, comprising: 9. A plurality of said electrodes are formed on a surface of said semiconductor chip, and a plurality of said inner leads and outer leads are formed on said insulating film, wherein said plurality of inner leads and outer leads are formed. 9. The method according to claim 8, wherein a lead is electrically connected to a common electrode, and a predetermined potential is supplied to the common electrode when forming the metal plating layer. 10. An electrode formed on the surface of the semiconductor chip is composed of three metal layers, a lowermost first layer is composed of an Al layer, an intermediate second layer is composed of a Ti layer, 9. The method according to claim 8, wherein the uppermost third layer is made of a Ni layer. 11. The method of claim 1, wherein the electroplating solution is nickel sulfate,
9. The method for manufacturing a semiconductor device according to claim 8, wherein the bath is a watt bath containing nickel chloride. 12. The step of forming the metal plating layer,
10. The method of manufacturing a semiconductor device according to claim 9, wherein a potential difference is applied between the common electrode and the plating electrode so that the common electrode has a positive polarity and the plating electrode has a negative polarity. . 13. The step of forming the metal plating layer,
13. The method according to claim 12, wherein a potential difference of 2 V is applied between the common electrode and the plating electrode, and a current of 60 mA flows between the two electrodes for 10 minutes.