JP2737115B2 - Oscillation frequency non-adjustable oscillation circuit - Google Patents
Oscillation frequency non-adjustable oscillation circuitInfo
- Publication number
- JP2737115B2 JP2737115B2 JP2121833A JP12183390A JP2737115B2 JP 2737115 B2 JP2737115 B2 JP 2737115B2 JP 2121833 A JP2121833 A JP 2121833A JP 12183390 A JP12183390 A JP 12183390A JP 2737115 B2 JP2737115 B2 JP 2737115B2
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- voltage
- frequency
- signal
- output
- oscillation
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、発振周波数を無調整化した発振周波数無
調整発振回路に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation frequency non-adjustable oscillation circuit whose oscillation frequency is not adjusted.
第7図は従来の発振周波数の調整を必要とする発振回
路の構成を示し、1は入力電圧Vcontにより出力発振周
波数f0を制御する電圧制御発振器(VCO)、2は電圧制
御発振器1に電圧Vcontを与える可変電圧源である。FIG. 7 shows the configuration of a conventional oscillation circuit which requires adjustment of the oscillation frequency, wherein 1 is a voltage controlled oscillator (VCO) for controlling the output oscillation frequency f 0 by the input voltage V cont , and 2 is a voltage controlled oscillator 1 This is a variable voltage source that supplies the voltage V cont .
又、第8図は従来の無調整化された発振回路の構成を
示し、3は電圧制御発振器1の出力信号を1/n(nは正
の整数、即ちn=1,2,…)に分周するn分周器、4はn
分周器3の出力信号f0/nと基準信号frefの位相差を検出
してその位相差に応じた電圧Verrを出力する位相比較器
(PD)、5は電圧制御発振器1が位相比較器4の出力で
制御可能となるように基準電圧Vrefを加算する加算器で
ある。FIG. 8 shows the configuration of a conventional non-adjusted oscillation circuit, and 3 shows the output signal of the voltage controlled oscillator 1 as 1 / n (n is a positive integer, that is, n = 1, 2,...). Divided n divider, 4 is n
A phase comparator (PD) for detecting a phase difference between the output signal f 0 / n of the frequency divider 3 and the reference signal f ref and outputting a voltage V err according to the phase difference, This is an adder for adding the reference voltage Vref so as to be controllable by the output of the comparator 4.
次に、動作について説明する。まず、調整を必要とす
る第7図の発振回路においては、可変電圧源2の出力電
圧Vcontを調整することにより電圧制御発振器1の出力
から任意の発振周波数f0を得ることができる。Next, the operation will be described. First, in the oscillation circuit shown in FIG. 7 which requires adjustment, an arbitrary oscillation frequency f 0 can be obtained from the output of the voltage controlled oscillator 1 by adjusting the output voltage V cont of the variable voltage source 2.
次に、無調整化された第8図の発振回路においては、
電圧制御発振器1の出力信号f0をn分周器3により1/n
に分周し、位相比較器4はこの分周した信号f0/nと基準
信号frefの位相差に応じた電圧Verrを出力し、加算器5
では基準電圧Vrefが加算され、可変電圧Vcontとして電
圧制御発振器1に入力される。この結果、f0/nと基準周
波数frefとが一致するように制御され、f0=n×frefと
なり、基準信号のn倍の発振周波数を無調整で発振させ
ることができる。Next, in the non-adjusted oscillation circuit of FIG.
The output signal f 0 of the voltage controlled oscillator 1 is divided by the n frequency divider 3 into 1 / n
The phase comparator 4 outputs a voltage V err corresponding to the phase difference between the frequency- divided signal f 0 / n and the reference signal f ref , and the adder 5
, The reference voltage V ref is added and input to the voltage controlled oscillator 1 as the variable voltage V cont . As a result, the control is performed so that f 0 / n and the reference frequency f ref match, and f 0 = n × f ref , so that the oscillation frequency n times the reference signal can be oscillated without adjustment.
従来の発振回路は以上のように構成されており、第7
図の場合には発振周波数の調整が必要となり、また第8
図の場合には無調整で得られる発振周波数は基準信号の
周波数のn倍に限定され、任意の発振周波数を無調整で
得るためには、基準信号の周波数を必要とする信号の周
波数の1/nに選ばねばならず、任意の周波数の基準信号
からいくつもの周波数の信号を無調整で得ることができ
なかった。The conventional oscillation circuit is configured as described above.
In the case of the figure, it is necessary to adjust the oscillation frequency.
In the case shown in the figure, the oscillation frequency obtained without adjustment is limited to n times the frequency of the reference signal. To obtain an arbitrary oscillation frequency without adjustment, the frequency of the signal that requires the frequency of the reference signal is one time. / n, and it was not possible to obtain signals of several frequencies from a reference signal of an arbitrary frequency without adjustment.
この発明は上記のような課題を解決するために成され
たものであり、任意の周波数の基準信号から任意の発振
周波数の信号を無調整で簡単に得ることができる発振周
波数無調整発振回路を得ることを目的とする。The present invention has been made in order to solve the above-described problems, and has an oscillation frequency non-adjustable oscillation circuit capable of easily obtaining a signal of an arbitrary oscillation frequency from a reference signal of an arbitrary frequency without adjustment. The purpose is to gain.
この発明に係る発振周波数無調整発振回路は、可変電
圧の信号を入力とし、入力信号の電圧に対応した周波数
の出力信号を発する電圧制御発振器、この電圧制御発振
器の出力信号に対応した電圧信号を発生する第1の周波
数−電圧変換器、基準信号の周波数をてい倍又は分周し
て異なる周波数の2つの副基準信号を発生する装置、上
記各副基準信号の周波数に対応する電圧信号をそれぞれ
出力する第2及び第3の周波数−電圧変換器、上記第2
及び第3の周波数−電圧変換器の出力を結合し、分圧出
力を生ずる分圧比可変の分圧器及びこの分圧器の出力を
基準電圧として上記第1の周波数−電圧変換器の出力を
比較し、その差に対応した電圧信号を上記電圧制御発信
器の入力信号とする比較器を備えたものである。An oscillation frequency non-adjustment oscillation circuit according to the present invention has a voltage-controlled oscillator that receives a variable voltage signal as an input and generates an output signal having a frequency corresponding to the voltage of the input signal. A first frequency-to-voltage converter to generate, a device for multiplying or dividing the frequency of the reference signal to generate two sub-reference signals of different frequencies, and a voltage signal corresponding to the frequency of each of the above-mentioned sub-reference signals. Output second and third frequency-to-voltage converters,
And the output of the third frequency-to-voltage converter are combined to produce a divided voltage output, and the output of the first frequency-to-voltage converter is compared with the output of this voltage divider as a reference voltage. And a comparator which uses a voltage signal corresponding to the difference as an input signal of the voltage control transmitter.
この発明においては、電圧制御発振器の出力を第1の
周波数−電圧変換器によって電圧信号に変換する一方、
基準信号の周波数をてい倍又は分周して異なる周波数の
2つの副基準信号を作成し、各副基準信号の周波数に対
応する電圧信号を第2及び第3の周波数−電圧変換器が
発生する。また第2及び第3の周波数−電圧変換器の出
力を結合する分圧器によって基準電圧となる分圧出力を
発生し、この基準電圧と上記第1の周波数−電圧変換器
の出力である電圧信号とを比較器によって比較し、その
差に対応した電圧信号を上記電圧制御発振器の入力とす
ることにより、上記電圧制御発信器の出力が上記基準電
圧に対応した出力に制御される。なお、基準電圧は分圧
器の分圧比を変えることにより任意の値とすることが出
来るため、電圧制御発振器の出力も任意の周波数とする
ことが出来る。In the present invention, while the output of the voltage controlled oscillator is converted into a voltage signal by the first frequency-voltage converter,
The frequency of the reference signal is doubled or divided to create two sub-reference signals of different frequencies, and the second and third frequency-to-voltage converters generate voltage signals corresponding to the frequency of each sub-reference signal. . A voltage divider that combines the outputs of the second and third frequency-to-voltage converters generates a divided voltage output that serves as a reference voltage, and generates a reference voltage and a voltage signal that is the output of the first frequency-to-voltage converter. Are compared by a comparator, and a voltage signal corresponding to the difference is input to the voltage-controlled oscillator, whereby the output of the voltage-controlled oscillator is controlled to an output corresponding to the reference voltage. Since the reference voltage can be set to an arbitrary value by changing the voltage dividing ratio of the voltage divider, the output of the voltage controlled oscillator can be set to an arbitrary frequency.
以下、この発明の実施例を図面とともに説明する。第
1図はこの実施例による発振周波数無調整発振回路の構
成を示し、6は基準信号frefをてい倍又は分周するてい
倍器又は分周器で、てい倍数又は分周数はaである。た
だし、てい倍器の場合にはaは正の整数でa=1,2,…と
なり、分周器の場合にはaは正の整数分の1で となる。7は同じく基準信号をfrefをてい倍又は分周す
るてい倍器又は分周器で、てい倍数又は分周数はbであ
り、b=1,2,…又は である。ただし、b>aとする。8a〜8cは入力周波数に
対応した電圧を出力する周波数−電圧変換器(F−V CO
NV)で、その特性はそれぞれ同一特性であり、一例を第
2図に示す。9は周波数−電圧変換器8a,8bの出力電圧V
a,Vbを分圧して、出力信号の周波数に相当する電圧を
得る分圧器で、Ra,Rbからなり、その接続点からの出力
は である。10は分圧器9の出力と周波数−電圧変換器8cの
出力とを比較し、その電位差を出力する比較器である。Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows the configuration of an oscillation frequency non-adjusted oscillation circuit according to this embodiment. Reference numeral 6 denotes a multiplier or a frequency divider which multiplies or divides a reference signal fref. is there. However, in the case of a multiplier, a is a positive integer and a = 1, 2,..., And in the case of a frequency divider, a is a positive integer. Becomes 7 is a multiplier or a frequency divider which multiplies or divides the reference signal by fref, and the multiple or frequency division number is b, and b = 1, 2,. It is. However, it is assumed that b> a. 8a to 8c are frequency-voltage converters (F-VCO) that output voltages corresponding to the input frequencies.
NV), the characteristics are the same, and an example is shown in FIG. 9 is the output voltage V of the frequency-voltage converters 8a and 8b
a, by applying a V b min, voltage divider to obtain a voltage corresponding to the frequency of the output signal, R a, consists R b, is output from the connection point It is. A comparator 10 compares the output of the voltage divider 9 with the output of the frequency-voltage converter 8c, and outputs the potential difference.
次に、動作について説明する。まず、任意の基準信号
frefにてい倍器又は分周器6,7により、希望する任意の
出力周波数f0を間に挟むように周波数変換される。即
ち、a×fref<f0<b×frefとなるようにa,bの値が決
定されているものとする。このように周波数変換された
副基準信号a×fref,b×frefはそれぞれ周波数−電圧変
換器8a,8bに入力され、入力信号周波数に応じた電圧
Va,Vbが出力される。この場合の入力周波数と出力電圧
の関係は第2図に示すような直線特性であり、a×fref
からb×frefまでの間ではその直線性は充分に保たれて
いる。電圧Va,Vbは分圧器9に入力れ、その分圧比Ra;
Rbに応じた出力電圧 が出力されるが、分圧比を適当に選ぶことにより、2つ
の副基準信号a×fref,b×frefの間の任意の周波数に対
応する電圧を得ることができる。一方、電圧制御発振器
1の出力信号f0は周波数−電圧変換器8cに入力され、そ
の周波数に応じた出力電圧V0が出力される。従って、周
波数−電圧変換器8cの出力V0と分圧器9の出力 を比較器10で比較し、その誤差電圧VErrは加算器5で基
準電圧Vrefを加算され、可変電圧Vcontとして電圧制御
発振器1に入力され、その出力周波数を制御する。この
ため、周波数−電圧変換器8cの出力電圧V0は分圧器9の
出力電圧 と等しくなるように制御され、結局電圧制御発振器1の
出力周波数f0は電圧 に対応する周波数 となる。従って、希望の発振周波数f0を、任意の基準信
号frefからa,b,Ra,Rbを適当に決定することにより、無
調整で得ることができる。Next, the operation will be described. First, any reference signal
The Empire multiplier or divider 6 and 7 f ref, is frequency-converted so as to sandwich any output frequency f 0 to the desired. That is, it is assumed that the values of a and b are determined so that a × f ref <f 0 <b × f ref . The sub-reference signals a × f ref and b × f ref thus frequency-converted are input to frequency-voltage converters 8a and 8b, respectively.
V a and V b are output. Relationship between the input frequency and the output voltage in this case is linear characteristics as shown in FIG. 2, a × f ref
The linearity is sufficiently maintained from to b × f ref . Voltage V a, V b is input to a voltage divider 9, the partial pressure ratio R a;
Output voltage according to R b Is output, but by appropriately selecting the division ratio, a voltage corresponding to an arbitrary frequency between the two sub-reference signals a × f ref and b × f ref can be obtained. On the other hand, the output signal f 0 of the voltage controlled oscillator 1 is frequency - is input to the voltage converter 8c, the output voltage V 0 corresponding to the frequency is outputted. Therefore, the frequency - the output of the output V 0 voltage divider 9 of the voltage converter 8c Are compared by a comparator 10, and the error voltage V Err is added to a reference voltage V ref by an adder 5 and input to the voltage controlled oscillator 1 as a variable voltage V cont to control the output frequency. For this reason, the output voltage V 0 of the frequency-voltage converter 8 c is equal to the output voltage of the voltage divider 9. Is controlled so that the output frequency f 0 of the voltage controlled oscillator 1 is equal to the voltage Frequency corresponding to Becomes Therefore, the desired oscillation frequency f 0 can be obtained without adjustment by appropriately determining a, b, R a , and R b from an arbitrary reference signal f ref .
なお、上記実施例においては、希望する出力信号の周
波数が2つの副基準信号a×frefとb×frefの間にある
(a×fref<f0<b×fref)ようにてい倍器又は分周器
6,7を設定したが、第3図(a)及び第4図(a)に示
すように発振回路を構成すれば、周波数−電圧変換器8a
〜8cの直線性が満足している範囲では、必ずしも上記実
施例のような関係になるようにてい倍器又は分周器6,7
を設定する必要はない。即ち、第3図(a)の場合には
第3図(b)に示すようにa×fref<b×fref<f0とな
るように設定する。又、分圧器9と比較器10との間に比
較器11,12を挿入しており、比較器11の出力は となり、比較器12の出力は となるので、 となる。又、第4図(a)の場合には、第4図(b)に
示すようにf0<a×fref<b×frefとなるように設定
し、また分圧器9と比較器10との間に比較器13,14を挿
入しており、比較器13の出力は となり、比較器14の出力は となるので、 となる。In the above embodiment, the frequency of the desired output signal is between the two sub-reference signals a × f ref and b × f ref (a × f ref <f 0 <b × f ref ). Doubler or divider
6, 7 are set, but if the oscillation circuit is configured as shown in FIGS. 3 (a) and 4 (a), the frequency-voltage converter 8a
In the range where the linearity of ~ 8c is satisfied, the multiplier or the frequency divider 6,7 is always set to have the relationship as in the above embodiment.
There is no need to set. That is, in the case of FIG. 3A, the setting is made so that a × f ref <b × f ref <f 0 as shown in FIG. 3B. Further, comparators 11 and 12 are inserted between the voltage divider 9 and the comparator 10, and the output of the comparator 11 is And the output of comparator 12 is So, Becomes In the case of FIG. 4 (a), as shown in FIG. 4 (b), f 0 <a × f ref <b × f ref is set, and the voltage divider 9 and the comparator 10 And comparators 13 and 14 are inserted between them, and the output of the comparator 13 is And the output of comparator 14 is So, Becomes
又、上記各実施例では基準信号が1つの場合について
説明したが、基準信号として周波数の異なる2つの信号
fref1,fref2(fref1<fref2)が与えられている場合で
も第5図に示すような構成で上記各実施例と同様な効果
を奏する。即ち、てい倍器又は分周器6,7にそれぞれ基
準信号fref1,fref2を入力しており、 となる。なお、この例でも副基準信号a×fref1,b×f
ref2と出力信号f0との大小関係はいずれの場合でもよ
い。In each of the above embodiments, the case where one reference signal is used has been described. However, two signals having different frequencies are used as the reference signal.
Even when f ref1 and f ref2 (f ref1 <f ref2 ) are given, the configuration shown in FIG. 5 provides the same effects as the above embodiments. That is, the reference signals f ref1 and f ref2 are input to the multiplier or the frequency dividers 6 and 7, respectively. Becomes In this example, the sub-reference signals a × f ref1 and b × f
magnitude relationship between ref2 and the output signal f 0 good either case.
さらに、上記各実施例では出力信号を単一周波数信号
として説明したが、VTRのようにビデオ信号を変調器に
よりFM信号に変調する場合においても、規定の信号部分
(VTRの場合は同期信号の先端部分)の時間のみ出力信
号を周波数−電圧変換し、その他の時間はその電圧を保
持するようにすれば、FM変調器の発振周波数の調整を無
調整化することができる。この場合の構成を第6図に示
す。図において、1aはFM変調器で、入力電圧に対応した
出力周波数が得られる点では一種の電圧制御発振器と考
えられる。15はビデオ信号の同期信号の先端部分の直流
電位を一定にするクランプ回路で、その直流電位はVref
である。16はFM変調器1aの出力信号foutを周波数−電圧
変換器8cにより変換した電圧のうち同期信号の先端部の
電圧を保持するサンプルホールド回路であり、回路15,1
6はクランプ及びサンプルホールドパルスにより動作す
る。C1はクランプ回路15に入力されるビデオ信号の直流
成分を除去しクランプ電圧を保持するコンデン、C2はサ
ンプルホールド回路16の同期信号の先端部の電圧を保持
するコンデンサであり、基準信号として色搬送波fscを
用いている。基本的動作は上記各実施例と同様であり、
上気したようなビデオ信号の同期信号の先端部の時間の
み周波数−電圧変換し、その他の時間はその電圧を保持
するようにする以外は上記各実施例と同様である。Further, in each of the above embodiments, the output signal is described as a single frequency signal. However, even when a video signal is modulated into an FM signal by a modulator like a VTR, a specified signal portion (in the case of a VTR, a synchronization signal If the output signal is subjected to frequency-to-voltage conversion only during the time of the front end portion, and the voltage is maintained during the other times, the adjustment of the oscillation frequency of the FM modulator can be eliminated. The configuration in this case is shown in FIG. In the figure, reference numeral 1a denotes an FM modulator, which is considered to be a kind of voltage controlled oscillator in that an output frequency corresponding to an input voltage is obtained. 15 is a clamp circuit for a constant DC potential of the distal end portion of the synchronization signal of the video signal, the DC potential V ref
It is. Reference numeral 16 denotes a sample-and-hold circuit that holds the voltage at the leading end of the synchronization signal among the voltages obtained by converting the output signal f out of the FM modulator 1a by the frequency-voltage converter 8c.
6 is operated by a clamp and sample hold pulse. C 1 is a capacitor that removes the DC component of the video signal input to the clamp circuit 15 and holds the clamp voltage, and C 2 is a capacitor that holds the voltage at the tip of the synchronization signal of the sample and hold circuit 16 and serves as a reference signal. A color carrier fsc is used. The basic operation is the same as the above embodiments,
This embodiment is the same as the above embodiments except that the frequency-to-voltage conversion is performed only at the time of the leading end of the synchronizing signal of the video signal, and the voltage is maintained at other times.
以上のようにこの発明によれば、任意の基準信号の周
数をてい倍又は分周して異なる周波数の2つの副基準信
号を作成し、各副基準信号の周波数に応じた電圧を分圧
器に供給して基準電圧となる分圧出力を発生すると共
に、上記基準電圧と電圧制御発振器の出力に対応した電
圧信号との差信号に対応した信号を電圧制御発振器の入
力とするようにしているため、基準信号の制約を受けず
に発振周波数を決定することができ、また分圧比を変更
するだけで発振周波数を簡単に変更することができる無
調整発振回路が得られる。As described above, according to the present invention, the frequency of an arbitrary reference signal is multiplied or divided to generate two sub-reference signals of different frequencies, and a voltage corresponding to the frequency of each sub-reference signal is divided by a voltage divider. To generate a divided output as a reference voltage, and a signal corresponding to a difference signal between the reference voltage and a voltage signal corresponding to the output of the voltage controlled oscillator is used as an input of the voltage controlled oscillator. Therefore, it is possible to determine an oscillation frequency without being restricted by the reference signal, and to obtain an unadjusted oscillation circuit that can easily change the oscillation frequency only by changing the voltage division ratio.
第1図及び第2図はこの発明の第1の実施例による回路
構成図及び周波数−電圧変換特性図、第3図(a),
(b)はこの発明の第2の実施例による回路構成図及び
周波数−電圧変換特性図、第4図(a),(b)はこの
発明の第3の実施例による回路構成図及び周波数−電圧
変換特性図、第5図及び第6図はこの発明の第4及び第
5の実施例による回路構成図、第7図及び第8図は従来
回路の構成図である。 1……電圧制御発振器、1a……FM変調器、6,7……てい
倍器又は分周器、8a〜8c……周波数−電圧変換器、9…
…分圧器、10〜14……比較器、15……クランプ回路、16
……サンプルホールド回路。 なお、図中同一符号は同一又は相当部分を示す。FIGS. 1 and 2 are a circuit configuration diagram and a frequency-voltage conversion characteristic diagram according to a first embodiment of the present invention, and FIGS.
4B is a circuit diagram and a frequency-voltage conversion characteristic diagram according to a second embodiment of the present invention, and FIGS. 4A and 4B are a circuit diagram and frequency-voltage diagram according to a third embodiment of the present invention. FIG. 5 and FIG. 6 are circuit configuration diagrams according to the fourth and fifth embodiments of the present invention, and FIG. 7 and FIG. 8 are configuration diagrams of a conventional circuit. 1 ... voltage controlled oscillator, 1a ... FM modulator, 6,7 ... multiplier or frequency divider, 8a-8c ... frequency-voltage converter, 9 ...
... voltage divider, 10-14 ... comparator, 15 ... clamp circuit, 16
…… Sample hold circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
圧に対応した周波数の出力信号を発する電圧制御発信
器、この電圧制御発信器の出力信号に対応した電圧信号
を発生する第1の周波数−電圧変換器、基準信号の周波
数をてい倍又は分周して異なる周波数の2つの副基準信
号を発生する装置、上記各副基準信号の周波数に対応す
る電圧信号をそれぞれ出力する第2及び第3の周波数−
電圧変換器、上記第2及び第3の周波数−電圧変換器の
出力を結合し、分圧出力を生ずる分圧比可変の分圧器及
びこの分圧器の出力を基準電圧として上記第1の周波数
−電圧変換器の出力を比較し、その差に対応した電圧信
号を上記電圧制御発信器の入力信号とする比較器を備え
た発信周波数無調整発振回路。1. A voltage controlled oscillator that receives a variable voltage signal as input and generates an output signal having a frequency corresponding to the voltage of the input signal, and a first signal that generates a voltage signal corresponding to the output signal of the voltage controlled oscillator. A frequency-to-voltage converter, a device that doubles or divides the frequency of the reference signal to generate two sub-reference signals of different frequencies, a second and a second device that respectively output voltage signals corresponding to the frequencies of the respective sub-reference signals Third frequency-
A voltage converter, a voltage divider that combines the outputs of the second and third frequency-to-voltage converters to generate a divided voltage output, and a variable voltage-dividing ratio; An oscillation frequency non-adjustable oscillation circuit comprising: a comparator that compares outputs of converters and uses a voltage signal corresponding to the difference as an input signal of the voltage-controlled oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121833A JP2737115B2 (en) | 1990-05-12 | 1990-05-12 | Oscillation frequency non-adjustable oscillation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121833A JP2737115B2 (en) | 1990-05-12 | 1990-05-12 | Oscillation frequency non-adjustable oscillation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0418811A JPH0418811A (en) | 1992-01-23 |
| JP2737115B2 true JP2737115B2 (en) | 1998-04-08 |
Family
ID=14821061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2121833A Expired - Fee Related JP2737115B2 (en) | 1990-05-12 | 1990-05-12 | Oscillation frequency non-adjustable oscillation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2737115B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2327092A1 (en) * | 1973-05-28 | 1974-12-12 | Siemens Ag | CIRCUIT ARRANGEMENT FOR CONVERTING AN INPUT FREQUENCY INTO AN OUTPUT FREQUENCY |
-
1990
- 1990-05-12 JP JP2121833A patent/JP2737115B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0418811A (en) | 1992-01-23 |
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