JP2740263B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to a method for forming a semiconductor memory device having one transistor cell having a stack structure.

(B) Conventional technology The structure of a conventional one-transistor cell semiconductor memory device having a stacked structure and a method of forming the same are described in IEEE International.
Electron Devices Meeting Tech.Dig. (1988) P592-P
Introduced in 595.

According to this structure, since the storage node electrode and the cell plate electrode are formed so as to be folded on each other with the SiO ₂ film as a boundary, the area on the plane is increased only by increasing the number of overlapping layers. Without this, the storage capacity of the SiO ₂ film can be dramatically increased.

For this reason, the semiconductor memory device can be further densified and highly integrated.

(C) Problems to be Solved by the Invention However, according to the conventional forming method, a storage node electrode having multiple wings is formed and then a plate electrode is formed therebetween. There is a point.

First, the wings of the storage node electrode tend to break during and after formation.

Second, it is difficult to dope impurities into the cell plate electrode made of a polycrystalline silicon film formed between the wings of the storage node electrode, and a complicated process such as two-step doping is required. It is.

SUMMARY OF THE INVENTION The present invention has been made in view of such conventional problems, and solves these problems. A semiconductor capable of reliably and easily forming wings of a storage node electrode and a cell plate electrode. It is an object of the present invention to provide a method for manufacturing a storage device.

(D) Means for Solving the Problems In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor memory device, comprising the steps of: forming a field effect transistor on a semiconductor substrate; A first insulating film for interlayer insulation so as to cover the first insulating film, and a first conductive film on the insulating film;
Forming a second insulating film on the conductive film, and partially removing the second insulating film, the first conductive film, and the first insulating film to form one of the field effect transistors. Providing a first opening on the source / drain impurity region; covering a side portion of the first conductive film exposed by the opening step with a third insulating film; The second which embeds and covers the whole surface
Forming a second conductive film, forming a second opening by partially removing the second conductive film so that the second insulating film is exposed, and forming the second conductive film. Forming a fourth insulating film covering the first insulating film; and partially exposing the second conductive film through the second opening to expose a part of the first conductive film. Forming a third conductive film filling the entire surface of the second opening and covering the entire surface; and partially removing the third conductive film so that the fourth insulating film is exposed. Forming a third opening, and forming a fifth insulating film covering the third conductive film.

(E) Operation According to the method of manufacturing a semiconductor memory device of the present invention, each wing of a storage node electrode having a plurality of wings and a cell plate electrode having a plurality of wings formed so as to alternately overlap the storage node electrode. Are alternately stacked one by one in the overlapping order, so that the blades are extremely unlikely to be damaged during and after manufacturing.

Similarly, when an impurity is implanted into a conductive film (for example, a polycrystalline silicon film) forming a wing, the impurity is sufficiently and surely implanted because the conductive film has at least an upper surface exposed. And the parasitic resistance of the electrode can be reduced.

Furthermore, according to the semiconductor memory device of the present invention, since it is formed by the above-described manufacturing method, it has structural stability,
Therefore, the reliability is improved.

(F) Example Next, an example of the present invention will be described with reference to the drawings. 1A to 1M are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

First, as shown in FIG. 1A, after an SiO ₂ film (2) and a Si ₃ N ₄ film (3) are sequentially formed on a Si substrate (1), the Si ₃ N ₄ film (3) is partially removed. I do.

Thereafter, as shown in FIG.
After forming the SiO ₂ film (4) and then removing the entire surface of the Si ₃ N ₄ film (3) and the SiO ₂ film (2), it is oxidized to form a thin gate SiO ₂ film (5).

Next, as shown in FIG. 7C, after a poly-Si film is deposited on the entire surface by the CVD method, phosphorus or the like is diffused to make the poly-Si film conductive. Thereafter, the poly-Si film is patterned to form poly-Si gate electrodes (6a) and (6b), and further oxidized to form SiO ₂ films (7a) and (7b) covering the gate electrodes (6a) and (6b). After the formation, arsenic or the like is ion-implanted to form source / drain regions (8a) to (8c).

Next, as shown in FIG. D, a portion of the SiO ₂ film (5) on the source / drain region (6b) is removed to form an opening (9), and then a poly-Si film is formed by a CVD method. After the formation, phosphorus or the like is diffused to be conductive, then silicidized, and further patterned to form a bit line (10) of the semiconductor memory device.

Next, as shown in FIG.
An iO ₂ film (11), an N-type poly-Si film (12), and a SiO ₂ film (13) are sequentially formed.

Then, using the same mask, the SiO ₂ film (13), poly-Si
An opening (14) is formed by removing the film (12) and part of the SiO ₂ film (11). Thereafter, thermal oxidation is performed to cover the exposed side of the poly-Si film (12) to form an SiO ₂ film (16) (FIG. F). At this time, the SiO ₂ film (1
7) forms.

Next, as shown in FIG.
The SiO ₂ film (17) is removed by E). The SiO ₂ film (1
The thickness of 5) is slightly reduced by the etching at this time.

Next, as shown in FIG. 5H, after a poly-Si film is deposited on the entire surface by the CVD method, an impurity such as phosphorus is implanted to make it conductive, and then an opening (19) is formed by patterning.

Next, as shown in FIG. 1A, a thin Si ₃ N ₄ film (20) is formed by a CVD method. After that, thermal oxidation may be performed to form an extremely thin SiO ₂ film on the Si ₃ N ₄ film (20). Thereby, the film thickness as the insulating film is improved, and the reliability is improved.

Next, as shown in FIG.
An opening (21) is formed by removing a part of the O ₂ film (15).

Next, as shown in FIG. 9K, after a poly-Si film (22) is deposited on the entire surface, phosphorus or the like is diffused to make it conductive. Thereby, the poly-Si film (12) and the poly-Si film (22) are electrically connected.

Thereafter, as shown in FIG. 4L, the poly Si film (22) is patterned to form an opening (23), and then a Si ₃ N ₄ film (24) is formed by a CVD method.

Further, through similar steps, as shown in FIG.
A storage node electrode having poly-Si films (18) and (25) forming a layer wing, and a cell plate electrode having poly-Si films (21) and (27) forming a two-layer wing A semiconductor memory device according to an embodiment of the present invention is provided.

Note that a necessary number of blades can be created by repeating the same process.

As described above, according to the embodiment of the present invention, it is possible to obtain a required amount of storage capacitance without increasing the area on a plane, so that it is possible to increase the density and integration of the semiconductor memory device. It becomes possible.

Further, according to the embodiment of the present invention, the wings of the overlapping electrodes are formed by stacking sequentially from the bottom, so that each wing is broken or chipped during the manufacturing process or even after the manufacturing process. There is an effect that there is little.

Furthermore, when phosphorus or the like is diffused into the poly-Si film constituting each wing to make it conductive, the conduction is performed from the exposed upper surface of the poly-Si film, so that the implantation of impurities is reliably performed without variation. As a result, the voltage dependence of the capacitance is reduced and a large capacitance can be obtained.

(G) Effects of the Invention As described above, according to the semiconductor memory device of the present invention, a required amount of storage capacitance can be obtained without increasing the area on a plane. Higher density and higher integration can be achieved.

According to the method for manufacturing a semiconductor memory device of the present invention, the conductive film forming the wings of the storage node electrode and the conductive film forming the wings of the cell plate electrode are formed in the overlapping order. The wing does not break during or after manufacture.

Further, according to the manufacturing method of the present invention, when each conductive film is composed of a poly-Si film, the impurity diffusion for making the poly-Si film conductive is performed from the exposed upper surface of the poly-Si film to the whole. In addition, the dispersion of the implanted impurities is reduced, the voltage dependence of the capacitance is reduced, and a large capacitance is obtained.

[Brief description of the drawings]

1A to 1M are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present invention.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yutaka Ota 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-59-231851 (JP, A) JP-A Sho 59-175153 (JP, A)

Claims (5)

(57) [Claims] A step of forming a field-effect transistor on a semiconductor substrate; a first insulating film for interlayer insulation so as to cover the field-effect transistor; a first conductive film on the insulating film; Forming a second insulating film on the first conductive film; and partially removing the second insulating film, the first conductive film, and the first insulating film to form the second field effect transistor. Providing a first opening on one of the source / drain impurity regions; covering a side portion of the first conductive film exposed by the opening step with a third insulating film; Forming a second conductive film that fills the opening and covers the entire surface; and removing the second conductive film partially so that the second insulating film is exposed. Forming a portion, and forming a fourth insulating film covering the second conductive film. A step of partially removing the second insulating film through the second opening and exposing a part of the first conductive film; embedding the second opening in the entire surface; And the third that covers the whole surface
Forming a third conductive film, forming a third opening by partially removing the third conductive film so that the fourth insulating film is exposed, and forming the third conductive film. Forming a fifth insulating film covering the semiconductor device. A second conductive film and a fourth conductive film connected to one of the source / drain impurity regions of the field effect transistor are used as storage node electrodes; The film is used as a cell plate electrode facing the storage node electrode, the second insulating film, the third insulating film, and the fourth insulating film are used as a capacitance between the storage node electrode and the cell plate electrode. 2. The method according to claim 1, wherein the drain impurity region is a bit line. 3. A field effect transistor having a symmetric structure, a storage node electrode, a cell plate electrode, and a capacitance between the electrodes are formed on both sides of the source / drain impurity region serving as a bit line. 3. The method of manufacturing a semiconductor memory device according to claim 2, wherein: 4. The method according to claim 2, wherein each conductor film is a polycrystalline silicon film. 5. An insulating film forming a capacitance between electrodes is made of Si ₃ N ₄
3. The method according to claim 2, further comprising a film.