JP2741990B2 - Computer power outage protection device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer using a battery as a power source, and more particularly, to a method of recovering a power failure by protecting the contents of a memory when the power supply from the battery is interrupted during operation. The present invention relates to an instantaneous power failure protection device for a computer that can continue processing afterwards.

[0002]

2. Description of the Related Art In recent years, portable devices equipped with small computers have been provided as seen in laptop personal computers and word processors. Since these devices cannot be used by connecting a cord to a commercial power source as in the related art, a battery is used as a power source.

[0003]

In such a small computer using a battery as a power source, the power supply to each circuit may be momentarily interrupted due to a shock or the like during operation. For this reason, conventionally, a large-capacity capacitor that can supply power at the momentary interruption is connected so that the computer continues to operate even during the momentary interruption time.

That is, the capacity C of the capacitor for supplying the necessary power at the momentary interruption is:

[0005]

C = I × t / ΔV where ΔV is the voltage drop allowed during an instantaneous interruption, t is the instantaneous interruption time, and I is the current consumption of the system.

If ΔV = 0.5 V, t = 50 ms, I
= 200 mA, the capacitance C of the capacitor was C = 50 × 200 / 0.5 = 20,000 μF, which was very large, making it difficult to mount with a small computer.

Even if only a CMOS IC is used, power consumption is large when a clock is input, and a similar capacity is required.

In the present invention, attention is paid to the fact that the power consumption is extremely low when the CMOS IC does not perform a switching operation. It is an object of the present invention to provide an instantaneous power failure protection device for a computer capable of retaining the contents of a simple memory.

[0009]

In order to solve the above-mentioned problems, an instantaneous power failure protection device for a computer according to the present invention detects an instantaneous interruption of power supply from a battery during operation in a computer powered by a battery. A voltage drop detection circuit that outputs a DMA request signal during the detection of the instantaneous interruption; performs a memory refresh operation based on the request signal output from the voltage drop detection circuit; , And a system clock control circuit for stopping clock oscillation based on a request signal output from the voltage drop detection circuit and an acknowledge signal output from the DMA controller.

[0010]

The voltage drop detection circuit detects an instantaneous interruption of the power supply from the battery during operation, and when the instantaneous interruption is detected, outputs a DMA request signal during the detection period.

The DMA controller performs a refresh operation of the memory based on the request signal output from the voltage drop detection circuit, and outputs a DMA acknowledge signal.

On the other hand, the system clock control circuit, based on a request signal output from the voltage drop detection circuit and an acknowledge signal output from the DMA controller,
Stop clock oscillation. As a result, even if the power supply from the battery is momentarily interrupted during operation, the contents of the memory are protected, and processing can be continued even after recovery from the power failure. In addition, since all clocks are stopped at the moment of an instantaneous interruption, there is no switching device, and
In the case of using an OS / IC, current consumption can be suppressed to about one hundredth of that during operation.

[0013]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the electrical configuration of the instantaneous power failure protection device for a computer according to the present invention.

In FIG. 1, an output of a battery 1 serving as a power source of a computer is supplied to each circuit block via a power supply circuit 2 and a capacitor 3 for protecting the instantaneous interruption when the battery 1 instantaneously shuts down. I have. The output of the battery 1 is supplied to a voltage drop detection circuit 4 for detecting a voltage drop due to an instantaneous interruption of the battery 1.
And the output of the voltage drop detection circuit 4 is DMA
(Direct Memory Access) The controller 5 is guided to a system clock control circuit 7 via an AND circuit 6.

The voltage drop detection circuit 4 detects the instantaneous interruption by detecting a voltage drop when the battery 1 is instantaneously interrupted due to an impact or the like, and a DMA request signal (DRQ signal) during the detection. Is output.

The DMA controller 5 receives the DRQ signal from the voltage drop detection circuit 4 and enters a DMA cycle, generates an acknowledge signal (ACK signal) of the DMA, and transmits this acknowledge signal to the system clock via the AND circuit 6. Output to the control circuit 7 and the like. Also, DMA
In the cycle, the DMA controller 5 and the memory 9 are directly connected by the address bus 11.

The system clock control circuit 7 sends a DMA clock to the DMA controller 5 during operation,
Output the CPU clock, and output a DRQ signal from the voltage drop detection circuit 4 to the DMA controller 5.
When an acknowledge signal is received from the CPU, the oscillation of the clock is stopped.

A memory 9 and an input / output control circuit 10 are connected bidirectionally to the CPU 8. The power supply voltage Vcc from the power supply circuit 2 is supplied to each of the circuit blocks 5, 7, 8, 9, and 10.

Upon receiving the DRQ signal from the voltage drop detection circuit 4, the DMA controller 5 sets the data bus, address bus, control bus, and the like of the CPU 8 to high impedance, disconnects the CPU 8 from these buses, and connects the DMA controller 5 with the memory. 9 is directly connected by an address bus 11 to perform a refresh operation of the memory 9.

Next, the operation of the instantaneous power failure protection device having the above configuration will be described.

When the computer operates, the power supplied from the battery 1 is supplied to each of the circuit blocks 5, 7,
8, 9, and 10, and each circuit block 5,
7, 8, 9, and 10 operate by receiving power supply from the battery 1.

During such an operation, when the battery 1 is momentarily interrupted by, for example, an impact or the like, each of the circuit blocks 5, 7,.
8, 9, and 10 thereafter receive power from the capacitor 3 and continue to operate. At this time, the voltage drop detection circuit 4
When the momentary interruption of the battery 1 is detected by the voltage drop, the DRQ signal is supplied to the DMA controller 5 and one input of the AND circuit 6 during the detection period.

When the DMA controller 5 receives the DRQ signal from the voltage drop detection circuit 4, it enters a DMA cycle. That is, the data bus, address bus, control bus, etc. of the CPU 8 are set to high impedance.
While disconnecting the CPU 8 from these buses,
The controller 5 and the memory 9 are directly connected by the address bus 11. As a result, the DMA controller 5 and the memory 9 enter a refresh cycle, and the refresh operation of the memory 9 is performed. As a result, even when the power supply from the battery 1 is momentarily interrupted during operation, the contents of the memory 9 are retained, and processing can be continued even after recovery from power failure.

At this time, the DMA controller 5
An acknowledge signal for DMA is generated, and this acknowledge signal is supplied to the other input of the AND circuit 6. When the DRQ signal and the acknowledge signal are guided to both inputs, the AND circuit 6 outputs an operation stop signal to the system clock control circuit 7. The system clock control circuit 7 stops the clock oscillation based on the operation stop signal.

That is, when the system clock control circuit 7 stops, all clocks stop, and there is no switching device. Therefore, when the whole is composed of a CMOS IC, the current consumption is reduced. It can be reduced to about one hundredth of that during operation.

Here, the time from the stop of the voltage to the start of the refresh operation is 1 μs, and the current consumption during that time is 200 m.
A, assuming that the clock stop period is 50 μs and the current consumption during this period is 500 μA, the capacitance C of the capacitor 3 for compensating for the 50 ms instantaneous interruption is only required to be about 100 μF.

Thereafter, when the instantaneous interruption is released, the output of the DRQ signal from the voltage drop detection circuit 4 is stopped. Thereby, the system clock control circuit 7 starts oscillating the clock and outputs the clock to the CPU 8. Also, DM
A controller 5 releases the DMA cycle and
The connection between the controller 5 and the memory 9 by the address bus 11 is released. As a result, the CPU 9 is connected to each bus again, so that the CPU 8 can continue the operation again.

FIG. 2 is an explanatory diagram showing the operation flow of the main part of the above-mentioned momentary power failure protection device.

As described above, according to the instantaneous power failure protection device of the present invention, when the battery 1 is momentarily interrupted, the contents of the memory 9 are retained, and the capacity of the instantaneous interruption protection capacitor 3 is also 100.
Since a capacitor with a small capacitance of about μF is sufficient, the capacitor 3
Can be reduced in size.

[0031]

The instantaneous power failure protection device for a computer according to the present invention detects an instantaneous interruption of power supply from a battery during operation, and outputs a DMA request signal while the instantaneous interruption is detected. A drop detection circuit, a DMA controller that performs a memory refresh operation based on a request signal output from the voltage drop detection circuit, and outputs an acknowledge signal of DMA, a request signal output from the voltage drop detection circuit, The system has a system clock control circuit that stops the oscillation of the clock based on the acknowledge signal output from the controller. The capacity of the capacitor may be small, and the size of the capacitor can be reduced. Further, by performing the refresh operation, the computer can be constituted by a large-capacity low-priced D-RAM or a pseudo S-RAM.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of an instantaneous power failure protection device for a computer according to the present invention.

FIG. 2 is an explanatory diagram showing a flow of operation of a main part of the instantaneous power failure protection device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Battery 3 Capacitor 4 Voltage drop detection circuit 5 DMA controller 7 System clock control circuit 9 Memory

Claims (1)

(57) [Claims] 1. A voltage drop detection circuit for detecting an instantaneous interruption of power supply from a battery during operation and outputting a DMA request signal during detection of the instantaneous interruption in a computer powered by a battery. A DMA controller that performs a memory refresh operation based on a request signal output from the voltage drop detection circuit and outputs a DMA acknowledge signal; a request signal output from the voltage drop detection circuit;
An instantaneous power failure protection device for a computer, comprising: a system clock control circuit for stopping oscillation of a clock based on an acknowledge signal output from an MA controller.