JP2745153B2 - Digital-to-analog conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital-to-analog conversion circuit. The present invention particularly relates to a digital-to-analog conversion circuit that weights, adds, and converts an output switched by a pulse width signal for each of an upper digit and a lower digit to an analog signal.

〔Overview〕

The present invention relates to a digital-to-analog conversion circuit that converts a digital input into an analog output by performing switching at a duty ratio of a pulse of an upper digit and a lower digit, wherein an output divided according to weighting of a lower digit is added without an addition resistor. By adding to the high-order digit, digital-to-analog conversion is made more stable and more accurate.

[Conventional technology]

In a digital-to-analog conversion circuit, as a method of increasing the conversion accuracy and increasing the speed, a digital signal is separated into an upper digit and a lower digit, and a pulse width signal having a duty ratio corresponding to the upper digit and the lower digit is generated. In some cases, the pulse width signal is added by a weighting addition circuit and converted into an analog signal.

 The configuration is shown in FIG.

A digital-to-analog conversion circuit that separates the input digital signal into an upper digit and a lower digit and converts the input digital signal into an upper bit and a lower bit, and a separating circuit 11 that separates the input digital signal into an upper bit and a lower bit. A pulse width signal generation circuit (PWM) 12 for converting a pulse width signal having a duty ratio corresponding to the upper bit and a pulse width signal generation circuit (PWM) for converting a lower bit to a pulse width signal having a duty ratio corresponding to the lower bit 13), a weighted addition circuit 14 for performing weighted addition of the pulse width signal of the upper bit and the pulse width signal of the lower bit according to the weight assigned to the upper bit and the lower bit, and a weighted addition circuit 14. An averaging circuit 15 for averaging the added output and outputting the result as an analog signal.

The addition of the high-order bit and the low-order bit in this weighting addition circuit is performed by a weighted addition resistor. For example, as shown in FIG. 4, a switch SW ₁ is assigned to a high-order bit, and a switch SW ₂ is assigned to a low-order bit.
Each upper bit reference voltage E _s input from 16, and the switching duty ratio of the pulse width signal of the lower bit, the switch SW ₁ of the summing resistor R which is weighted high-order bit output, the output of the switch SW ₂ The signal was added to the operational amplifier (AMP) 17 of the averaging circuit 15 via the addition resistor nR weighted to the lower bit and coupled. The switched output is averaged by the operational amplifier 17 and taken out at the output terminal 18 as an analog output.

[Problems to be solved by the invention]

However, the addition of the switching output of the upper bit and the lower bit using the addition resistor in this way cannot further increase the stability and accuracy. That is,
Since the addition resistors are used by connecting discrete resistors, the stability with respect to aging and temperature differs individually, and the stability of the entire addition resistor cannot be increased. In addition, high-precision ones cannot be prepared,
It is difficult to improve the stability, and the use of ultra-high-precision, ultra-high-stability resistors makes the digital-to-analog conversion circuit expensive.

The present invention is to solve such a problem, and to provide a digital-to-analog conversion circuit capable of improving the accuracy and stability by adding the switching outputs of the upper bit and the lower bit without using an addition resistor. With the goal.

[Means for solving the problem]

The present invention provides means for separating an input digital signal into an upper digit and a lower digit, a circuit for generating a first pulse width signal corresponding to the upper digit, and a second pulse corresponding to the lower digit. A digital-to-analog conversion circuit comprising a circuit for generating a width signal, a circuit for weighting and adding voltages corresponding to the two pulse width signals, and a circuit for averaging the added output. The adding circuit includes a voltage dividing circuit that generates a voltage corresponding to the weight of the lower digit, and a second switch that selects an output voltage or a common potential of the voltage dividing circuit according to the second pulse width signal. A buffer amplifier that receives the output voltage of the second switch as an input, a reference voltage source that generates a voltage corresponding to the weight of the upper digit based on the output of the buffer amplifier, A first switch for selecting a voltage generated by a reference voltage source or a voltage at the base point according to the first pulse width signal.

[Action]

The reference voltage is switched by the first switch corresponding to the upper bit at the duty ratio of the pulse width signal of the upper bit and coupled to the averaging circuit. The divided voltage or the common potential obtained by dividing the reference voltage in accordance with the weighting of the lower bits is switched by the second time division switch assigned to the lower bits at the duty ratio of the pulse width signal of the lower bits. And is coupled to the base side of the first switch via a buffer amplifier.

Therefore, the output corresponding to the weighting of the lower bit can be added to the output corresponding to the weighting of the upper bit without adding resistance.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a weighted addition circuit having a configuration according to an embodiment of the present invention.

The features of the weighting and adding circuit in the digital-to-analog conversion circuit of the present embodiment include a voltage dividing circuit 4 for generating a voltage corresponding to the weighting of the lower digit, an output voltage of the voltage dividing circuit 4 or a common potential. , A buffer switch 6 that receives the output voltage of the second switch 5 as an input, and an output of the buffer amplifier 6 as a base point. And a Zener diode 2 as a reference voltage element for generating a reference voltage _Er1 corresponding to the weight of the upper digit,
A first switch for selecting a voltage generated by the Zener diode or a voltage at the base point according to a first pulse width signal corresponding to an upper bit.

That is, the circuit of this embodiment includes a constant current source 1, a Zener diode 2 having one end connected to the constant current source 1 and generating a reference voltage _Er1 assigned to the upper bit, and a switch S corresponding to the upper bit. _1a and the switch S _1b have two contact paths, and when the switch S _1a conducts,
The switch _S1b is non-conductive, only one of the switches is closed, and the output between both switch contacts is provided. The switch S1b includes a switch 3 connected in parallel with the zener diode 2. The output of the switch 3 is connected to the averaging circuit 7. A voltage divider 4 for dividing the reference voltage E _r1 by a ratio n corresponding to the weighting of the upper bit and the lower bit, and the output of the voltage divider 4 is mutually conductive according to the lower bit,
It is led to a switch 5 having switches S _2a and S _2b that are non-conductive. The output of the switch 5 is led to the operational amplifier 6, and the output of the operational amplifier 6 is the switch in the switch 3 described above.
S _1b and one terminal of the Zener diode 2. The output of the switch 3 is guided to an averaging circuit 7 for averaging the analog output, digital-to-analog conversion output E _o of upper bits and lower bits are added is taken as the output of the averaging circuit 7.

Next, the operation of the circuit of this embodiment will be described with reference to FIG. FIG. 2 illustrates the waveform of digital-to-analog conversion by the circuit of the present embodiment.

The reference voltage _Er1 is generated in the Zener diode 2 by the constant current from the constant current source 1. The reference voltage _Er1 is switched by the switch 3 at the duty ratio (T ₁ : T ₀ ) of the pulse width signal of the upper bit. As shown in FIG. 2A, when the duty ratio of the upper bit is T ₁ : T ₀ , a switching output as shown in FIG. 2A is output as the output V ₁ of the switch 3 as shown in FIG. You.

The voltage E _r2 corresponding to the lower bits divided into 1 / n by the voltage dividing circuit 4 is the duty ratio of the pulse width signal of the low-order bits by the switch 5 is switched in (T ₂ T _0), the output Is input to the operational amplifier 6 and coupled to the switch _S1b side of the switch 3. Output between the common potential switched by the pulse width signal of this lower bit
V ₂ is as shown in FIG. 2 (b).

Here, the switch S _1b closed switch S _1a of the switch 3
Is open, the output V ₂ of the operational amplifier 6 is added to the base point side of the switch 3.
The voltage E _r2 corresponding to the lower bit is superimposed on the reference voltage E _r1 and added to V ₀ , and the sum is input to the averaging circuit 7. Also,
When the switch S _1b of the switch 3 is closed, the output V ₀ which switch 3 appears a voltage E _r2 corresponding to the lower bits is input to the averaging circuit 7.

Therefore, as shown in FIG.
Voltage V ₀ to be input has a obtained by adding the output of the V ₀ = V ₁ + V _2, and the switch 3 respectively and the switch 5 to the.

The averaging circuit 7 averages the output V ₀ obtained by adding the upper bit and the lower bit to obtain a digital-to-analog conversion output.
Output as E _o .

That is, the digital-to-analog conversion output E _o is The output is proportional to the duty ratio of the pulse width signal of the upper bit and the lower bit.

If the above equation (1) is made more strict,
The voltage E _r2 divided for the lower bits is (1 / n) E _r1
Rather, it is 1 / n of the sum of the lower bit switching output V ₂ and Becomes Therefore, the voltage dividing ratio n of the voltage dividing circuit 4 is 1 /
In consideration of (1-1 / n), it is preferable to determine the value corresponding to the weight of the upper bit and the lower bit.

〔The invention's effect〕

As described above, according to the present invention, the switching outputs of the upper bit and the lower bit can be added without passing through the addition resistor. The voltage dividing circuit of the present invention does not use resistors manufactured as individual elements, but only needs to output a terminal determined by a voltage dividing ratio from one resistor, so that the change of the voltage dividing resistor with respect to temperature change or aging is proportional. And
Its stability or accuracy can be improved as compared with those using an addition resistor.

Further, a digital-to-analog conversion circuit can be configured with inexpensive circuit elements.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an embodiment. FIG. 2 is a waveform chart for explaining the operation of the embodiment. FIG. 3 is a block diagram showing a digital-to-analog conversion circuit. FIG. 4 shows a conventional weighted addition circuit. DESCRIPTION OF SYMBOLS 1 ... Constant current source, 2 ... Zener diode, 3 and 5 ... Switch, 4 ... Divider circuit, 6, 17 ... Operational amplifier, 7, 15 ... Averaging circuit, 11 ... Separation circuit, 12, 13 ... Pulse width signal Generation circuit, 14: weighted addition circuit, 15: averaging circuit, 16: terminal, 18: output terminal.

Claims (1)

(57) [Claims] 1. A means for separating an input digital signal into an upper digit and a lower digit, a circuit for generating a first pulse width signal corresponding to the upper digit, and a second signal corresponding to the lower digit. A digital-to-analog conversion circuit comprising: a circuit that generates a pulse width signal; a circuit that weights and adds the voltages corresponding to the two pulse width signals; and a circuit that averages the added output. A voltage dividing circuit (4) for generating a voltage corresponding to the weighting of the lower digit; and a voltage selecting circuit for selecting an output voltage or a common potential of the voltage dividing circuit according to the second pulse width signal. A second switch (5), a buffer amplifier (6) for inputting an output voltage of the second switch, and a voltage corresponding to the weight of the upper digit is generated based on the output of the buffer amplifier. And a first switch (3) for selecting a generated voltage of the reference voltage source or a voltage of the base point according to the first pulse width signal. Digital-to-analog conversion circuit.