JP2746982B2 - Variable delay circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a variable delay circuit composed of a COMS (complementary MOS transistor) circuit, and more particularly to a power saving circuit.

[Conventional technology]

Conventionally, there has been proposed a variable delay circuit having a shift register configuration in which flip-flops configured by COMS circuits are connected in multiple stages. For example, as shown in FIG. ₂ , a shift register is formed by connecting _n flip-flops FF ₁ , FF ₂ , FF ₃ ,..., FF _n in series, and a signal is sent to the first flip-flop FF ₁ The signals are input and the signals are sequentially shifted to delay. Then, the output of each flip-flop is selected by a selector SE.
L and different outputs are obtained by selecting the output in this selector SEL.

[Problems to be solved by the invention]

In the above-described conventional variable delay circuit, the signals output from the flip-flops are sequentially input to the next-stage flip-flop. Therefore, even when the delay amount is small, that is, when all the flip-flops are used, Is operating. For this reason, even if each flip-flop is composed of CMOS to reduce power consumption,
Each flip-flop is always operating, and there is a problem that the effect of reducing power consumption cannot be obtained.

An object of the present invention is to provide a variable delay circuit that can reduce power consumption.

[Means for solving the problem]

In the variable delay circuit according to the present invention, flip-flops constituted by CMOS circuits are arranged in multiple stages, and a signal input to the input side of the first-stage flip-flop is passed through by selecting the flip-flops of the second and subsequent stages. In the circuit for varying the delay of the signal output from the output side of the flip-flop selected as the last stage to the signal output terminal, the output side of each flip-flop except the last stage flip-flop has this output side. A switch for switching connection between the input side of the flip-flop of the next stage and the signal output terminal is connected.

[Action]

In the above-described configuration, the operations of the flip-flops after the switch that has been switched to the output side are stopped, and the power consumption of these flip-flops is reduced.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.
In the figure, n flip-flops FF ₁ , FF ₂ , FF ₃ ,..., FF _n constituted by a CMOS circuit are connected in series, and these constitute a shift register. Further, each switch on the output side of the flip-flops _{SW 1, SW 2, SW 3} , ..., are connected to SW _n. These switches are normally connected to one contact,
It is configured such that only one of the switches can be selectively switched to the other contact point by an operation. These switches have one contact connected to the input of the next-stage flip-flop and the other contact commonly connected as an output. Incidentally, one contact of the switch SW _n of the last stage is open.

According to this configuration, by selecting one of the switches and switching the contact to the other, the signals that have passed through the number of flip-flops up to the selected switches can be taken out as an output. Can be obtained. For example, in the example of FIG. 1, since the switching by selecting the switch SW _2, signal the flip-flop FF _1, FF ₂
Only the delay due to

In this case, since no signal is input to the flip-flops FF ₃ ,..., FF _n after the selected switch SW ₂ ,
These flip-flops are brought into a stationary state, and the operation is substantially stopped. Thereby, at least the switch SW ₂
Subsequent flip-flop FF _3, ..., it is possible to reduce the power consumption of minutes FF _n to work.

〔The invention's effect〕

As described above, the present invention provides a multi-stage CMOS
In a variable delay circuit comprising flip-flops constituted by a circuit, an output side of each of the flip-flops except a last-stage flip-flop has a switch for switching between an input side of a next-stage flip-flop and the signal output terminal. The flip-flop is connected, so by switching the output side of any flip-flop to the signal output terminal, this flip-flop can be selected as the last-stage flip-flop,
As a result, an arbitrary delay amount of the signal can be obtained, and the signal is not input to the flip-flops subsequent to the flip-flop selected as the last stage. Power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional variable delay circuit. FF _{1 to} FF _n ...... Flip-flop (register), SW _{1 to} SW _n
…… Switch, SEL …… Selector.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-253315 (JP, A) JP-A-54-144853 (JP, A) JP-A-58-124325 (JP, A) JP-A-61- 230515 (JP, A)

Claims (1)

(57) [Claims] A flip-flop constituted by a CMOS circuit is arranged in multiple stages, and a signal input to the input side of the first-stage flip-flop is passed through the second-stage and subsequent flip-flops. In the circuit for varying the delay of the signal output from the output side of the selected flip-flop to the signal output terminal, the output side of each flip-flop except the last stage flip-flop has the output side of each flip-flop. A variable delay circuit, wherein a switch for switching connection between the input side of the next-stage flip-flop and the signal output terminal is connected.