JP2748441B2 - Video signal conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion circuit, and more particularly to a video signal conversion circuit capable of converting a signal between three primary color signals and a luminance / color difference signal.

[Conventional technology]

Conventional video signal conversion circuits of this type convert red (R), green (G), and blue (B) three primary color signals to luminance (Y) and two color difference signals (Cb, Cr) to a luminance color difference signal, or It is known as a circuit that converts a luminance (Y) and a luminance color difference signal of two color difference signals (Cb, Cr) into three primary color signals of red (R), green (G), and blue (B).

Such video signal converter circuit, during signal format conversion from RGB three primary color signals to luminance and color difference signals, when the coefficient E ₀ to E _8, Has a circuit configuration capable of realizing the following equation. That is, the input R signal is multiplied by the coefficient E ₀ in the multiplier. This multiplier outputs an output signal (E ₀ × R). Input G signal is multiplied by a coefficient E ₁ in the multiplier. An output signal (E ₁ × G) is output from this multiplier. Further, the input B signal is multiplied by a coefficient E ₂ in a multiplier. The output signal (E ₂ ×
B) is output. Output signals from these multipliers are added by an adder. Thereby, the Y signal is output from the adder.

Input R signal is multiplied by a coefficient E ₃ in the multiplier. An output signal (E ₃ × R) is output from this multiplier. Input G signal is multiplied by a coefficient E ₄ in the multiplier. An output signal (E ₄ × G) is output from this multiplier. Also, B signal input is multiplied by a coefficient E ₅ in multiplier. The output signal (E ₅
× B) is output. The output signals from these multipliers are
It is added by an adder. Thereby, a Cb signal is output from the adder.

Input R signal is multiplied by a coefficient E ₆ in multiplier. The multiplier outputs an output signal (E ₆ × R). Input G signal is multiplied by a coefficient E ₇ in the multiplier. An output signal (E ₇ × G) is output from this multiplier. Further, the input B signal is multiplied by a coefficient E ₅ in multiplier. The output signal (E ₅
× B) is output. The output signals from these multipliers are
It is added by an adder. As a result, a Cr signal is output from the adder.

Also, such a video signal conversion circuit converts the luminance / color difference signal
When signal format conversion to RGB three primary color signals, the coefficients E ₉ to E ₁₇
Then Has a circuit configuration capable of realizing the following equation. That is, the input Y signal is multiplied by a coefficient E ₉ in the multiplier. An output signal (E ₉ × Y) is output from this multiplier. Input Cb signal is multiplied by a coefficient E ₁₀ in multiplier. This multiplier outputs an output signal (E ₁₀ × Cb). Further, the input Cr signal is multiplied by a coefficient E ₁₁ in multiplier. This multiplier outputs an output signal (E ₁₁ × Cr). Output signals from these multipliers are added by an adder. Thereby, from the adder,
An R signal is output.

Input Y signal is multiplied by a coefficient E ₁₂ in multiplier. An output signal (E ₁₂ × Y) is output from this multiplier. The input Cb signal is converted into a coefficient E by a multiplier.
Multiplied by ₁₃ . The output signal (E ₁₃ × C
b) is output. Further, the input Cr signal is multiplied by a coefficient E ₁₄ in multiplier. An output signal (E ₁₄ × Cb) is output from this multiplier. Output signals from these multipliers are added by an adder. As a result, a G signal is output from the adder.

Input Y signal is multiplied by a coefficient E ₁₅ in multiplier. This multiplier outputs an output signal (E ₁₅ × Y). The input Cb signal is converted into a coefficient E by a multiplier.
Multiplied by ₁₆ . The output signal (E ₁₆ × C
b) is output. Further, the input Cr signal is multiplied by a coefficient E ₁₇ in multiplier. An output signal (E ₁₇ × Cr) is output from this multiplier. Output signals from these multipliers are added by an adder. Thereby, the B signal is output from the adder.

The above-described video signal conversion circuit can change the mutual signal format of the three primary color signals and the luminance and color difference signals.

[Problems to be solved by the invention]

However, according to the conventional video signal conversion circuit described above, since a multiplier and an adder are required for each equation, there is a drawback that the circuit scale becomes large.

The present invention has been made to solve the above-described drawbacks, and has as its object to provide a video signal conversion circuit having a reduced circuit scale.

[Means for Solving the Problems] According to the present invention, in a video signal conversion circuit capable of mutually converting a signal format between a three primary color signal and a luminance color difference signal, (a) the three primary color signals are converted into a luminance color difference signal. A conversion instruction output unit for outputting any one of a first instruction for converting to a first color or a second instruction for converting a luminance / color difference signal into a three primary color signal, and (b) a conversion instruction output unit for outputting the first instruction. A first input register unit that individually latches each of the input three primary color signals, and (c) a luminance input while the conversion instruction output unit is outputting the second instruction. A second input register unit for individually latching each of the color difference signals, and (d) individually latching each of the output luminance and color difference signals while the conversion instruction output unit is outputting the first instruction. A first output register section; (E) a second output register unit that individually latches each of the three primary color signals to be output while the conversion instruction output unit is outputting the second instruction; The information indicating whether one of the first instruction and the second instruction is output and the signal values of the input three primary color signals and the input luminance color difference signal are used as address information, and the respective signal values of the input three primary color signals or the input luminance color difference signals are used. Stores multiplied data obtained by multiplying coefficients for the respective conversions, and outputs an instruction from the conversion instruction output unit and a corresponding input three primary color signal or input luminance as a latch output of the first input register unit or the second register unit. A read-only memory for selectively taking in the color difference signal and outputting the multiplied data, (g) an adder for adding the multiplied data from these read-only memories, and (h)
The addition result of the adder is distributed to each signal after conversion, and when the conversion instruction output unit is outputting the first instruction, it is supplied to the corresponding first output register unit, and the second instruction is output. When outputting, the video signal conversion circuit is provided with a data distribution unit that supplies the data to the corresponding second output register unit.

That is, in the present invention, the conversion instruction output unit that outputs one of the first instruction for converting the three primary color signals into the luminance and color difference signals and the second instruction for converting the luminance and color difference signals into the three primary color signals is output. In response to this, the use of some components such as the first input register unit constituting the video signal conversion circuit is switched or the use area of the memory is switched so that the circuit can be shared during conversion. As a result, the circuit scale can be reduced to 1/3 or less of the conventional circuit.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a video signal conversion circuit according to the present invention. FIG. 2 is an explanatory diagram showing storage contents of a read-only memory used in the embodiment.

In FIG. 1, a video signal conversion circuit includes a first input register section 1, a second input register section 2, a read-only memory (ROM section) 3, an adder 4, and a first output register section. 5, a second output register section 6, and a control circuit 7.

The first input register section 1 includes an R input register 11 for latching an R signal from the input terminal Pa, a G input register 12 for latching a G signal from the input terminal Pb, and a B signal from the input terminal Pc. And a B input register 13. The second input register section 2 includes a Y input register 21 for latching a Y signal from the input terminal Qa, a Cb input register 22 for latching a Cb signal from the input terminal Qb, and a Cr from the input terminal Qc.
And a Cr input register 23 for latching signals. The R input register 11 and the Y input register 21 are commonly connected to the a input terminal of the ROM section 3. The G input register 12 and the Cb input register 22 are
It is connected to the b input terminal of the M section 3. B input register 13
And the Cr input register 23 are shared and
Connected to input terminal.

The ROM section 3 is composed of a first ROM 31, a second ROM 32, and a third ROM 33. The first ROM 31 has contents as shown in FIG. 2A, and the second ROM 32 has contents as shown in FIG. The third ROM
Numeral 33 stores contents such as Mc in FIG. 2 (C). In the ROMs 31, 32, and 33, the data for the signal format conversion from the three primary color signals to the luminance chrominance signal is stored for the addresses 0 to n, and the signal format conversion for the luminance chrominance signal is converted to the three primary color signals for the address n + 1 to m Data is stored.
The input of the first ROM 31 is connected to the a input terminal. 2nd ROM
The 32 inputs are connected to the b input. The input of the third ROM 33 is connected to the c input terminal. 1st ROM31, 2nd ROM32,
Each output signal from the third ROM 33 is supplied to the adder 4.

The adder 4 includes two adders 41 and 42. The addition circuit 41 adds the output from the first ROM 31 and the output from the second ROM 32, and can supply the addition result to the addition circuit. The addition circuit 42 is an addition circuit
The addition result from 41 and the output signal from the third ROM 33 are added and can be supplied to the data distribution circuit 71 of the control circuit 7.

The data distribution circuit 71 can supply the output signal from the adding circuit 42 to the first output register section 5 and the second output register section 6 in a time-division manner. This data distribution circuit
The reference numeral 71 includes a first register 71a, a second register 71b, and a third register 71c. These registers 71a ~
Reference numeral 71b designates an output signal from the adder circuit 42, and outputs each output to the first output register 5 and the second output register 5.
Is output to the output register section 6.

The first output register section 5 includes a Y output register 51 for latching a Y signal, and a Cb output register 52 for latching a Cb signal.
And a Cr output register 53 for latching a Cr signal. The output of the Y output register 51 outputs a Y signal via the output terminal Qa, the output of the Cb output register 52 outputs a Cb signal via the output terminal Qb, and the Cr output register 53
Output a Cr signal via the output terminal Qc.

The second output register section 6 includes an R output register 61 for latching an R signal and a G output register 62 for latching a G signal.
And a B output register 63 for latching the B signal. The output of the R output register 61 outputs an R signal through an output terminal Pa, the output of the G output register 62 outputs a G signal through an input terminal Pb, and a B output register 63
Output a B signal through the input terminal Pa.

The control circuit 7 includes an input terminal In in addition to the data distribution circuit 71.
An inverter 72 that takes in the signal format conversion command CTL via the
The clock Ck obtained by multiplying the clock Ck taken from the input terminal Ik
A counter 73 forming a signal Ck / 2 having a cycle of 1/2 of the signal Ck / 4 and a signal Ck / 4 having a cycle of a quarter of the clock Ck, and the signal Ck / 2 and the signal Ck / 2.
A decoder 74 which takes in Ck / 4 and forms a signal Ck ₀ , a signal Ck ₁ , and a signal Ck ₂ . Signal format conversion command
The CTL is supplied to the first input register unit 1 and the first output register unit 5. Inversion signal format conversion command ICTL
Are the second input register section 2 and the second output register section 6
And has been supplied to. The signal Ck / 2 is supplied to the ROM section 3. The signal Ck / 4 is supplied to a first input register unit 1, a second input register unit 2, a first output register unit 5, and a second output register unit 6, , And the ROM section 3. Signal Ck ₀ from the decoder 74 to the register 71a of the data distribution circuit 71, the signal Ck ₁ in the register 71b, the signal Ck ₂ in the register 71c, are to be supplied.

 The operation of the embodiment configured as described above will be described.

FIG. 3 is a time chart for explaining the operation of the embodiment.

<Operation of Converting Signal Format from Three Primary Color Signals to Luminance and Color Difference Signal> The operation of converting the signal format from the three primary color signals to the luminance and color difference signal is as follows. That is, the inversion signal format conversion command
When the ICTL is changed from the high level to the low level, the outputs of the second input register unit 2 and the second output register unit 6 become the high level, and the second input register unit 2 and the second output register unit 6 do not operate. on the other hand,
At this time, the signal format conversion command CTL is inverted by the inverter 72 and changes from a low level to a high level. Thereby, the first input register section 1 and the first output register section 5 become operable.

Then, the input data of R, G, and B input from the input terminals Pa to Pc are input to the R input registers 11 and G of the first input register unit 1 at the rise of the signal Ck / 4 (t _{1 in} FIG. 3). Input register 1
2, latched in the B input register 13. Next, in a third view of the time t ₁ ~t ₂ of the first stage (FS), in order to obtain the Y signal, E from the 1ROM31 of ROM portion _{3 0 × R, E 1 ×} G from the 2ROM32, the The calculation result of E ₂ × B is output from the 3ROM 33. These output signals are added by the adding circuit 41 and the adding circuit 42 of the adder 4, at the leading edge of the signal Ck ₀ (FIG. 3 t
₂ ) The data is latched in the register 71a of the data distribution circuit 71.

In the second stage (SS), to obtain the Cb signal, E ₃ × R from the first ROM 31 and E ₄ × from the second ROM 32 of the ROM unit 3 are used.
G, the calculation result of E ₅ × B is output from the third ROM 33. These output signals are supplied to an adder circuit 41 and an adder circuit 42 of the adder 4.
In are added, rising in (FIG. 3 t ₃₎ of the signal Ck _1, it is latched in the register 71b of the data distribution circuit 71.

In the third stage (TS), in order to obtain the Cr signal, E ₆ × R from the first ROM 31 and E ₇ × from the second ROM 32 of the ROM section 3 are used.
G, the calculation result of E ₈ × B is output from the third ROM 33. These output signals are supplied to an adder circuit 41 and an adder circuit 42 of the adder 4.
In are added, at the rising edge of the signal Ck ₂ (FIG. 3 t _4), is latched in the register 71c of the data distribution circuit 71.

Thus, the register of the data distribution circuit 71 of the control circuit 7
The luminance / color difference signals (Y, Cb, Cr) latched by 71a to 71c are
At the next rising edge of the signal Ck / 4 (t5 in FIG. ₃ ), it is latched by the registers 51 to 53 of the first output register section 5. The luminance / color difference signals (Y, Cb, Cr) latched by the registers 51 to 53 are
Output from output terminals Qa to Qc. As described above, the conversion from the three primary color signals to the luminance and color difference signals is performed in one cycle of the signal Ck / 4.

<Conversion of Signal Format from Luminance / Color Difference Signal to Three Primary Color Signals> First, the inversion signal format conversion command ICTL is changed from a low level to a high level. Thereby, the first input register unit 1
The output of the first output register section 5 becomes high level, and the first output register section 5 does not operate. On the other hand, at this time, the signal format conversion command CTL is inverted by the inverter 72 and changes from a high level to a low level. Thereby, the second input register section 2 and the second output register section 6 become operable.

Then, the input signals of Y, Cb, and Cr input from the input terminals Qa to Qc are input to the Y input registers 21 and Cb of the second input register section 2 at the rise of the signal Ck / 4 (t _{1 in} FIG. 3). Input register 2
2, latched by the Cr input register 23. Next, in a third view of the time t ₁ ~t ₂ of the first stage (FS), in order to obtain the R signal, E ₉ × Y from the 1ROM31 of ROM portion 3, E ₁₀ × Cb from the 2ROM32, the The calculation result of E ₁₁ × Cr is output from 3ROM33. These output signals are added by the adding circuit 41 and the adding circuit 42 of the adder 4, at the leading edge of the signal Ck ₀ (FIG. 3 t
₂ ) The data is latched in the register 71a of the data distribution circuit 71.

In the second stage (SS), to obtain the G signal, E ₁₂ × Y from the first ROM 31 of the ROM section 3 and E ₁₃ from the second ROM 32
× Cb, the calculation result of E ₁₄ × Cr is output from the third ROM 33.
These output signals are added by the adding circuit 41 and the adding circuit 42 of the adder 4, at the leading edge of the signal Ck ₁ (FIG. 3
t ₃ ), latched by the register 71 b of the data distribution circuit 71.

In the third stage (TS), in order to obtain the B signal, E ₁₅ × Y from the first ROM 31 and E ₁₆ from the second ROM 32 of the ROM section 3 are used.
× Cb, the operation result of E ₁₇ × Cr is output from the third ROM 33.
These output signals are added by the adding circuit 41 and the adding circuit 42 of the adder 4, at the leading edge of the signal Ck ₂ (FIG. 3
t ₄ ), latched by the register 71 c of the data distribution circuit 71.

Thus, the register of the data distribution circuit 71 of the control circuit 7
The luminance and chrominance signals (R, G, B) latched by 71a to 71c are latched by the registers 51 to 53 of the first output register section 5 at the rise of the next signal Ck / 4 (t5 in FIG. ₃ ). Is done. register
The luminance / color difference signals (R, G, B) latched by 51 to 53 are output from output terminals Pa to Pc. As described above, the conversion from the luminance / color difference signal to the three primary color signals is performed in one cycle of the signal Ck / 4.

As described above, in the present embodiment, the signal processing is performed in a time-division manner, so that the circuit scale can be reduced to 1/3 or less of the related art.

〔The invention's effect〕

As described above, according to the present invention, a conversion instruction output for outputting any one of the first instruction for converting a three-primary-color signal into a luminance-color-difference signal or the second instruction for converting a luminance-color-difference signal into a three-primary-color signal In response to this, the use of some components such as the first input register unit constituting the video signal conversion circuit is switched or the use area of the memory is switched. Since the circuits in the first and second circuits are greatly shared, the circuit scale of the two conversion circuits can be significantly reduced, and the cost can be reduced and the reliability of the circuits can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the contents of a ROM used in the embodiment, and FIG. 3 is a timing chart showing the operation of the embodiment. 1 first input register section 2 second input register section 3 ROM section 4 adder 5 first output register section 6 second output register Unit 7, control circuit.

Claims (1)

(57) [Claims] A video signal conversion circuit capable of mutually converting a signal format between a three primary color signal and a luminance / chrominance signal, wherein a first instruction for converting the three primary color signals into a luminance / chrominance signal or a luminance / chrominance signal is provided. A conversion instruction output unit that outputs any one of the second instructions for converting the three primary color signals into three primary color signals; and each of the three primary color signals that are input while the conversion instruction output unit is outputting the first instruction. A first input register unit for individually latching, and a second input register unit for individually latching each of input luminance and color difference signals while the conversion instruction output unit is outputting the second instruction. A first output register unit that individually latches each of the output luminance and color difference signals while the conversion instruction output unit is outputting a first instruction; and Give instructions A second output register unit that individually latches each of the three primary color signals to be output, and information indicating whether the conversion instruction output unit is outputting the first instruction or the second instruction. And the signal values of the input three primary color signals and the input luminance color difference signal as address information, and stores multiplication data obtained by multiplying each signal value of the input three primary color signals or the input luminance color difference signal by a coefficient for each conversion, A read-out unit for selectively taking in an instruction from the conversion instruction output unit and a corresponding input three primary color signal or input luminance color difference signal as a latch output of a first input register unit or a second register unit, and outputting the multiplied data; A dedicated memory, an adder for adding the multiplication data from these read-only memories, and distributing the addition result of the adder to each converted signal. In both cases, when the conversion instruction output unit is outputting the first instruction, it is supplied to the corresponding first output register unit, and when it is outputting the second instruction, it is supplied to the corresponding second output register unit. A video signal conversion circuit, comprising: