JP2748472B2 - Frame circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a digital VT for compressing the data amount of a digital image signal and recording it on a magnetic tape by a rotating head.
It relates to a framing circuit applicable to R.

[Summary of the Invention]

According to the present invention, a digital image signal is decomposed into image blocks, and a frame removal process according to a motion for each image block, a variable length encoding process according to a change amount defined by a plurality of pixels included in the image block, and a digital A signal is supplied from an encoding circuit that performs a buffering process of controlling a bit length of a pixel code with a threshold value so that a data amount generated in a predetermined period of an image signal does not exceed a predetermined value. In a framing circuit for generating a continuous output signal, a motion detection flag of an image block, information corresponding to a change amount defined by a plurality of pixels included in the image block, and a predetermined By inserting control data determined for each period at a predetermined position in the sync block, these important data can be strongly protected from errors. It is protected and the image can be restored well.

[Conventional technology]

The present applicant obtains a dynamic range defined by a maximum value and a minimum value of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application No. 59-266407, and this dynamic range A high-efficiency coding apparatus that performs adaptive coding has been proposed. In addition, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 232789, there has been proposed a high-efficiency encoding apparatus that performs encoding adaptive to a dynamic range with respect to a three-dimensional block formed from pixels in an area included in each of a plurality of frames. Furthermore, Japanese Patent Application No. 60-
As described in the specification of Japanese Patent No. 268817, there has been proposed a variable-length encoding method in which the number of bits changes according to a dynamic range so that the maximum distortion generated when performing quantization is constant.

High-efficiency code (AD
RC) is suitable for application to a digital VTR because it can significantly reduce the amount of data to be transmitted. Especially,
The variable length ADRC can increase the compression ratio. However, the variable-length ADRC uses a buffering process when using a fixed-rate transmission path such as a digital VTR that records a predetermined amount of data as one track because the amount of transmission data varies depending on the content of the image. is required.

The applicant of the present application obtains a frequency distribution of a dynamic range, for example, as described in Japanese Patent Application No. 61-257586, converts this frequency distribution into an integral type distribution, and sets a coding threshold value. A buffering device has been proposed which obtains the amount of generated information by applying it to a cumulative frequency distribution and determines a threshold value such that the amount of generated information does not exceed the transmission rate.

Buffering when the bit length of the variable length ADRC pixel code is (0 to 4) will be described. If the threshold for encoding is T1 to T4 (where T1>T2>T3> T4),
For the image block of the dynamic range DR in the range of (maximum value to T1), the bit length is set to 4 and (T1-1 to T1)
The bit length is set to 3 for the image block of the dynamic range DR in the range of 2), and the bit length is set to 2 for the image block of the dynamic range DR in the range of (T2-1 to T3). The bit length is set to 1 for an image block of the dynamic range DR in the range of 1 to T4, and the bit length is set to 0 for the image block of the dynamic range DR of (T4-1 to the minimum value) (the pixel code is transmitted). Is not). A plurality of combinations of these threshold values T1 to T4 are prepared in advance, for example, 32 from the first to the 32nd. When the first set of thresholds is applied, the amount of generated information is maximized. When the 32nd set of thresholds is applied, the amount of generated information is minimized. Threshold sets are set such that the amount of generated information monotonously decreases in order from the third threshold set. Each set of thresholds is distinguished by a 5-bit threshold code.

A distribution table of the frequency of occurrence of the dynamic range DR of a number of image blocks included in two frame periods of the input video data is formed. In this process, the address of the memory (RAM) is set as the dynamic range DR, and the data to be written at each address is set to +1. The frequency distribution table is converted into an integral type by accumulating the frequency of each address of the memory. By applying the above-described set of threshold values to the cumulative frequency distribution table, the amount of generated information can be obtained. A set of thresholds is determined so that the amount of information generated during two frame periods does not exceed the capacity of the transmission path. ADRC encoding is performed using this set of thresholds.

Further, a method of further compressing the information amount by combining the ADRC of a three-dimensional block and the frame dropping process has been proposed by the present applicant (see Japanese Patent Application No. 61-153330). According to this method, when the three-dimensional block is a stationary block, an average value of pixels at corresponding positions in a plurality of regions constituting the three-dimensional block is formed, and the average value is transmitted, so that a pixel of the image block is transmitted. It compresses data by half. A motion detection flag MDT indicating whether or not frame drop processing has been performed is transmitted to the receiving (reproducing) side.

Even in the case of the high-efficiency coding method combining the three-dimensional ADRC and the frame drop processing, the buffering processing is performed. As this type of buffering method, the present applicant has disclosed a method described in Japanese Patent Application No. 62-133924, Japanese Patent Application No. 62-133925, Japanese Patent Application No. 63-183781, etc. Has been proposed. In other words, the above dynamic range
The amount of transmission information is controlled by controlling both the threshold value in the DR level direction and the threshold value for determining whether to drop a frame. The threshold value for determining whether to drop a frame is called a motion threshold value.

As described above, when the output signal generated by the combination of ADRC and buffering is recorded, it is converted by the framing circuit into a form of a recording signal in which sync blocks are continuous. The reproduced signal is supplied to an ADRC decoder via a frame decomposition circuit.

[Problems to be solved by the invention]

As one of the methods for converting the coded output signal of the variable length ADRC having the buffering process and the frame dropping process into transmission data, for example, the coded output signal generated for every four image blocks is stored in a sync block. Can be stuffed in order from the beginning. That is, the motion detection flags MDT (total 1 byte) of the four image blocks are located in the sync block, and the dynamic range DR, the minimum value MIN, and the pixel code (referred to as a bit plane) of each image block are sequentially arranged. The array is located at

Even if the threshold code THR that controls the amount of generated information is reproduced correctly, the MDT of a certain sync block
Alternatively, when an error occurs in the DR, the bit length of the bit plane of the image block after the image block becomes unknown, and the error propagates to the end of the sync block. This error data includes DR, MIN, MDT
Important words such as are included.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a framing circuit that can prevent a propagation error from occurring in an important word.

[Means for solving the problem]

According to the present invention, a digital image signal is decomposed into image blocks, and a frame removal process according to a motion for each image block, a variable length encoding process according to a dynamic range of the image block, and data generated during a predetermined period of the digital image signal. A signal is supplied from an encoding circuit that performs a buffering process that controls a bit length of a pixel code with a threshold value so that an amount does not exceed a predetermined value, and a framing process is performed in which a sync block generates a continuous output signal. In the circuit, a motion detection flag of the image block, dynamic range information, and control data determined every predetermined period are inserted at predetermined positions in the sync block for controlling the amount of generated data.

[Action]

An output signal of an encoder that performs buffering processing, frame drop processing, and variable-length ADRC encoding is converted into a continuous data series of sync blocks. Motion detection flag MDT, dynamic range D at a predetermined position in the sync block
R and the minimum value MIN are inserted. In the frame decomposition circuit, MDT, DR, and MIN inserted in each sync block can be separated. Since these data are inserted into predetermined slots in the sync block, it is possible to prevent a propagation error from occurring. In addition, since the position of the important word is determined, it is easy to encode a special error correction code for the important word. Further, since an error is unlikely to occur in an important word, an error correction of an image block in which an error has occurred in a pixel code can be performed using the important word.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description is made in the following order.

a. Recording circuit and reproducing circuit b. Framing circuit c. Modification a. Recording circuit and reproducing circuit FIG. 1 shows the configuration of a recording circuit and a reproducing circuit of a digital VTR to which the present invention can be applied. , 1
The red (R), green (G), and blue (B) signals of the three primary colors are supplied to the input terminals indicated by. The three primary color signals are converted into digital signals by the A / D converter indicated by 2. The luminance signal (Y) is obtained by the digital matrix circuit shown in FIG.
And color difference signals (U, V) are formed. In the luminance signal and the color difference signal, (Y: U: V) has a sampling frequency of (4: 4: 4).

Since the (4: 4: 4) digital component signal has a large amount of information, it is converted by the rate conversion circuit 4 into a (3: 1: 0) sampling rate and time-division multiplexed signal. That is, the sampling frequency of the luminance signal is (3/4), the sampling frequency of the chrominance signal is (1/4), and the U and V of the chrominance signal are line-sequential signals. The output signal of the rate conversion circuit 4 is
To convert the signals in the order of television scanning into signals in the order of image blocks.

In this embodiment, as shown in FIG. 2, two areas A11 and A12 occupying the same position (4 lines × 4 pixels) in a screen of two consecutive frames constitute one image block, and one image The block includes 32 pixels. Further, in the blocking circuit 5, the blanking period in the input signal is removed, the valid data is made continuous, and a data absence period is formed in the data series. One line contains 858 samples, the valid data of which is 720 samples, and the number of lines in one frame is 525.
Since the number of valid lines is 488, the number of data and the number of valid data in the two-frame period are as follows.

Number of valid data: 720 × 488 × 2 = 702,720 Number of data in two frame periods: 858 × 525 × 2 = 900,720 Blocking circuit 5 is composed of four frame memories, and only valid data of two frame periods is stored in two frame memories. At the same time, the valid data converted into the order of the image blocks is read from the other two-frame memories. By setting the read addresses of the two-frame memory to the order of the image blocks, the order of the scanning lines can be converted to the order of the blocks. Therefore, the output signal 9 of the blocking circuit 5 includes a data absence period of 231H (H: horizontal cycle) as in the following equation.

(900,900-702,720) {858} 231H The output signal of the blocking circuit 5 is supplied to the ADRC encoder 6. The ADRC encoder 6 detects a maximum value MAX and a minimum value MIN for each image block, and a dynamic range DR, which is a difference between the two, and performs variable-length encoding in accordance with the dynamic range DR. Done.
For example, four thresholds T1, T2, T3, T4 (T4 <T3 <T2 <T1)
Is set. When the dynamic range DR of the image block is (0 ≦ DR <T4), the number of allocated bits is set to 0, and only the maximum value MAX and the minimum value MIN of the image block are transmitted. When (T4 ≦ DR <T3), the number of allocated bits is one. When (T3 ≦ DR <T2), the number of allocated bits is 2 bits. When (T2 ≦ DR <T1), the number of allocated bits is 3 bits. (T1 ≦ DR <
In the case of (255), the number of allocated bits is 4 bits. Codes for designating a set of these four thresholds include a luminance signal threshold code YTHR and a chrominance signal threshold code CTHR.

As described above, when encoding the variable length ADRC of 0 to 4 bits, the buffering process is performed so that the information amount in the two frame period does not exceed the predetermined value. The buffering calculates the frequency of occurrence of the dynamic range DR in the two-frame period, determines the optimal thresholds T1 to T4 from the distribution of the frequency of occurrence of the dynamic range DR, and further prepares the dynamic range DR to prepare for the next processing. Consists of a series of processes for clearing the memory in which the frequency is stored. Using the threshold value determined by this buffering, encoding of the variable length ADRC is performed.

The output signal of the blocking circuit 5 is composed of two frames of valid data converted in the order of image blocks. The ADRC encoder 6 collects the frequency of the dynamic range DR during the data valid period, ,
It creates a cumulative frequency distribution table, determines thresholds, and clears memory. Next, variable-length ADRC encoding is performed using a threshold value.

Further, in the case of a still image block, the ADRC encoder 6 forms an average value of two areas A11 and A12 forming one block, and performs a frame drop process of encoding the average value in place of the two areas. You. As a result of the frame dropping process, the information amount of the image data is reduced to half in the case of a still image block. A motion detection flag MDT indicating whether the block is a still image block or a moving image block is formed.

The output signal of the ADRC encoder 6 includes a code signal (referred to as a bit plane BPL) corresponding to each pixel and additional data. The additional data includes a motion detection flag MDT for each image block, a dynamic range DR, a minimum value MIN, threshold values YTHR and CTHR of a luminance signal and a color difference signal, an image block number, a two-frame identification signal DBFR, and the like. It is.
The number of pixels in one block is 16 for a still image and 32 for a moving image. Therefore, the data amount of the bit plane BPL is 0 bytes at the minimum and 16 bytes at the maximum according to the bit length, as shown in FIG.

An output signal of the ADRC encoder 6 is supplied to a framing circuit 7 and converted into data having a frame configuration. The output signal of the framing circuit 7 is supplied to an error correction code parity generation circuit 8, and an error correction code having, for example, a product code configuration is encoded. The output signal of the parity generation circuit 8 is supplied to a digital modulation circuit 9 and undergoes digital modulation processing. Output signal of digital modulation circuit 9 is parallel →
The recording signal of the serial data is supplied to the serial conversion circuit 10 and is output from the parallel-to-serial conversion circuit 10.

This recording signal is generated when the rotating head comes into contact with the magnetic tape,
The data is supplied to a tape transport 11 that performs recording and reproduction, and is recorded on a tape. Also, the reproduction signal reproduced from the tape is converted to a serial-to-parallel conversion circuit via a reproduction amplifier, etc.
The signal is supplied to the digital demodulation circuit 12 to be converted into a parallel signal, which is then supplied to the digital demodulation circuit 13 for digital demodulation. An output signal of the digital demodulation circuit 13 is supplied to a TBC (time axis correction device) 14. The output signal of the TBC 14 is supplied to the error correction circuit 15, and the error is corrected by the error correction code. The error correction circuit 15 generates an error flag indicating the corrected data and the presence or absence of an error.

An output signal of the error correction circuit 15 is supplied to a frame decomposition circuit 16 described later. The bit plane, the additional data, and the error flag are separated by the frame decomposing circuit 16, and the output signal of the frame decomposing circuit 16 is supplied to the ADRC decoder.
Supplied to 17. The ADRC decoder 17 decodes the bit plane using the additional data, and obtains 8-bit restored data corresponding to each pixel. The output signal of the ADRC decoder 17 is supplied to the block decomposition circuit 18.

The block decomposition circuit 18 converts the data of each pixel in the order of the image blocks into a signal in the scanning order of the television signal. The block decomposition circuit 18 generates pixel data as an 8-bit code signal corresponding to each pixel, an error flag indicating whether or not each pixel has an error, and a motion detection code. The motion detection code is a signal indicating a still image block or a moving image block, and is separated from additional data. In the case of a still image block, two regions A11 and A
Instead of 12, a frame drop compression in which the average value of both is encoded is performed.

The output signal of the block decomposition circuit 18 is applied to the smoothing circuit 19
Supplied to In the smoothing circuit 19, interpolation is performed on the still image block which has been dropped and compressed, and one area is used as data of two areas. At the same time, when the still image blocks continue, a smoothing process is performed to prevent the connection of the images between the blocks from becoming unnatural. At the output of the smoothing circuit 19, pixel data and an error flag are generated, and these output signals are supplied to the error correction circuit 20. In the error correction circuit 20, the error data is interpolated by other correct data having a temporal and spatial correlation.

The output signal of the error correction circuit 20 is supplied to the rate conversion circuit 21. The rate conversion circuit 21 converts the (3: 1: 0) time-division multiplexed signal into a (4: 4: 4) component signal. Output signals (luminance signal Y, color difference signals U, V) of the rate conversion circuit 21 are supplied to a digital matrix circuit 22,
It is converted into three primary color signals (R, G, B). The three primary color signals are converted into analog three primary color signals by the D / A converter 23, and are taken out to the output terminal 24.

b. Framing circuit The framing circuit 7 includes a plurality of memory blocks, and each memory block has a so-called double bank configuration including two memories. The output signal of the ADRC encoder 6 is separately written into each memory block,
In addition, by reading data from each memory block in a controlled time slot, a byte data sequence is output from the framing circuit 7.

First, an input signal supplied from the ADRC encoder 6 to the framing circuit 7 will be described. These input signals are supplied in synchronization with the timing signal shown in FIG. In FIG. 4, FRID is a frame ID inverted in a frame cycle, DBFR is a two-frame ID inverted in a two-frame cycle, DTEN is a data enable signal indicating a data valid period, and BLKP is , Block pulses of a block cycle. The two-frame ID has a waveform indicated by a broken line during high-speed playback. One memory bank of each memory block of the framing circuit 7 performs a write operation in two frame periods, and performs a read operation in the next two frame periods. The other memory bank performs a write operation and a read operation in a phase opposite to that of the one memory bank.

YTHR and CTHR: Both of these threshold codes are 1 every 2 frames as a result of buffering of ADRC encoder 6.
This is a 5-bit code in which the values are determined. But ADRC
When output from the encoder 6, it is attached to each image block. The image block of the luminance signal Y is provided with YTHR, and the image block of the color signal C is provided with CTHR.

In the framing circuit, these threshold codes YTHR and CTHR are simply treated as data, but in the block decomposition circuit, in order to restore the BTL (bit length data) of each image block, these threshold codes and dynamic The range DR is used. The reason is that the BTL is not transmitted from the framing circuit to the frame decomposition circuit.

Also, during normal playback, one YTHR and one CTHR fixed for two frames are used to output the BTL of all image blocks in two frames, so that YTHR and CTH
R is a very important code.

YCID: 1-bit flag indicating whether the image block is a Y signal block or a C signal block.

MDT: A 2-bit motion detection flag indicating whether or not the image block has been dropped. When the MDT is (00), it means that the block is a still block and frames have been dropped. When the MDT is (11), it means that the block is a motion block and frames have not been dropped. When subsampling is also used, it is also used as a selection signal for an interpolation filter. Both the framing circuit and the frame disassembling circuit not only handle this flag as data, but also use the flag as an input signal of a control system circuit. Specifically, it is used when obtaining the number of bytes of the effective BPL of each image block.

DR: 8-bit dynamic range data representing the amplitude in the image block. The framing circuit simply handles DR as data, but the frame decomposition circuit uses YTHR and CT to determine the bit length of each image block.
Use in combination with HR.

MIN: 8-bit data indicating the minimum value of the amplitude in the image block.

BPL3 to BPL0: Indicates bit planes, and is an encoded code signal of each pixel. It is input in 4 bits in parallel regardless of whether it is valid or invalid. Effective BPL is determined by MDT and BTL. In FIG. 5 and FIG. 6, the hatched portions are
FIG. 5 shows the BPL of an image block on which frame removal processing has been performed, and FIG. 6 shows the BPL of an image block on which frame removal processing has not been performed.

As shown in FIGS. 5A and 6A, when (BTL = 0), there is no valid bit at all. (4) of the image block
Each pixel of (× 4 × 2 = 32 pixels) has a 4-bit encoded code, BPL3 is a set of the most significant bit (MSB) of the encoded code, and BPL2 is the second bit of the encoded code BPL1 is a set of third bits of the encoded code, BPL0 is a fourth bit of the encoded code,
That is, it is a set of least significant bits (LSBs). The dropped image block is composed of 16 pixels.

In the case of (BTL = 1), as shown in FIGS. 5B and 6B, the effective data is 16 bits and 32 bits, respectively. In the case of (BTL = 2), as shown in FIGS. 5C and 6C, the valid data is 32 bits and 64 bits, respectively.
Is a bit. In the case of (BTL = 3), as shown in FIG. 5B and FIG. 6B, the effective data is 48 bits and 96 bits, respectively. In the case of (BTL = 4), as shown in FIG. 5D and FIG.
Bits and 128 bits.

BTL: Bit length data indicating the number of effective bits per pixel. It is determined for each image block from the dynamic range DR of the image block and the threshold code THR. Take values from 0 to 3.

BKAD: A framing circuit that indicates the serial number of an image block outputs a data byte sequence DT in which a sync block continues with an overhead area left behind so that overhead can be easily added. Data byte sequence DT
Is not only the image effective code (MDT, DR, MIN, effective BPL),
YTHR, CTH added only one per sync block
There are R, DBFR, and BPID. These additional codes are important as auxiliary means for the operation of the frame decomposition circuit. Furthermore, FRID, S
YNP (sync pulse) is output. SYNP is a sync signal of a sync block in the circuit. The output side FRID is
Synchronized with SYNP.

The arrangement of the codes will be described with reference to FIG. Seventh
A two-frame period defined by the timing signal FRID shown in FIG. A includes eight segments as shown in FIG. 7B. One segment includes sync pulse SYNP (7th
(184 + 12 = 196) sync blocks synchronized with FIG. C) are included. The 184 sync blocks are effective sync blocks having an image code area and an additional code area, and the last 12 sync blocks are invalid sync blocks including parity of an error correction code. The length of one sync block is 156 bytes, and 16
The data of the image blocks are inserted.

The first to seventh segments in one cycle of the timing signal FRID each have the data configuration shown in FIG. 7D, and the seventh segment has the data configuration shown in FIG. 7E. The sync blocks are classified into three types, A type, B1 type, and B2 type, according to the data arrangement. The B1 type is the main one. The (4 × 46 = 184) valid sync blocks of the first to seventh segments include five A-type sync blocks located at the beginning and the end, respectively, and 174 B1 sync blocks arranged in the middle. Type sync block. PT0 is the parity of the error correction code for data aligned in the horizontal direction, and PT0
2 is parity for data aligned in the vertical direction. The effective sync block of the eighth segment is
It is composed of an A type sync block located at the beginning and an end, and a B1 type and B2 type sync block arranged in the middle.

FIG. 7F shows a data structure of a B1 type sync block, FIG. 7H shows a data structure of a B2 type sync block, and FIG. 7I shows a data structure of an A type sync block. . The sync block has a sync pattern (SYNC) and an ID at the beginning. The ID is a series of numbers (sync block numbers) assigned to (8 × 196 = 1568) sync blocks included in two frame periods.
It is. Also, the leading part of the sync block after the ID is shown in an enlarged manner in FIG. 7G.

The principle of the code arrangement of the sync block will be described.
In the sync block, a portion excluding an overhead portion to which parity of an error correction code is added is divided into an image code region and an additional code region. The image code area includes MDT, DR, MIN, and BPL, and the additional code area includes DBF
R, YTHR, CTHR, BPID are included. The additional code area is located near the beginning of the sync block regardless of the type difference,
It has the configuration shown in FIG. 7G.

Among the outputs of the ADRC encoder, MDT, DR, and MIN are placed at predetermined positions in the image code area as important words. As shown in FIGS. 7F and 7G, DRs and MINs of the four image blocks are located after the MDT (1 byte in total) of the four image blocks. These MDT, DR, MI
N is located at 3 byte intervals. One effective sync block includes MDT, DR, and MIN of a total of 16 image blocks. Another important term is the additional code YT
There are HR, CTHR, BPID. Parity is specially added to these important words to reduce the effects of errors. PT1 is the parity of the error correction code for the important word.

The bit plane BPL is located in the other part of the image code area except the part occupied by the important word.

A valid BP is used for the image code area that is not
L is sequentially packed over two frames.

In FIG. 7G, BPID is the ID signal of the first BPL of the sync block. The 15-bit BPID1 is
Indicates the number of the image block in the two frames to which the
ID2 indicates a number (sub-block number) assigned to each byte in the image block. First 1 of additional code area
The byte is BA1, and the second, third, fourth
The second respective byte is BA2, BA3, BA4. The data structure of this additional code area is A type, B1 type,
Same between B2 types. The A type effective sync block does not include MDT, DR, MIN as shown in FIG. 7I, and the B1 type sync block includes MDT, DR, MIN as shown in FIG. 7F. included. By adjusting the number of these two types of valid sync blocks, useless MDT, DR, and MIN slots in which valid codes cannot be entered are reduced. In addition, MDT,
B2 type with partial DR and MIN slots (Fig. 7H
Useless sync block)
It is easy to completely eliminate T, DR, and MIN.

The framing circuit 7 is dedicated to the motion detection flag MDT, the dynamic range DR, the minimum value MIN, the bit length code BTL, the bit plane BPL, the identification code BPID indicating the block number, and the frame DBFR inverted every two frame periods. Memory blocks are provided. Further, a register to which the threshold code THR is supplied is provided. The above-mentioned codes from the ADRC encoder 6 are written to these memory blocks, and as shown in FIG. 7, each code is read from the memory block so that each code is located in a predetermined time slot. Is read.

c. Modified Example In the above embodiment, the number of the first image block in the sync block is inserted as the identification code BPID in order to refresh the propagation error of the pixel code in the frame decomposition circuit. However, the address when writing the pixel code BPL generated in the two-frame period into the memory of the framing circuit may be continuous, and the BPID may not be inserted.

Although the dynamic range DR and the minimum value MIN are transmitted as the information of the dynamic range, any two of the dynamic range DR, the minimum value MIN, and the maximum value MAX may be transmitted.

Furthermore, the buffering method used in combination with the process of controlling the amount of generated information by changing the threshold value for distinguishing whether the image block is a still block or a moving block and the above-described control using the threshold value THR is also used. The present invention is applicable.

〔The invention's effect〕

According to the present invention, the motion detection flag MDT, the dynamic range DR, and the minimum value MIN are inserted at predetermined positions (time slots) of each sync block. It can be prevented from occurring. Also, it is easy to add dedicated parity to these important words in order to enhance protection against important word errors. Furthermore, since a propagation error does not occur in an important word, there is an advantage that it is possible to use an important word to perform error correction of an image block in which a pixel code is in error.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a recording / reproducing circuit to which the present invention can be applied, FIGS. 2 and 3 are schematic diagrams used for describing image blocks and bit planes, and FIG. 4 is supplied to a framing circuit. FIGS. 5 and 6 are schematic diagrams showing a bit plane in detail, and FIG. 7 is a schematic diagram used for explaining an output signal of the framing circuit. Explanation of main reference numerals in the drawings 6: ADRC encoder, 7: framing circuit, 17: ADRC decoder.

Claims (1)

(57) [Claims] A digital image signal is decomposed into image blocks, and a frame removal process according to a motion is performed for each of the image blocks, and a variable length coding according to a change amount defined by a plurality of pixels included in the image block. A signal is supplied from an encoding circuit that performs a process and a buffering process of controlling the bit length of the pixel code with a threshold value so that the data amount of the digital image signal generated during a predetermined period does not exceed a predetermined value. In a framing circuit for generating an output signal in which sync blocks continue, a control data determined every predetermined period for controlling the motion detection flag of the image block, the change amount information, and the generated data amount. Is inserted at a predetermined position in the sync block.