JP2749749B2 - Logic circuit delay verification method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of verifying a delay of a logic circuit, and more particularly to a method of verifying a delay of a logic circuit for automatically verifying a delay time of wiring actually formed on the logic circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a procedure for verifying a delay value of a logic circuit. The procedure will be described with reference to FIG.

When a logic circuit is designed, a designer creates a circuit diagram (step 1), simulates the tentative wiring diagram (hereinafter referred to as a tentative layout), and performs operation verification (hereinafter a tentative simulation). (Step 2). If the expected wiring delay time cannot be obtained at this point, the wiring is re-created or the design is started again (step 3). When the operation verification is normally completed, the result of the temporary simulation is stored as the expected delay time 9. Next, a logic circuit is actually created (step 4), and a simulation is also performed on the created logic circuit (hereinafter, referred to as an actual layout) (hereinafter, referred to as an actual simulation) (step 5).

The delay time of the logic circuit is verified by comparing the actual delay time value 10 obtained by the actual simulation (step 5) with the expected delay time value 9 obtained by the provisional simulation (step 2) (step 5). 6). As a result of the comparison, if they do not match, the temporary layout or the actual layout is redone in consideration of the result of the verification (step 5). As a result of the comparison / verification (step 6), if the expected result is obtained, the operation verification of the logic circuit is completed, and the logic circuit is eventually manufactured (step 8).

Conventionally, in the process of the actual simulation (step 5), since the designer of the logic circuit has created a circuit diagram by himself, he is familiar with the operation, detailed contents, etc. of each function constituting the logic circuit. doing. Therefore, even if a failure occurs during operation verification, the designer can easily estimate the location of the cause in the logic circuit from the phenomenon of the failure, the expected delay time 9, the actual delay time 10, and the like. did it. Then, the input / output values around the approximated location were verified, and the location of the failure was identified by narrowing down the location of the failure.

However, recently, instead of creating a circuit diagram by a designer himself, a designer has automatically created a logic circuit diagram using a CAD system equipped with a logic synthesis tool. This logic synthesis tool is a software tool executed on a CAD system. The designer describes a language for creating a circuit diagram and inputs the language into the logic synthesis tool to automatically create schematic information. Then, operation verification is performed on the created logic circuit.

The use of such a logic synthesis tool makes it possible to quickly lay out a logic circuit even when the logic circuit becomes sophisticated and complicated.

[0008]

However, by causing the logic synthesis tool to automatically create a logic circuit diagram, if any trouble occurs during the actual simulation, the designer can create the logic circuit created by the logic synthesis tool. Analyze,
After recognizing the logic circuit, it is necessary to detect the location where the failure has occurred. In other words, a logic circuit can be created easily and quickly by using a logic synthesis tool, but if a problem occurs, it becomes necessary to analyze the logic circuit, and instead, it is necessary to remove the problem. There is a problem that extra work and time are required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a logic circuit in which a failure due to a wiring delay time during an actual simulation does not require a thorough knowledge of the logic circuit. Another object of the present invention is to provide a method for verifying the delay of a logic circuit, which can automatically estimate the defective portion.

[0010]

In order to achieve the above object, a method of verifying a delay of a logic circuit according to the present invention comprises a logic circuit for verifying a location of a failure caused by a delay occurring on an actual layout of a logic circuit. In the circuit delay verification method, an expected value extraction step of storing an expected value, which is a predetermined delay time of a wiring between elements, as a part of delay information of an element having an output terminal connected to the wiring. And storing the actual delay time value of the wiring between the respective elements obtained by the simulation on the actual layout of the logic circuit as a part of the delay information of the element having the output terminal connected to the wiring. Delay value extracting step, starting from a delay generating element that does not output a desired logical value after a predetermined time elapses with respect to an input value to the logic circuit, For all the delay factor elements disposed on the upstream side, a back trace is performed using the expected value and the actual delay time value of the delay factor element, and the logical value of each of the delay factor elements is calculated. A logic value calculation step, and a mismatch detection for comparing the respective logic values calculated in the logic value calculation step in the delay factor element and detecting the delay factor element having the delay information in which the comparison result is mismatched And step.

According to the present invention, the above steps are performed,
In particular, the mismatch detection step is repeatedly performed upstream until a delay factor element that does not cause a mismatch is detected.
With this, it is possible to provide an indication that there is a portion that causes a problem due to a delay on the wiring connected to the output terminal of the delay factor element that does not match.

[0012]

According to the logic circuit delay verification method of the present invention having the above-described configuration, the expected value which is the predetermined delay time of the wiring between the elements is set to the output terminal connected to the wiring. Is stored as a part of the delay information on the element side having

An actual delay time value of a wiring between each element obtained by a simulation using a logic circuit actually wired is stored as a part of delay information of an element having an output terminal connected to the wiring. I do.

If there is a delay generating element which does not output a desired logical value after a lapse of a predetermined time with respect to the input value to the actually wired logic circuit, an upstream delay starting from the delay generating element is used. Extract all the factor elements. A back trace is performed on the extracted delay factor element using the expected value and the actual delay time value, which are delay information of each delay factor element, and the logical value of each delay factor element is calculated.

The calculated logical values are compared with each other, and a delay factor element having delay information that makes the comparison result inconsistent is detected. This processing is sequentially performed in the upstream direction until a delay factor element having delay information having a matching comparison result is detected.

Thus, it is possible to provide an indication that there is a location where a defect due to a delay exists on the wiring of the logic circuit in which the comparison result does not match.

[0017]

Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a part of a logic circuit for explaining this embodiment. FIG. 2 shows a table for storing delay information used when detecting a delay point of the wiring in the logic circuit shown in FIG. 1. Each table shows the connection relation of the wiring of the logic circuit in FIG. Correspondingly tied.

The feature of the present invention is that, in the logic circuit of FIG. 1, a delay time (hereinafter referred to as an expected value) of a wiring obtained as a result of a tentative simulation using a tentative layout and an actual layout are used. By using the delay time of the wiring obtained as a result of the actual simulation (hereinafter, referred to as a real-time delay value) and comparing the logical values at a predetermined time, a failure point due to the delay of the logical circuit is estimated. That is.

Hereinafter, a procedure for estimating the location of a problem caused by a delay will be described with reference to FIGS.

First, a tentative simulation is performed in the tentative layout of the logic circuit shown in FIG. On the left side of FIG. 3, a time chart when a tentative simulation is performed is shown. In this embodiment, the results of the tentative simulation are used as expected values, and the tables 63 and 6 shown in FIG.
5,..., 73. Tables 63, 65, ...
, 73 are provided corresponding to the respective elements 13, 15, ..., 23. In FIG. 2, each table 63,
, 73 are connected using arrow lines. The obtained expected value is an expected value in each wiring. In this embodiment, the expected value is stored as delay information of an element having an output terminal connected to a certain wiring in a table corresponding to the element. Therefore, in this embodiment, as shown in FIGS. 1 and 2, 5 ps, which is the expected value of the wiring 43,
And 10 ps, which is the expected value of the wiring 45, is stored in the table 65 of the element 15.
The expected values, 10 ps, 5 ps, 10 ps, 10
ps is stored. In this embodiment, out
Since the terminal 11 and the input terminal (not shown) are also required for connecting the above tables, they are considered as one element.

Second, an actual simulation is performed in an actual layout. On the right side of FIG. 3, a time chart when an actual simulation is performed is shown. The actual delay time value as a result of the actual simulation is stored in each of the tables 63, 65,..., 73 shown in FIG. The actual delay time value 5p of each of the elements 13, 15,.
s, 25ps, 5ps, 5ps, 15ps, 10ps
Is a predetermined table 63 in the same manner as the above-mentioned expected value,
65,..., 73.

Inputting a predetermined input pattern from the input terminal (not shown) of the logic circuit of FIG. 1 to the logic circuit of FIG. 1 in which the expected value and the actual delay time value are obtained as described above. The operation is verified.

Hereinafter, in the logic circuit of FIG.
The procedure when sampling the logical value of the out terminal 11 at 00 ps will be described with reference to the time chart of FIG. In the present embodiment, the delay time of the element itself is substantially the same in both the tentative simulation and the actual simulation, and thus is omitted from the calculation of the delay time.

According to FIG. 3, at the input terminal 11b of the out terminal 11, which is the most downstream of the logic circuit of FIG.
Logical value 111 by provisional simulation at ps
Is 1, and the logical value 211 in the actual simulation is 0. That is, even if the transition of the output between the tentative simulation and the actual simulation is the same, a logical value that does not match is output at the predetermined time of 100 ps. Therefore, in the present embodiment, the out terminal 11 is regarded as a delay generation element, and the back trace, which will be described later, is performed with respect to the delay factor element disposed on the upstream side from the out terminal 11 as a starting point. It will be a guide to the location.

Here, if the logic value of the expected value at the input terminal 11b matches the logical value of the actual delay time value for a certain input pattern, it is determined that the logic circuit of FIG. You. Note that the element 13 and the element 1
No search is made for a delay generating element which is a starting point in the order of 5 and upstream.

Starting from the out terminal 11, first,
The waveform of the output terminal 13a immediately upstream of the out terminal 11 among the delay factor elements is examined. As shown in Table 63, the expected value at the time of the tentative simulation is 5 ps, and thus the waveform at the output terminal 13a is a waveform obtained by advancing the waveform at the input terminal 11b by 5 ps. Then, as the logical value 113 of the output terminal 13a, the logical value at the time of 5 ps before 100 ps, that is, at the time of 95 ps is output,
Its value is 1. Similarly, since the actual delay time value in the actual simulation is also 5 ps, the waveform of the output terminal 13a is
The waveform at the input terminal 11b is advanced by 5ps. As the logical value 213 of the output terminal 13a, the logical value at the time of 5 ps before 100 ps, that is, at the time of 95 ps is output, and the value is 0. Therefore, the result of the provisional simulation and the result of the actual simulation do not match, and it is determined that the wiring 43 may be a defective portion, and the defect information (Bad) is stored in the table 63 as the determination information.

Next, the waveforms of the output terminals 15a and 17a of the elements 15 and 17 which determine the waveform of the output terminal 13a are examined. First, in the element 15, the table 65
As shown in the figure, the expected value at the time of the provisional simulation is 1
0 ps, the waveform at the output terminal 15 a
The waveform of b is advanced by 10 ps. Output terminal 15
The logical value 115 of a is 10 ps before 95 ps,
That is, the logical value at the time of 85 ps is output, and the value is 1. Similarly, since the actual delay time value in the actual simulation is 25 ps, the waveform at the output terminal 15a is a waveform obtained by advancing the waveform at the input terminal 13b by 25 ps. As the logical value 215 of the output terminal 15a, the logical value at the time of 25 ps before 95 ps, that is, at the time of 70 ps is output, and its value is 0. Therefore, since the results of the provisional simulation and the actual simulation do not match, it is determined that the wiring 45 may be a defective portion, and the defect information (Bad) is stored in the table 65 as the determination information.

In the element 17, when it is obtained in the same manner as described above, the logical value 117 of the output terminal 17a at the time of the tentative simulation is a value 10 ps before 95 ps, that is, the logical value at the time of 85 ps is output. And its value is 1. The logical value 217 of the output terminal 17a during the actual simulation is 95 ps.
The logical value at the time of 5 ps before, that is, at the time of 90 ps is output, and the value is 1. Therefore, the result of the provisional simulation and the result of the actual simulation match, so that it is determined that the wiring 47 is not a defective portion, and the normal information (Good) is stored in the table 67 as the determination information.

As described above, when the comparison results match, it is determined that the logic circuit upstream of the wiring 47 in which no fault has occurred has no fault due to the delay. Are not compared.

By repeatedly performing the above processing, the logical values and determination information shown in FIGS. 2 and 3 can be obtained. This process is repeatedly performed on the wiring connected upstream from the wiring determined to be defective until a wiring determined to be free of defects appears. In this embodiment, FIG.
According to the determination information, it can be determined that there is a cause of a failure due to delay on the wiring including the wiring connecting the elements 13, 15, and 19 and until the wiring is determined to be normal information.

As described above, according to the present embodiment, the expected value and the real time delay value of the wiring between the elements are obtained, and the back tracing is performed for the predetermined time from the elements whose logical values do not match. , A process of comparing logical values. And
Tables 63, 64,..., 7 for storing the results
3. Further, by outputting the values of the table following it to a monitor or the like, it is possible to know at a glance a place where there is a possibility of a failure due to a delay, and to give an indication of the place of the failure.

[0033]

As described above, according to the delay verification method of the present invention, the back trace is performed by using the expected value of the delay time between the elements and the delay time value on the actual wiring. Thus, it becomes possible to automatically provide an indication of the location of the defect due to the delay.

Therefore, even if the designer is not familiar with the logic circuit, it is possible to give an indication of a defective portion, and it is possible to efficiently verify the logic circuit.

Further, it is possible to reduce the time required for manufacturing the logic circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a logic circuit for explaining a delay verification method according to the present invention.

FIG. 2 is a diagram showing a table for storing delay information corresponding to the logic circuit of FIG. 1;

FIG. 3 is a time chart of elements included in the logic circuit of FIG. 1;

FIG. 4 is a flowchart illustrating a procedure for verifying a delay value of a logic circuit.

[Explanation of symbols]

 11 out terminal 13, 15, 17, 19, 21, 23 element 63, 65, 67, 69, 71, 73 Table

Claims (1)

(57) [Claims] 1. A delay verification method for a logic circuit for verifying a location of a failure caused by a delay occurring on an actual layout of a logic circuit, comprising the steps of: An expected value extracting step of storing as a part of delay information of an element having an output terminal connected to a wiring; and an actual delay time value of a wiring between the respective elements obtained by a simulation on a real layout of the logic circuit. Actual delay value extraction step of storing as a part of delay information of the element side having an output terminal connected to the wiring, a desired logic value after a predetermined time elapses with respect to the input value to the logic circuit Starting from the delay generating element that does not output, the expected value of the delay factor element and the actual delay time are determined for all the delay factor elements disposed upstream of the delay generating element. Performing a backtrace using each of the inter-values, and calculating a logical value of each of the delay factor elements; and comparing the respective logical values calculated by the logical value calculation step in the delay factor element. A mismatch detecting step of detecting the delay factor element having the delay information having a mismatched comparison result.