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JP2749966B2 - Printed circuit board structure - Google Patents
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JP2749966B2 - Printed circuit board structure - Google Patents

Printed circuit board structure

Info

Publication number
JP2749966B2
JP2749966B2 JP2171114A JP17111490A JP2749966B2 JP 2749966 B2 JP2749966 B2 JP 2749966B2 JP 2171114 A JP2171114 A JP 2171114A JP 17111490 A JP17111490 A JP 17111490A JP 2749966 B2 JP2749966 B2 JP 2749966B2
Authority
JP
Japan
Prior art keywords
printed circuit
circuit board
connection
patterns
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2171114A
Other languages
Japanese (ja)
Other versions
JPH0458584A (en
Inventor
淳 寺島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2171114A priority Critical patent/JP2749966B2/en
Publication of JPH0458584A publication Critical patent/JPH0458584A/en
Application granted granted Critical
Publication of JP2749966B2 publication Critical patent/JP2749966B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • H05K3/363Assembling flexible printed circuits with other printed circuits by soldering

Landscapes

  • Combinations Of Printed Boards (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は少なくとも2板のプリント基板を接続するプ
リント基板構造に関する。
Description: TECHNICAL FIELD The present invention relates to a printed board structure for connecting at least two printed boards.

[従来の技術] 従来の基板同士の接続の代表的な例を第3図乃至第6
図に示す。従来基板同士を半田付により、電気的に接続
する場合、例えば上側に配置される基板が、フレキシブ
ルプリント基板である場合、第6図に示す如く、半田付
に要する部分、即ちパターンの露出部分1fを爪形状(構
造については後述)に外形加工しているものが知られて
いる。しかし、この構造は、半田付性が良い反面、半田
ごて等の外力による爪部1fの損傷、切断等による断線が
発生していた。この様な断線の危険性の少ない構造とし
て、第3図乃至第5図に示される基板の構造が知られて
いる。同図で示される基板の構造を説明する。1はフレ
キシブルプリント板(以下FPCと呼ぶ)であり、基板3
の上側に配置され半田付される。FPC1は、ポリイミド材
から成るペース1a上に銅箔パターン1bが配置されてお
り、パターンの上面は、カバーフィルムあるいはレジス
トインク等の絶縁材1cで被覆されており、その先端部分
は、接続のため露出している。銅箔パターン1bの露出部
先端は、半田材料が載り易くなるように半円形の開口部
1hを有している。3は、FPC1に対して下側に配置される
基板である。基板3は、ベース材3a(材質は、ガラスエ
ポキシ等の硬質、あるいはポリイミド材のような可撓性
を有するもののいずれでもよい。)上に、半田付接続用
のパターン3bが、FPC1上のパターン1bと同ピッチ4で配
置されており、該パターン3bの上面は、カバーフィルム
あるいはレジストインク等の絶縁材3c,3c′で被覆され
ており3cと3c′のすき間は、接続用のパターン3bが露出
している。
[Prior Art] FIGS. 3 to 6 show typical examples of conventional connection between substrates.
Shown in the figure. In the case where conventional substrates are electrically connected to each other by soldering, for example, when the substrate disposed on the upper side is a flexible printed circuit board, as shown in FIG. 6, a portion required for soldering, that is, an exposed portion 1f of the pattern Is known in which the outer shape is processed into a nail shape (the structure will be described later). However, while this structure has good solderability, the nail 1f is damaged by an external force of a soldering iron or the like, and breakage is caused by cutting or the like. The structure of the substrate shown in FIGS. 3 to 5 is known as a structure having a low risk of disconnection. The structure of the substrate shown in FIG. Reference numeral 1 denotes a flexible printed board (hereinafter referred to as FPC),
And soldered. In the FPC 1, a copper foil pattern 1b is arranged on a pace 1a made of a polyimide material, and the upper surface of the pattern is covered with an insulating material 1c such as a cover film or a resist ink, and a tip portion thereof is connected for connection. It is exposed. The tip of the exposed part of the copper foil pattern 1b has a semicircular opening so that the solder material can be easily placed on it.
Has 1h. Reference numeral 3 denotes a substrate disposed below the FPC 1. The substrate 3 has a base material 3a (made of a hard material such as glass epoxy or a flexible material such as a polyimide material) on a base material 3a, and a pattern 3b for connection by soldering and a pattern on the FPC1. 1b are arranged at the same pitch 4 and the upper surface of the pattern 3b is covered with an insulating material 3c, 3c 'such as a cover film or a resist ink, and a connection pattern 3b is provided between the gaps 3c and 3c'. It is exposed.

そこで、FPC1と基板3を半田付接続する場合、FPC1の
外形部端部が、図中2点鎖線で示すl1の位置に合うよう
に重ね合わされる。
Therefore, when connecting soldering the FPC1 and substrate 3, the outer portion end of FPC1 are superimposed to match the position of the l 1 indicated by the two-dot chain line in FIG.

ここで基板3の絶縁材3cの先端部は通常FPC1の外形端
部が、基板3に位置する位置l1から所定間隔dだけ内側
に後退した位置l2に設けられている。これは、基板同士
のずれによってl2がl1より前方へ突出してしまう銅箔パ
ターン1bとパターン3bとの間に、銅箔パターンのつなが
らない部分を生じてしまうため半田付性が悪くなってし
まうからである。
Wherein the distal end portion of the insulating material 3c of the substrate 3 is outer end portion of the normal FPC1 are provided from the position l 1 located on the substrate 3 at positions l 2 which is recessed inward by a predetermined distance d. This causes a portion where the copper foil pattern is not connected between the copper foil pattern 1b and the pattern 3b in which l 2 protrudes forward from l 1 due to displacement between the substrates, so that solderability is deteriorated. Because.

実際の半田接続は、第5図にて示されるように、パタ
ーン露出部1bとパターン3bにまたがるように半田材4が
盛られ接続が完了する。
In the actual solder connection, as shown in FIG. 5, the solder material 4 is laid over the pattern exposed portion 1b and the pattern 3b, and the connection is completed.

[発明が解決しようとしている課題] しかしながら、電気的な回路規模の増大に伴ない、基
板同士の接続が増加してしまうと、限られた面積の中
で、高密度の接続が必要となり必然的に、挟ピッチでの
多数の信号ラインの接続が要求される。この要求に対応
して、接続パターンピッチを狭くすればする程、パター
ン同士のリークが頻発するのである。
[Problems to be Solved by the Invention] However, if the connection between the substrates increases with the increase in the electric circuit scale, a high-density connection is required in a limited area. In addition, connection of a large number of signal lines at a narrow pitch is required. In response to this demand, the narrower the connection pattern pitch, the more frequently patterns leak.

リークのメカニズムは、(1)パターン同士が近接し
たために起こる、単純な半田ブリッジによるものの他に
(2)第4図、第5図に示す様に、基板3のベース3a、
絶縁材3cの先端部側面3eと、FPC1のベース1aとの間に微
少間隔Bが生じてしまい、融解した半田が、間隔Bを側
面3eに沿って、毛管現象の如く伝わり隣接するパターン
に達してしまうのである。即ち、このようにしてリーク
が発生するものである。
The mechanism of the leak is (1) in addition to a simple solder bridge that occurs due to the proximity of the patterns, (2) as shown in FIGS. 4 and 5, the base 3a of the substrate 3,
A minute space B is generated between the tip side surface 3e of the insulating material 3c and the base 1a of the FPC 1, and the melted solder reaches the adjacent pattern along the space B along the side surface 3e like a capillary phenomenon. It will be. That is, a leak is generated in this manner.

(1)に対しては、塗布する半田量をコントロールす
ることで比較的容易にブリッジを防ぐことができるが、
(2)の現象については、外観ではチェックができず、
またいつも同じ条件で発生するとは限らないため、その
対策に苦慮していたのが現状である。
For (1), the bridge can be prevented relatively easily by controlling the amount of solder to be applied.
Regarding the phenomenon (2), the appearance cannot be checked.
In addition, since it does not always occur under the same conditions, it is difficult to take countermeasures at present.

[課題を解決するための手段] 本発明は接続する2板のプリント基板のうちの一方の
プリント基板に複数の接続パターンを露出させたプリン
ト基板構造において、複数の接続パターンの端部の絶縁
被覆層を段差状に形成し、該パターンの間に入り込むよ
うにしたことにより、リークの原因となる上記微少間隔
Bを無くし、半田等の接着物質の流れ込みを防止したこ
とを特徴とする。
Means for Solving the Problems According to the present invention, in a printed circuit board structure in which a plurality of connection patterns are exposed on one of two printed circuit boards to be connected, an insulating coating of an end portion of the plurality of connection patterns is provided. By forming the layer in a stepped shape and penetrating between the patterns, the minute spacing B causing a leak is eliminated, and the flow of an adhesive substance such as solder is prevented.

[実施例] 第1図及び第2図は本発明の実施例を示すものであ
る。
Embodiment FIG. 1 and FIG. 2 show an embodiment of the present invention.

同図において、FPC1の構造については従来実施例(第
3図)と差異はないため、ここでの説明は省略する。
In the figure, the structure of the FPC 1 is not different from that of the conventional embodiment (FIG. 3), and the description is omitted here.

2はFPC1に対してその下側に配置されるプリント基板
である。
Reference numeral 2 denotes a printed circuit board disposed below the FPC 1.

プリント基板2はベース材2a(材質はガラスエポキシ
等の硬質あるいはポリイミド材のような可撓性を有する
もののいずれでもよい)上に、接着用パターン2bがFPC1
上の接続用パターン1bと同ピッチで配置されており、そ
の上面がカバーフィルムあるいはレジストインク等の絶
縁材2c,2c′で被覆されており、その間隙は接続パター
ン露出部分である。
The printed circuit board 2 is formed on a base material 2a (the material may be any of a hard material such as glass epoxy or a flexible material such as a polyimide material).
They are arranged at the same pitch as the connection pattern 1b above, and the upper surface is covered with insulating materials 2c and 2c 'such as a cover film or resist ink, and the gap is an exposed portion of the connection pattern.

ここで、絶縁材2cの端部の形状は、隣接する接続パタ
ーン2bの間隙の領域において、FPC1の外形端部をプリン
ト基板2に合わせる位置l1よりもDだけ突出させた位置
l2まで延長させている。また、接続パターン2b上の領域
においては、前記位置l1よりも“d"だけ内側の位置l3
で退避させた形状としている。
Here, the shape of the end of the insulating material 2c is a position where the outer end of the FPC 1 is protruded by D from the position l1 where the outer end of the FPC 1 is aligned with the printed circuit board 2 in the gap region between the adjacent connection patterns 2b.
l has been extended to 2 . The connection in the region of the patterns 2b, and then to the position l 1 than "d" is retracted only to the inside of the position l 3 shape.

従ってプリント基板2の絶縁材2cの外形形状は前記接
続パターン1b及び2bの配列ピッチと等ピッチを有する波
形の段差形状をなしている。
Therefore, the outer shape of the insulating material 2c of the printed circuit board 2 has a stepped shape of a waveform having the same pitch as the arrangement pitch of the connection patterns 1b and 2b.

次に、ここで説明したプリント基板2とFPC1を重ね合
わせて半田接続を行なうわけだか、FPC1とプリント基板
2を重ね合せた時に前述のような微少間隔Bは生じな
い。なぜなら、この間隔Bはプリント基板2の絶縁材に
より充填されているからである。従って間隙Bを半田材
が伝わって生じるリーク現象は起こらない。
Next, the printed circuit board 2 and the FPC 1 described above are superimposed to perform the solder connection. When the FPC 1 and the printed circuit board 2 are superimposed, the minute interval B does not occur. This is because the space B is filled with the insulating material of the printed circuit board 2. Therefore, the leak phenomenon that occurs when the solder material is transmitted through the gap B does not occur.

また、FPC1の先端部に対して“D"だけ突出した基板2
上の絶縁材2cが隣接する接続パターン同士の間に介在す
るため半田ブリッジも同時に防ぐことができる。
Also, the substrate 2 protruding by “D” from the tip of the FPC1
Since the upper insulating material 2c is interposed between adjacent connection patterns, solder bridges can be prevented at the same time.

[発明の効果] 一方のプリント基板と他方のプリント基板が重ね合わ
された時に各接続パターン間に微少間隔Bを生じさせな
い構造になっているため、半田材が間隙Bを伝わること
によって生じるリーク現象は起こらない。また同時に絶
縁材が隣接する接続パターン同士の間に介在し単純な半
田ブリッジも防止できるため狭ピッチで、多数の接続が
可能である。
[Effects of the Invention] Since the structure is such that a minute space B is not generated between each connection pattern when one printed circuit board and the other printed circuit board are superimposed, a leak phenomenon caused by the transmission of the solder material through the gap B is prevented. Does not happen. At the same time, since an insulating material is interposed between adjacent connection patterns and a simple solder bridge can be prevented, a large number of connections can be made at a narrow pitch.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明による2つのプリント基板の斜視図、 第2図は、第1図の上面図、 第3図は、従来例を示すプリント基板の斜視図、 第4図は第3図の上面図、 第5図は第4図のA−A断面図、 第6図はその他の従来例を示すプリント基板の斜視図、 1……フレキシブルプリント基板、2……プリント基
板、1b・2b……接続パターン、2c・2c′……絶縁材。
FIG. 1 is a perspective view of two printed boards according to the present invention, FIG. 2 is a top view of FIG. 1, FIG. 3 is a perspective view of a printed board showing a conventional example, and FIG. Top view, FIG. 5 is a sectional view taken along line AA of FIG. 4, FIG. 6 is a perspective view of a printed circuit board showing another conventional example, 1... Flexible printed circuit board, 2. … Connection pattern, 2c ・ 2c ′ …… Insulation material.

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】少なくとも2枚のプリント基板の複数のパ
ターン同士を接続する為に、一方のプリント基板に複数
の接続パターンを露出したプリント基板構造において、 前記複数の接続パターンの端部の絶縁被覆層を段差状に
形成し、該複数の接続パターンの間に該絶縁被覆層を入
り込ませたことを特徴とするプリント基板構造。
1. A printed circuit board structure in which a plurality of connection patterns are exposed on one printed circuit board in order to connect a plurality of patterns on at least two printed circuit boards. A printed circuit board structure, wherein a layer is formed in a step shape, and the insulating coating layer is inserted between the plurality of connection patterns.
【請求項2】少なくとも2枚のプリント基板の複数のパ
ターン同士を接続する為に、一方のプリント基板に複数
の接続パターンを露出させ、該一方のプリント基板の前
記接続パターンに対して、他方のプリント基板における
端部の接続パターンを重ねた状態で接続するプリント基
板構造において、 前記一方のプリント基板の前記複数の接続パターンの端
部の絶縁被覆層を段差状に形成し、該複数の接続パター
ンの間であって且つ前記他方のプリント基板の前記接続
パターンの端部位置より突出するように、該絶縁被覆層
を入り込ませたことを特徴とするプリント基板構造。
2. A method for connecting a plurality of patterns on at least two printed circuit boards, exposing a plurality of connection patterns on one printed circuit board, and connecting the plurality of connection patterns on the one printed circuit board to the other. In a printed circuit board structure in which connection patterns at ends of a printed circuit board are connected in an overlapping state, an insulating coating layer at an end of the plurality of connection patterns of the one printed circuit board is formed in a step shape, and the plurality of connection patterns are formed. The printed circuit board structure, wherein the insulating coating layer is inserted so as to protrude from an end position of the connection pattern of the other printed circuit board.
【請求項3】上記絶縁被覆層の段差状部を波形状にした
ことを特徴とする請求項(1)もしくは(2)記載のプ
リント基板構造。
3. The printed circuit board structure according to claim 1, wherein said stepped portion of said insulating coating layer is corrugated.
JP2171114A 1990-06-27 1990-06-27 Printed circuit board structure Expired - Fee Related JP2749966B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2171114A JP2749966B2 (en) 1990-06-27 1990-06-27 Printed circuit board structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2171114A JP2749966B2 (en) 1990-06-27 1990-06-27 Printed circuit board structure

Publications (2)

Publication Number Publication Date
JPH0458584A JPH0458584A (en) 1992-02-25
JP2749966B2 true JP2749966B2 (en) 1998-05-13

Family

ID=15917234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2171114A Expired - Fee Related JP2749966B2 (en) 1990-06-27 1990-06-27 Printed circuit board structure

Country Status (1)

Country Link
JP (1) JP2749966B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101699B2 (en) * 1993-09-29 1995-11-01 インターナショナル・ビジネス・マシーンズ・コーポレイション Printed circuit board and liquid crystal display device

Also Published As

Publication number Publication date
JPH0458584A (en) 1992-02-25

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