JP2750412B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for processing image data of a line drawing image such as a character or an illustration to reduce a line drawing portion.

[0002]

2. Description of the Related Art In the field of image processing for processing image data, a contraction (thinning) process is performed on a line drawing portion (hereinafter simply referred to as a line drawing) such as a region into which a character, an illustration or a pattern is fitted. May be valid. For example, it is effective in removing shape deformation (so-called noise) that appears as small irregularities at the boundary of a line drawing. Also, in character identification, the connection of the center line of a character has an important meaning, and in many cases, the thickness is not so significant, so the center line of the character may be obtained for character determination. Is also effective in this case.

Conventionally, as a method of such a thinning processing,
There are those using a four-neighbor window and those using an eight-neighbor window. That is, the bitmap data indicating the line drawing is multiplied by 4 neighborhood windows or 8 neighborhood windows for each pixel, and the central pixel P having a value of 1 is set to a value of 0 when even one value is included in the window. Thus, the line drawing portion has a narrowed shape. In the 4 neighborhood window, FIG.
As shown in FIG. 17A, four peripheral pixels (hatched portions in the figure) above, below, left and right of the central pixel P are selected, and in the eight-neighbor window, as shown in FIG. 8 peripheral pixels (hatched portions in the figure) around the pixel are selected. When the value 1 (line drawing portion) and the value 0 (background portion other than the line drawing) are mixed in these peripheral pixels, it means that the line drawing is cut off in the direction of the pixel having the value 0. By setting the center pixel P having the value 1 to the value 0, the boundary of the line drawing portion can be moved to the position of the center pixel P.

[0004]

However, in the prior art, bitmap data representing an image is fetched one by one into a 4-neighbor window or an 8-neighbor window.
After that, there is a problem that it takes a considerable processing time to perform operations such as performing a logical operation sequentially on each pixel for the entire image area to be processed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the prior art, and has as its object to provide an image processing apparatus capable of realizing a thinning of a line drawing at a high speed.

[0006]

In order to solve the above-mentioned problems, the present invention has the following arrangement. A first configuration of the image processing apparatus according to the present invention is an image processing apparatus that processes a line drawing image such as a character or an illustration in a bitmap format to thereby reduce a line drawing portion which is a target area to be reduced. A line data storage means for storing, for each line, three lines in the main scanning direction which are adjacent to each other in the bitmap format image data; and three line data stored in the line data storage means. A first logical product calculating means for calculating logical product of data for each set of the same digit position to generate new line data;
Left shift operation means for shifting the line data created by the AND operation means by one bit in the upper digit direction, and shift of the line data created by the first AND operation means in the lower digit direction by one bit Logical shift of data for each set of the same digit position in the three line data generated by the right shift operation means for shifting the digit and the first logical product operation means, the left shift operation means and the right shift operation means. The second aspect is to provide a second AND operation means for producing line data by reducing the width.

A second configuration of the image processing apparatus according to the present invention is to process a line drawing image such as a character or an illustration in a bitmap format to process a line drawing portion which is a target area to be reduced. An image processing apparatus for storing three adjacent lines in the main scanning direction in the bitmap format image data as first line data, second line data, and third line data for each line. Data storage means, first left shift operation means for shifting the first line data by one bit in the upper digit direction, and first right shift operation for shifting the first line data by one bit in the lower digit direction Means, and two line data generated by the first left shift operation means and the first right shift operation means, and the first line data having the same digit position. The calculates the logical sum of the data for each 4
First OR operation means for generating line data, second left shift operation means for shifting the third line data by one bit in the upper digit direction, and digit shift in the third line data by one bit in the lower digit direction Moving second right shift operation means; and two line data generated by the second left shift operation means and the second right shift operation means and the third line data; A second logical sum calculating means for calculating a logical sum to generate fifth line data; and calculating a logical product of data for each set of the same digit position in the second line data, the fourth line data and the fifth line data. To create sixth line data
AND operation means, third left shift operation means for shifting the sixth line data by one bit in the upper digit direction, and third right shift operation for shifting the sixth line data by one bit in the lower digit direction A logical AND of data for each set of the same digit position in the arithmetic means, the two line data generated by the third left shift arithmetic means and the third right shift arithmetic means, and the sixth line data. Having a second AND operation means for producing thinned line data,
It is a gist.

[0008]

In the first image processing apparatus of the present invention having the above-described configuration, three lines in the main scanning direction, which are mutually adjacent in the bitmap format image data, are line-by-line by the line data storage means. The new line data which is stored and becomes the logical product of these three line data is stored in the first line data.
Generated by AND operation means. This new line data is the same as the result of applying the following processing to the image data using the window.

This processing is performed as shown in FIG.
A logical product of values in the 1 × 3 window W1 whose longitudinal direction is in the sub-scanning direction and which is moved in the main scanning direction of the three line data in the main scanning direction is calculated. L1 is the same as the line data generated by the first AND operation means.

Next, the line data generated by the first AND operation unit is shifted by one bit in the upper digit direction by the left shift operation unit, and the line data generated by the first AND operation unit is shifted by one bit. Only by the right shift operation means in the lower digit direction.
Thinning line data, which is a logical product of the three line data generated by the first AND operation unit, the left shift operation unit, and the right shift operation unit, is generated by the second AND operation unit.

The thinned line data generated by the second logical operation means is the same as the result obtained by performing processing using the following window on the line data generated by the first logical operation means. Become. Taking the logical product of the three line data generated by the first logical product calculating means, the left shift calculating means, and the right shift calculating means means that the main scanning direction is extended in the main scanning direction as shown in FIG. The same as the process of sequentially moving the 3 × 1 window W2 in the main scanning direction of the line data L1 created by the first logical product calculating means and calculating the logical product of the values in the window W2. It will be.

Accordingly, the thinned line data thus created scans a window having a length of 3 × 3 in the main scanning direction and the sub-scanning direction, and the window W
The result is the same as the result obtained by calculating the logical product of the values in 2, and the same processing result as the thinning process using the window near 8 is obtained. Further, according to the present invention, the image data in the bitmap format is read in line units in the main scanning direction, and a thinning result can be obtained by performing an arithmetic processing in line units. There is no need to fetch bit data and perform arithmetic processing.

Next, the operation of the second image processing apparatus according to the present invention will be described. In the second image processing apparatus, three lines in the main scanning direction that are adjacent to each other in the bitmap format image data are defined as first line data, second line data, and third line data.
Line data is stored for each line by line data storage means. The first line data is shifted by one bit in the upper digit direction by the first left shift operation means, and the first line data is shifted by one bit in the lower digit direction by the first digit.
The digit is shifted by the right shift operation means, and a fourth logical sum of the two line data shifted by the digit and the first line data is obtained.
The line data is generated by the first OR operation means. Further, the third line data is shifted by one bit in the upper digit direction to the second line data.
The digit is shifted by the left shift operation means, the third line data is shifted by one bit in the lower digit direction by the second right shift operation means, and the logical sum of both line data shifted by these digits and the third line data is obtained. The fifth line data is generated by the second OR operation means.

The fourth line data has the following meaning. Taking the logical sum of the two line data generated by the first left shift operation means and the first right shift operation means and the first line data means that a 3 × 1 window whose longitudinal direction is the main scanning direction is used. Is scanned in the main scanning direction of the first line data, and the logical sum within the window is approximately set to the value of the center coordinate of the window.
The line data is a set of values of the center coordinates thus obtained. Similarly, the fifth line data is a set of center coordinate values approximately obtained in the 3 × 1 window in the longitudinal direction in the main scanning direction with respect to the third line data.

Next, sixth line data which is a logical product of the second line data, the fourth line data, and the fifth line data is created by the first logical product calculating means. Subsequently, the sixth line data is shifted by one bit to the third digit in the upper digit direction.
While the digit is shifted by the left shift operation means, the sixth line data is shifted by one bit in the lower digit direction by the third right shift operation means, and the logic of the two line data shifted by these digits and the sixth line data is further changed. Thinned line data to be a product is created by the second AND operation means. The first AND operation means, the third left shift operation means, the third
Since the operations by the right shift operation means and the second logical product operation means have the same functions as those of the first image processing apparatus described above, the line data generated by these means has a length in the main scanning direction and the sub-scanning direction. The result is the same as the result obtained by scanning the 3 × 3 window and calculating the logical product of the values in the window W2.

However, the first line data and the third line data for scanning this window are, as described above,
Since it is a set of values of the center coordinates approximately obtained in a 3 × 1 window with the main scanning direction as the longitudinal direction,
In the first and third lines, only one bit of the center coordinate has an effect on the AND operation by the second AND operation means. For this reason, the thinning line data generated by the second AND operation means can obtain a processing result close to the thinning processing using the windows near four. In addition, according to the present invention, arithmetic processing can be performed on a line-by-line basis, and it is not necessary to fetch all image data one by one into a window and perform arithmetic processing as in the related art.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to further clarify the structure and operation of the present invention described above, preferred embodiments of the present invention will be described below.

A. FIG. 2 is a block diagram showing a schematic configuration of an image processing apparatus as a first embodiment of the present invention. This image processing device
CPU1, ROM3, RAM5, image memory 7
, An input / output interface 9, first to third line buffers 11a, 11b, 11c,
And a line shifter 15. These components 1 to 15 are connected to each other by a bus line 17. The input / output interface 9 is connected to a magnetic disk device 21, a CRT display 22, a keyboard 23, and a mouse 24 as peripheral devices.

The magnetic disk device 21 is a storage medium for storing an image including a line drawing such as a character or an illustration as bitmap image data. From the stored image data, image data for each page to be processed is extracted, transferred to the image memory 7, and stored. The CRT display 22 is a display unit for displaying an image to be processed, and also displays the image after the thinning process.

First to third line buffers 11a to 11a
Reference numeral 1c denotes memories each having a capacity capable of storing one line in the main scanning direction in one page of image data stored in the image memory 7. The logical operation unit 13 includes AND units 13a and 13c for calculating a logical product of data at the same digit position in a plurality of input line data, and an inverter 13b for inverting the value of each digit of the input line data. The function is switched in response to a control command from the CPU 1.

The line shifter 15 is a circuit for performing an operation on line data. As shown in FIG. 3, the input side path is branched in three directions, and a left shifter 15a, a right shifter 15b and a direct connection line 15c are connected in parallel. And the output side is connected to the AND device 15d. Note that in the line memory of this embodiment, the so-called LSB is
Is described as being located at the left end. Although "digit" and "bit" are equivalent as data units,
It is used appropriately for explanation.

The left shifter 15a provided in the line shifter 15 is an arithmetic and logic unit for shifting data consisting of a plurality of bit strings by one bit in the upper digit direction, and the right shifter 15b is provided with a data shift consisting of a plurality of bit strings. Is an arithmetic and logic unit that shifts one digit in the lower digit direction by one bit. Both shifters 15a and 15b replenish the empty position (the least significant digit in the case of the left shifter 15a and the most significant digit in the case of the right shifter 15b) generated by the digit shift with a value 0, and push out one bit. It has a function to throw away. Each of the shifters 15a and 15b is composed of a barrel shifter that connects MOS circuits arranged in a crossbar switch shape and sequentially shifts control lines, and once shifts one entire line of image data in the main scanning direction. It has a capacity to move the digit.

In the image processing apparatus having such a configuration, the CPU
In response to the exchange of data with each of the constituent elements according to No. 1, the circuit configuration shown in the block diagram of FIG. 4 is realized.

That is, in the circuit configuration shown in FIG. 4, the first to third line buffers 11a to 11c store the first
The third line data LD1, LD2, and LD3 are sent to the AND unit 13a of the logical operation unit 13, and the AND unit 13a
The line data LD4 output from the line shifter 15
Sent to The line shifter 15 outputs thinning line data LD5 as a processing result. Further, the thinned line data LD5 is returned to the logical operation unit 13 and input to the inverter 13b of the logical operation unit 13. Inverter 13b
The line data LD6 whose value has been inverted by the second line data LD2 is stored in the second line buffer 11b.
Is input to the AND device 13c. The AND device 13c performs a logical operation on the two line data LD2 and LD6, and outputs the operation result as edge data LD7. The thinned line data LD5 and the edge data LD7 are stored in the image memory 7 via the bus line 17 in FIG.

Next, the operation of the image processing apparatus having such a configuration will be described. The CPU 1 reads one page of bitmap image data stored in the magnetic disk drive 21 via the input / output interface 9 and reads the image memory 7.
Is executed in advance. In this way, the image memory 7 stores an image for each page to be processed.

Next, the CPU 1 sequentially extracts line data for one line in the main scanning direction from the image data for one page stored in the image memory 7 in the sub-scanning direction and stores the line data in the third line buffer 11a. At the same timing, the line data stored in the first to third line buffers 11a to 11c are stored while sequentially shifting the second to the first and the third to the second.

The CPU 1 stores the first to third line data LD in the first to third line buffers 11a to 11c.
1 to LD3 are stored, first of all,
Or the third line data LD1 to LD3 are logical operation units 1
3 and the logical operation unit 13 outputs new line data LD4 obtained by calculating the logical product of the first to third line data for each digit.

The line data LD4 output from the AND unit 13a is sent to the line shifter 15. In the line shifter 15, the line data LD4 is shifted by the left shifter 15a in the upper digit direction, and the line data LD4 is shifted.
Is shifted in the lower digit direction by the right shifter 15b, and then both line data LD created by these digit shifts are shifted.
The logical product of each of the digit positions of the 4L, LD4R and the line data LD4 that has not been shifted is calculated by the AND unit 15d (see FIG. 3). The result of this operation is input to the bus line 17 as narrowing line data LD5 for the main scanning line indicated by the second line data LD2, and is stored in the image memory 7.

Further, in this embodiment, the line shifter 15
Is input to the logical operation unit 13b. The value of the line data LD5 is inverted by the inverter 13b, and the line data LD6
The AND of each digit position with the second line data LD2 is obtained by the AND unit 13c. The line data thus created is input to the bus line 17 as edge data indicating the contour of the line image before thinning, and is stored in the image memory 7.

How the line drawing is reduced by the operation of the image processing apparatus will be described below with reference to a specific example.

FIG. 5A shows bitmap format image data DT representing a line drawing LA drawn with a value of 1 on a background indicated by a value of 0. From this image data DT, the scanning line (line) number in the sub-scanning direction is now the n-th (where n is a positive number and takes a value from the value 0 to the maximum bit number N in the sub-scanning direction) n + 1 The line data of the (n) th and (n + 2) th main scanning directions are sequentially read. These read line data are stored in the first to third line buffers 11a, 11b, 11c as line data LD1 to LD3. The storage results are shown as LD1, LD2, and LD2 in FIG.
This is shown in LD3.

First to third line buffers 11a, 1
When the line data LD1 to LD3 are stored in 1b and 11c, as shown in FIG.
Is sent to the AND device 13a, and the line data LD1
The line data LD4, which is the logical product of .about.LD3, is created. Next, the line data LD4 is sent to the left shifter 15a, and line data LD4L is generated by shifting the line data LD4 by one bit in the upper direction.

On the other hand, the line data LD4 is supplied to the right shifter 1
5b, line data LD4R is generated by shifting the line data LD4 by one bit in the lower direction.

Subsequently, the line data LD4 and the line data LD4L, LD4R shifted by one digit are sent to the AND unit 15d, and these line data LD4, LD4
Line data LD5, which is the logical product of L and LD4R, is created. The line data LD5 is thinned line data of the (n + 1) th line, and is stored in the image memory 7.

In the same manner, in the image data DT shown in FIG. 5A, these processes are sequentially performed on the nth line from the 0th line to the N-2th line. To be stored. Thus, the thinning process can be performed over the entire area of the image data DT. FIG. 5B shows the thinned line drawing CLA in the image memory 7 obtained as a result of the thinning process. Comparing FIG. 5A and FIG. 5B, it can be seen that the line drawing LA has been reduced to the line drawing CLA.

In the image processing apparatus of this embodiment, the thinned line data LD5 subjected to the thinning processing is sent to the inverter 13b, and as shown in FIG. Inverted line data LD6 is created. Subsequently, the line data LD6 and the line data LD2 stored in the second line buffer 11b are sent to the AND device 13c, and line data LD7 obtained by calculating the logical product of the two line data LD2 and LD6 is created. The processing shown in FIG. 7 is performed in an area other than the line drawing CLA after the thinning and the line drawing L before the thinning.
Since the overlapped portion with A is obtained, the line data LD7 as the processing result is, as shown in FIG. 8, the difference between before and after the thinning, that is, by the thinning process. This indicates the deformation area ER. This deformation area ER
Is equivalent to the contour of the line drawing LA before thinning, and the line data LD7 is input to the bus line 17 as edge data and stored in the image memory 7.

The AND devices 13a and 15d of the present embodiment
Is an OR unit for calculating the logical sum of the line data, so that pseudo fat data can be obtained.

The thinned line data LD5 produced by the image processing apparatus of the first embodiment described above is multiplied by a window having a length of 3 × 3 in the main scanning direction and the sub-scanning direction. The result is the same as the result obtained by calculating the logical product of the values within, and the same processing result as the thinning processing using the window near eight is obtained. Further, in the present image processing apparatus, the bitmap format image data is read line by line in the main scanning direction, and a thinning result can be obtained by performing arithmetic processing in line units. It is not necessary to take in bit data one by one and perform arithmetic processing. For this reason, the line drawing can be reduced at a high speed. In this embodiment,
Since the edge portion of the line drawing is obtained using the thinned image, the edge portion can also be obtained at a high speed.

B. Modification Example In the first embodiment, the left shift unit 15a and the right shift unit 15b are used to shift the entirety of one line in the main scanning direction at a time. However, instead of this, a bit string of one word ( For example, one shift register that shifts the digit by 32 bits may be used to shift the digit of one line by software processing. Hereinafter, the procedure of digit shifting by the processing of such software will be described in detail.

The flow chart of FIG. 9 shows the procedure of digit shift in the lower digit direction, that is, right shift processing. CPU1
As shown in FIG. 10, when the process is started, first, the line data is divided into 32 bits, which is the number of bits of one word, and each of the divided areas is divided as shown in FIG.
H (1), H (2),..., H (M) in order from the head direction (step S100). Next, a value 1 is set to the variable k (step S110), and the bit string stored in the divided area H (k) is transferred to the shift register (step S120). Next, the shift register executes a right shift for moving the stored bit string in the lower digit direction (step S130). At this time, the value 0 is set in the most significant digit.

Subsequently, the contents of the current shift register are transferred following the bit string previously transferred to the work area prepared in advance in the RAM 5 (step S140). Thereafter, the variable k is incremented by the value 1 (step S
150), and transfers the bit string stored in the divided area H (k) to the shift register (step S160). Next, the shift register executes a right shift for moving the stored bit string in the lower digit direction (step S170).

After the execution of step S170, the divided area H
It is determined whether or not the value of the least significant digit of the bit string stored in (k-1) is 1 (step S180). If it is determined that the value is 1, the value 1 is added to the most significant digit of the shift register. Is transferred (step S190). On the other hand, step S180
If it is determined that is not the value 1 in step S190, step S190
Skip processing. Thereafter, the contents of the shift register are transferred to the work area (step S192). At this time, it is assumed that data is written from a position next to the position written by the previous data transfer.

Thereafter, it is determined whether or not the variable k has reached the number M of the divided areas H (step S194). If it is determined that the variable k has not reached the number M, the process returns to step S150 and returns to step S1.
The processes from 50 to S194 are repeatedly executed. on the other hand,
If it is determined in step S194 that the variable k has reached the value M, the process goes to “END” to end the processing of this routine.

According to the right and left shift processing of such a configuration, the line data for one line in the main scanning direction can be shifted in the lower digit direction and the upper digit direction by using only one shift register. it can. Note that the procedure of the left shift processing can be easily realized by reversing the designation direction of the divided area in the right shift processing, the writing direction of the data of the work area, and the like. I do.

Next, another image processing apparatus for realizing the narrowing around eight will be described. In the first embodiment, first,
New line data is created by calculating the logical product of three adjacent lines in the main scanning direction, and then the line data is subjected to left shift and right shift, respectively, and the result of both shifts is compared with the line data. The logical product is obtained and the line data is reduced, but instead of this, 8
Neighboring narrowing may be realized. First, 1 in the main scanning direction
Perform a left shift and a right shift on the line, respectively.
The logical product of the result of both shifts and the line data before shifting is calculated. Similarly, the same processing as that for the one line is performed on two lines adjacent to the one line. After that, the logical product of the three line data thus formed is obtained to make the line data thinner. As a result, similarly to the first embodiment, the narrowing of the line drawing in the vicinity of 8 can be realized at a high speed.

C. FIG. 11 is a block diagram showing a schematic configuration of an image processing apparatus as a second embodiment of the present invention. This image processing apparatus is different from the first embodiment in that the second line shifters 201a to 201a
201c is provided, and the other configuration is the same. In this embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and the line shifter 15 of the first embodiment is referred to as a first line shifter 15 in this embodiment.

The second line shifters 201a to 201c
This is a circuit that receives the line data LD1 to LD3 output from the first to third line buffers 11a to 11c and performs an operation on the line data LD1 to LD3, and has the following configuration. That is, the second line shifter 20
1a to 201c, as shown in FIG. 12, the input-side path branches in three directions, and the left shifter 211 and the right shifter 21
2 and a direct connection line 213 are connected in parallel, and their outputs are connected to an OR unit 214. Note that the left shifter 2
11 and the input side of the right shifter 212
5 and 216 are provided respectively, and the left shifter 21 is provided.
1, lines 217 and 2 bypassing right shifter 212, respectively
The 18 side is configured to be selectable by selectors 215 and 216, respectively. Further, the selector 219 can select between the left shifter 211 and the right shifter 212.

The selectors 215, 216, 2
By sending a control command to the line 19, the signal flow of the input line data LD1 (or LD2, LD3) is sent to the left shifter 211, the right shifter 212, and the direct connection line 213, respectively. Shifter 211
And the direct connection lines 213 and 21 bypassing the right shifter 212.
7,218.

The second line shifters 201a to 201
c and left shifter 211 and right shifter 21
2 has the same configuration as the left shifter 15a and the right shifter 15b of the first embodiment. The OR unit 214 calculates the logical sum of the plurality of line data by calculating the logical sum of the data for each set of the same digit position of the input plurality of line data.

In the image processing apparatus having such a configuration, the CPU
In response to the exchange of data with each of the constituent elements according to No. 1, the circuit configuration shown in the block diagram of FIG. 13 is realized. That is, in the circuit configuration shown in FIG.
The first to third line data LD1, LD2, LD3 stored in the line buffers 11a to 11c are sent to the second line shifters 201a to 201c, respectively. Next, the line data LD11, LD12, LD13 output from the second line shifters 201a to 201c are sent to the AND unit 13a of the logical operation unit 13, and the AND unit 13a
Is output to the first line shifter 15. Then, the line shifter 15 outputs thinned line data LD15 as a processing result.

Further, the thinning line data LD15 is returned to the logical operation unit 13, and the inverter 13b of the logical operation unit 13
Is input to The line data LD16 whose value has been inverted by the inverter 13b is input to the AND device 13a together with the second line data LD2 stored in the second line buffer 11b. In the AND device 13a, both line data LD
2. The logical product of LD16 and LD16 is obtained, and the operation result is output as edge data LD17.

Next, the operation of the image processing apparatus having such a configuration will be described. The CPU 1 stores the first to third line data LD in the first to third line buffers 11a to 11c.
When 1 to LD3 are stored, the following operations are sequentially performed. First, the first to third line data LD1 to LD3 are stored in the second line shifters 201a to 201c.
Respectively. At this time, the CPU 1 sends a control command to each of the second line shifters 201a to 201c so that the first second line shifter 201a and the third second line shifter 201c are input to the left shifter 211 and the right shifter. 212 and the direct connection line 213 side, and the second second line shifter 201b is configured so that the input signal bypasses the left shifter 211 and the right shifter 212.

Therefore, the first second line shifter 201a transfers the line data LD1 to the left shifter 211.
To move to the upper digit direction, and the line data L
D1 is shifted by the right shifter 212 in the lower digit direction,
Thereafter, the OR of each digit between the two line data created by these digit shifts and the line data LD1 that has not been digit shifted is obtained by the OR unit 214 (see FIG. 12). Further, the third second line shifter 201c performs the same processing as that of the first second line shifter 201a on the third line data LD3. In the second second line shifter 201b, the line data LD2 is divided into three directions and bypasses the shifter to obtain the logical sum of them by the OR unit 214. The output data LD12 from the second line shifter 201b thus obtained is the same as the input data LD2.

Next, the second line shifters 201a to 201a
1c output from the line data LD11 to LD13
Is sent to the logical operation unit 13, and the logical operation unit 13 outputs new line data LD <b> 14 obtained by calculating a logical product for each digit of each line data.

The line data LD14 output from the AND unit 13a is sent to the first line shifter 15. In the first line shifter 15, the line data LD14 is shifted to the upper digit direction by the left shifter 15a, and the line data LD14 is shifted to the lower digit direction by the right shifter 15b. Both line data and line data LD with no digit shift
The AND of each digit with 4 is calculated by the AND unit 15d (see FIG. 3). The result of this operation is the second line data LD
The data is input to the bus line 17 as the thinning line data LD15 in the main scanning line indicated by 2, and is stored in the image memory 7.

Further, in this embodiment, as in the first embodiment, the line data LD15 is input to the inverter 13b and the AND unit 13a. In the AND device 13a, the inverter 1
3b and the line data LD16 and the second
Second line data L stored in line buffer 11b
The logical product of D2 and data at each digit position is obtained. The line data thus created is input to the bus line 17 as edge data and stored in the image memory 7.

Next, how the line drawing is reduced by the operation of the image processing apparatus will be described with reference to a specific example.
As in the first embodiment, the bitmap format image data DT shown in FIG. From the image data DT, first, line data LD1 to LD3 in the main scanning direction from the nth to the (n + 2) th are read out and stored in the first to third line buffers 11a, 11b and 11c, respectively. The storage results are shown in LD1 and LD2 in FIG. 15 and LD3 in FIG.

First to third line buffers 11a, 1
1b and 11c are first to third line data LD1 to LD
When D3 is stored, the content of the line data changes according to the procedure shown in FIGS. That is, as shown in FIG. 15, the first line data LD1 is sent to the left shifter 211 of the second line shifter 201a, and line data LD1L is generated by shifting the first line data LD1 by one bit in the upper direction. . When moving this digit,
The value 0 is added to the vacant position of the least significant digit generated by the digit shift, and one bit of the pushed out most significant digit is discarded.

The first line data LD1 is also sent to the right shifter 212 to produce line data LD1R obtained by shifting the first line data LD1 by one bit in the lower direction. At the time of this digit shift, a value 0 is added to the empty position of the most significant digit generated by the digit shift, and one bit of the pushed out least significant digit is discarded. Subsequently, the first line data LD1, the line data LD1L, and the line data LD1R are sent to the OR unit 214, and the line data LD11 obtained by calculating the logical sum of the line data LD1, LD1L, and LD1R is created.

On the other hand, the third line data LD3 stored in the third line buffer 11c is stored in the second line shifter 20.
1c to the left shifter 211 and the third line data L
Line data LD3L is generated by shifting D3 one bit higher in the upper direction. At the time of this digit shift, a value 0 is added to the vacant position of the least significant digit generated by the digit shift, and one bit of the pushed out most significant digit is discarded. Further, line data LD13 is generated from the third line data LD3 in the same manner as the above-mentioned LD2.

Thereafter, the flow shifts to FIG.
D11 and LD13 and the second line data LD2 stored in the second line buffer 11b (actually, the data passed through the second line shifter 201b, but have the same contents as the second line data LD2). The line data LD2 and LD1 are sent to the AND device 13a.
Line data LD14, which is the logical product of LD1 and LD13, is created. Next, the line data LD14 is sent to the left shifter 15a, and line data LD14L is generated by shifting the line data LD14 by one bit in the upper direction. At the time of this digit shift, a value 0 is added to the vacant position of the least significant digit generated by the digit shift, and one bit of the pushed out most significant digit is discarded.

On the other hand, the line data LD14 is also sent to the right shifter 15b to produce line data LD14R obtained by shifting the line data LD14 by one bit in the lower direction. At the time of this digit shift, a value 0 is added to the empty position of the most significant digit generated by the digit shift, and one bit of the pushed out least significant digit is discarded.

Subsequently, the line data LD14 and both line data LD4L and LD4R shifted by one digit are sent to the AND unit 13a, and these line data LD14 and LD4 are sent.
Line data LD1 that is the logical product of 14L and LD4R
5 is made. The line data LD15 is thinned line data as a processing result obtained by performing a thinning process on the line data LD2 of the (n + 1) th line.

In the image data DT shown in FIG. 14A, the n-th line is sequentially moved from the 0th line to the N-2th line, so that a thinning process can be performed over the entire area of the image data DT. it can. FIG. 14B shows a thinned line drawing CLA obtained as a result of the thinning process. Comparing FIG. 14A and FIG. 14B, it can be seen that the line drawing LA has been narrowed down to the line drawing CLA. The edge data indicating the outline of the line image is obtained from the thinned line data LD15. However, since this configuration is the same as that of the first embodiment, the description is omitted.

[0065] In the image processing apparatus of the second embodiment, as described in detail above, the thinning process using the 4-neighbor window
Close processing results are obtained. Moreover, in this embodiment, as in the first embodiment, the arithmetic processing can be performed on a line-by-line basis, and it is not necessary to fetch the bit data one by one into the window and perform the arithmetic processing as in the related art. For this reason, the line drawing can be reduced at a high speed.

Next, another image processing apparatus for realizing narrowing of four neighborhoods will be described. First, any one in the main scanning direction
A left shift and a right shift are performed on the line data of the line (n-th line). Next, the line data after the left shift, the line data after the right shift, the line data before the shift, and the line data of the (n-1) th line and the (n + 1) th line adjacent to the nth line, that is, a total of 5 AND the two line data. The result of this logical product becomes the thinning line data. In this manner, as in the second embodiment, narrowing of the line drawing in the vicinity of 4 can be realized at a high speed.

The embodiments of the present invention have been described in detail above.
The present invention is not limited to these embodiments at all, and it goes without saying that the present invention can be implemented in various modes without departing from the gist of the present invention.

[0068]

As described in detail above, according to the image processing apparatus of the present invention, since the thinning process can be performed in line units in the main scanning direction, the thinning of the line image can be realized at a high speed. can do.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating an operation of a first image processing apparatus according to the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an image processing apparatus as a first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a schematic configuration of a first line shifter 15 provided in the image processing apparatus.

FIG. 4 is a block diagram illustrating a circuit configuration realized by the image processing apparatus.

FIG. 5 is an explanatory diagram showing thinned image data reduced by the image processing apparatus together with original image data.

FIG. 6 is an explanatory diagram showing how the line data LD1 to LD3 stored in the first to third line buffers are changed to create the thinned line data LD5.

FIG. 7 is an explanatory diagram showing how edge data LD7 is created from thinned line data LD5.

FIG. 8 is an explanatory diagram showing a contour of a line image represented by edge data LD7.

FIG. 9 is a flowchart illustrating a procedure of a right shift process executed by the CPU 1 as a modified example of the first embodiment.

FIG. 10 shows divided areas H (1) and H of one-line data.
It is explanatory drawing which shows (2), ..., H (M).

FIG. 11 is a block diagram illustrating a schematic configuration of an image processing apparatus according to a second embodiment of the present invention.

FIG. 12 is a block diagram illustrating a schematic configuration of a second line shifter 201a provided in the image processing apparatus.

FIG. 13 is a block diagram illustrating a circuit configuration realized by the image processing apparatus.

FIG. 14 is an explanatory diagram showing thinned image data thinned by the image processing apparatus together with original image data.

FIG. 15 is an explanatory diagram of the first half of a procedure showing how the line data LD1 to LD3 stored in the first to third line buffers are changed to create the thinned line data LD5.

FIG. 16 is an explanatory diagram of the latter half of the procedure.

FIG. 17 is an explanatory diagram showing windows near 4 and 8 as a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 7 Image memory 11a 1st line buffer 11b 2nd line buffer 11c 3rd line buffer 13 Logical operation unit 13a, 13c AND device 13b Inverter 15 Line shifter 15a Left shift device 15b Right shift device 15d AND device 201a Second line shifter 201b Second line shifter 201c Second line shifter 211 Left shifter 212 Right shifter 214 OR unit LD1 First line data LD2 Second line data LD3 Third line data LD5 Thinning line data LD7 Edge data LD15 Thinning line data LD7 Edge data

Claims (2)

(57) [Claims] 1. An image processing apparatus for processing a line drawing image such as a character or an illustration in a bitmap format to reduce a line drawing portion to be a target area to be reduced. Line data storage means for storing three lines in the main scanning direction which are adjacent to each other among the image data of the format as three line data, and the same digit in the three line data stored in the line data storage means First logical product operation means for calculating logical product of data for each set of positions to generate new line data; digitizing the line data generated by the first logical product operation means by one bit in the upper digit direction Moving left shift operation means, and right shift operation means for shifting the line data created by the first AND operation means by one bit in the lower digit direction In the three line data generated by the first AND operation unit, the left shift operation unit, and the right shift operation unit, the AND operation of the data is performed for each set of the same digit position to narrow the line data to generate line data. An image processing apparatus comprising: a second AND operation unit. 2. An image processing apparatus for processing image data representing a line drawing image such as a character or an illustration in a bitmap format, thereby narrowing a line drawing portion to be a narrowing target area. Line data storage means for storing three adjacent lines in the main scanning direction among the image data of the format as first line data, second line data and third line data for each line; First left shift operation means for shifting the digit by one bit in the upper digit direction, first right shift operation means for shifting the first line data by one bit in the lower digit direction, the first left shift operation means, The logical sum of the data is calculated for each pair of the same digit position between the two line data generated by the first right shift calculating means and the first line data, and First OR operation means for generating line data, second left shift operation means for shifting the third line data by one bit in the upper digit direction, and digit shift of the third line data by one bit in the lower digit direction Moving second right shift operation means; two line data generated by the second left shift operation means and the second right shift operation means and the third line data; A second logical sum calculating means for calculating a logical sum to generate fifth line data; and calculating a logical product of the data for each set of the same digit position in the second line data, the fourth line data and the fifth line data. First AND operation means for generating sixth line data by means of: a third left shift operation means for shifting the sixth line data by one bit in the upper digit direction; Third right shift operation means for shifting data by one bit in the lower digit direction; two line data generated by the third left shift operation means and the third right shift operation means; and the sixth line data. 2. An image processing apparatus comprising: a second logical product calculating means for calculating a logical product of data for each set at the same digit position to create line data by thinning.