JP2750776B2 - Graphic equalizer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a graphic equalizer circuit, and more specifically, has a high degree of freedom in setting a bias of an input signal, and can improve an S / N ratio. The present invention relates to a graphic equalizer circuit suitable for use in an IC.

[Prior Art] FIGS. 3A and 3B are explanatory diagrams of a conventional graphic equalizer circuit.

As shown in FIG. 1A, this circuit includes a variable resistor (volume, V) between a non-inverting input terminal (+ phase input) and an inverting input terminal (−phase input) of an operational amplifier (OP) 1.
R) 2 are connected, and the variable terminal side is grounded via the LCr series resonance circuit 3. The output signal (voltage) V ₀ of the operational amplifier 1 is fed back to the inverting input terminal via the resistor R ₀ , and the input signal (voltage) Vi is supplied via the resistor Ri.

Here, assuming that the open loop gain of the operational amplifier 1 is A, if A >> 1, and Ri and R ₀ are Ri = R ₀ = R, the following relationship is established. The input / output relationship at the resonance frequency f ₀ of the series resonance circuit 3 when the variable terminal of the volume 2 is at the point A is expressed by the following equation. At this time, no current flows through the volume 2. Therefore, the operational amplifier 1
Is a buffer amplifier.

The input / output relationship at the resonance frequency f ₀ of the series resonance circuit 3 when the variable terminal of the volume 2 is at the point B is as follows. At this time, no current flows through the volume 2. Therefore, the operational amplifier 1 operates as a normal amplifier.

The input / output relationship of the series resonance circuit 3 at the resonance frequency f ₀ when the variable terminal of the volume 2 is at the middle point is V ₀ = Vi.

As can be understood from the above relational expression, this circuit has a graphic equalizer function. Note that r is the resistance value of the resistor r of the resonance circuit 3.

The above is the case where there is one series resonance circuit 3. Normal,
The graphic equalizer circuit has an audio band of 5 to 5.
It is divided into about seven divisions, and an operation of attenuating or emphasizing over a certain band from a specific center frequency is performed.
For this purpose, 5 to 7 series resonance circuits 3 having different center frequencies f ₀ and 5 to 7 volume controls 2 corresponding thereto are connected in parallel to the non-inverting input terminal and the inverting input terminal of the operational amplifier 1, respectively. Become.

Such a circuit has a disadvantage that it is difficult to form an IC because the volume 2 is connected to the input side of the operational amplifier 1.
Therefore, Japanese Patent Application Laid-Open
No. -276312. This circuit employs a configuration in which the volume 2 is drawn out to control the current values of voltage-current conversion circuits (hereinafter, V / I conversion circuits) 3 and 4 as shown in FIG. These V / I conversion circuits 3, 4
Receives an input signal via the active filter 5 and converts a voltage corresponding to the frequency into a current value. The converted current values are respectively applied to the non-inverting input terminal and the inverting input terminal of the operational amplifier 1. Thus, a signal in the band set by the active filter 5 is obtained.
Note that the V / I conversion circuits 3 and 4 operate differentially with each other according to the operation of the volume.

[Problem to be Solved] In the circuit of FIG. 3 (a), an external capacitor is required even if the resonance circuit is subjected to coil simulation, and a plurality of volumes connected to the operational amplifier are provided. However, there is a drawback that noise is easily generated due to these routings, and the number of pins for wiring connection from the circuit to the outside is increased.

On the other hand, the circuit of FIG. 2B is easier to be integrated into a circuit than the circuit of FIG. 2A, but requires a resistor Ri in series on the input side, and the value of the resistor Ri is used as the feedback resistor of the operational amplifier 1. However, there is a problem in that there is a limitation in circuit design due to the fact that the value must be set to almost the same value as in the above, and there is a limitation in the level of the input voltage Vi. In addition, there is a disadvantage that the S / N ratio is lowered depending on the input bias level and a dynamic range cannot be sufficiently obtained.

An object of the present invention is to solve such a problem of the prior art, and an object of the present invention is to provide a graphic equalizer circuit which is easily formed into an IC, is not easily limited by a bias level or the like, and has a large dynamic range. .

[Means for Solving the Problems] The graphic equalizer circuit of the present invention for achieving the above object has the following features: a first voltage-current conversion circuit receiving an input signal; an active filter receiving the output; A load resistance inserted between the output of the first voltage-current conversion circuit and the reference bias voltage line, and a voltage generated by the output generated at the load resistance are received at a first input thereof. An operational amplifier fed back to its second input through a phase opposite to the phase of the first input;
An output side is connected to a terminal side of a load resistor that generates a voltage by the output, has a first variable current source, receives an output of the active filter, and controls a gain according to a current value of the first variable current source. A second voltage-current conversion circuit,
A third current source having an output side connected to the second input side of the operational amplifier, receiving the output of the active filter, and controlling the gain according to the current value of the second variable current source. A current conversion circuit, wherein the current values of the first and second variable current sources are externally controlled.

[Operation] As described above, the V / I conversion circuit is provided on the input side, receives the input signal, and causes a current corresponding to the voltage level of the input signal to flow through the load resistor to generate a voltage. In order to attenuate and emphasize the signal according to the frequency, the current of the V / I conversion circuit is received by the active filter to generate a voltage corresponding to the frequency, and the voltage is applied to the attenuation side. And V / I conversion circuits provided corresponding to the emphasis side to convert to current,
Further, since these current conversion outputs are configured to be added (or subtracted) by the above-described load resistors, it is not necessary to insert resistors in series on the input side.

As described above, the input side is a V / I conversion circuit, and since no resistance is inserted in series with the input of the amplifier, the degree of freedom in setting the input bias and the like is increased, and the dynamic range is reduced. We can secure enough. Moreover,
Rather than a direct volume control method, DC control is used, so a circuit that is suitable for IC integration and has a large S / N ratio can be obtained.

In addition, the operational amplifier inserted as the output of the graphic equalizer circuit has its first input and its second input having the opposite phase, that is, the (+) phase input and the (-) phase input are virtual. Since there is a short-circuit relationship, the equalized signal applied to the (-) phase input is equivalently added (subtracted because the phase is different, at the load resistor terminal) via the (+) phase input side. Will be. This results in all equalized input signals occurring at the terminals of the load resistor. Since the other terminal of the load resistor is connected to the reference bias line, all equalized signals are superimposed at the reference bias point. As a result, the fluctuation of the reference level is small, the S / N ratio is improved, and the dynamic range can be increased.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a basic block diagram of a graphic equalizer circuit to which the present invention is applied, and FIG. 2 is a specific circuit diagram thereof. Note that components equivalent to those in FIG. 3 are denoted by the same reference numerals.

Reference numeral 10 denotes a graphic equalizer circuit, which receives an input signal Vi by a V / I conversion circuit 11, and outputs a current output to a load resistor RL. The terminal 11a of the load resistor RL is a terminal at which a voltage is generated by the above-mentioned current.
Connected to the non-inverting input terminal of The terminal on the opposite side is connected to the reference bias line Vr.

The output current of the V / I conversion circuit 11 is further applied to a plurality of active filters 12a, 12b,. A voltage control type voltage source type active filter (VCVS) is generally used as the active filter. Here, a voltage source type of current input is used. Therefore, the output of the active filter 12a usually becomes a voltage. The output voltage of the active filter 12a is applied to V / I conversion circuits 13a and 14a, respectively. The output current of the V / I conversion circuit 13a is applied to the terminal 11a connected to the non-inverting input terminal of the load resistor RL, and the output current of the V / I conversion circuit 14a is applied to the inverting input terminal of the operational amplifier 1. Have been. V / I
The conversion circuits 13a and 14a usually operate in opposite phases.

The other active filters 12b,.
The output side is connected to two V / I conversion circuits similar to the I / L conversion circuits 13a and 14a, respectively, and the V / I conversion circuits
They are connected to the non-inverting input terminal and the inverting input terminal of the operational amplifier 1 in the same relationship as the conversion circuits 13a and 14a, respectively, but these are omitted in the figure.

The feedback resistor R ₀ to the inverting input terminal side of the operational amplifier 1
Here, R ₀ = RL, and the resistance value is the same value as the load resistance RL. Also, let the voltage-current conversion rate of each V / I conversion circuit be 1 / RL (or K × 1 / RL). K
Is the gain of the V / I conversion circuits 13a and 14a, and gm is controlled by externally controlling the current values of the current sources 13b and 14b of these emitter-coupled differential pairs. ,
For example, it is selectively controlled by the control circuit 15 from the outside via the volume 16.

When the setting of the volume 16 is at the middle point, the control circuit 15 controls the currents of the current sources of the V / I conversion circuits 13a and 14a to be zero so that they do not operate. Also, when the setting of the volume 16 is lower than the midpoint, the V /
The operation of the V / I conversion circuit 14a is stopped by operating only the I conversion circuit 13a. Further, in the signal emphasis state where the setting is above the middle point, only the V / I conversion circuit 14a is operated and the operation of the V / I conversion circuit 13a is stopped.

Next, such a control operation will be described. The voltage at the non-inverting input terminal of the operational amplifier 1 (voltage at terminal 11a)
Is set to VL, and for convenience of explanation, the bias voltage Vr is set to the ground level. Also, the explanation will be focused on the V / I conversion circuits 13a and 14a,
Since the circuits of the other active filters 12b,... Are the same, the description thereof is omitted.

In this case, only the V / I conversion circuit 13a operates according to the set value of the volume 16 below the middle point, and the V / I conversion circuit 1
4a is controlled not to operate. Therefore, the operational amplifier 1 becomes a buffer amplifier. The input / output relationship is (However, the frequency f ₀ is the center frequency of the active filter 12a).

As a result, the amount of attenuation with respect to the input signal Vi can be controlled by selecting the value of K. Then, at the time of maximum signal attenuation (when the setting of the volume 16 corresponds to the case where the volume 2 in FIG. 3A is set to the point A), the gain K of the V / I conversion circuit 13a takes the largest value.

In this case, only the V / I conversion circuit 14a operates according to the set value of the volume 16 above the middle point, and the V / I conversion circuit 1
3a is controlled not to operate. As a result, the input signal
The relationship between Vi and the non-inverting input VL of the operational amplifier 1 is Vi = VL. Therefore, the input / output relationship is (However, the frequency f ₀ is the center frequency of the active filter 12a).

As a result, the amount of enhancement for the input signal Vi can be controlled by selecting the value of K. Then, at the time of maximum signal emphasis (when the setting of the volume 16 corresponds to the case where the volume 2 in FIG. 3A is set to the point B), the gain K of the V / I conversion circuit 14a takes the largest value.

Flat state At this time, the V / I conversion circuit 13a and the V / I conversion circuit 14a are controlled so as not to operate together. The operational amplifier 1 simply serves as a buffer, so that Vi = V ₀ . This is volume 16
Corresponds to the case where the volume 2 in FIG. 3A is set to the middle point.

For this reason, this circuit can be provided with the function of a graphic equalizer, and a signal (voltage) is input to the operational amplifier 1 by a load resistor RL inserted in parallel with the operational amplifier 1. There is no need to insert a resistance value in series on the side. In addition, since the input signal is received by the V / I conversion circuit 11, the bias level on the input side can be set freely, and
The S / N ratio does not decrease and the dynamic range cannot be taken sufficiently.

FIG. 2 is a specific example of the circuit shown in FIG. 1, and 21 corresponds to the V / I conversion circuit 11 in FIG. Reference numeral 22 denotes an active filter circuit forming a bandpass filter. This circuit 22
The differentiating circuit 24 consisting of the variable gm circuit 23 and a capacitor C ₁
When integrating circuit 25 comprising a variable gm circuit 25 and a capacitor C ₂
In a cascade connection.

26 is a circuit corresponding to the V / I conversion circuit 13a, and 27 is
This is a circuit corresponding to the V / I conversion circuit 14a. 28 corresponds to the operational amplifier 1.

Here, the attenuation control of the input signal can be performed by selectively setting the value of the current value IA of the current source 26a of the V / I conversion circuit 26,
By selectively setting the value of the current value IB of the current source 27a of the V / I conversion circuit 27, the emphasis control of the input signal can be performed. When the current values IA and IB are set to zero, an output having flat characteristics is obtained. Therefore, the DC control can attenuate or enhance the input signal.

As described above, in the embodiment, the V / I conversion circuits 13a, 1
Although only one of 4a is operated selectively,
These V / I conversion circuits may be differentially controlled by the control circuit 15. For example, the conversion conductance of the V / I conversion circuit 13a is (1-a) · gm, and the V / I conversion circuit 14a is (1 + a )
・ If gm, this a is determined by the volume 16 so that 1 ≧ a
Control may be performed as ≧ −1. In this case, a =
When the midpoint is set to 0, the operation of the V / I conversion circuits 13a and 14a can be stopped.

In the embodiment, the voltage / current conversion rates of the V / I conversion circuits 11, 13a, and 14a are set to the same value or K × K, but they need not always be the same. Further, the load resistance RL and the feedback resistance _{R0 of the} operational amplifier 1 have the same value, but they need not have the same value. For example, if the value of K of the V / I conversion circuits 13a and 14a is set to 2K and doubled, the load resistance RL can be set to 1/2 of the value of the feedback resistance _R0 , that is, RL / 2. Alternatively, the value of K of the V / I conversion circuits 13a and 14a can be set to different values. V / I conversion circuit 11 accordingly
And the value of the load resistance RL can be various values.

[Effects of the Invention] As can be understood from the above description, the present invention has a configuration in which the input side is a V / I conversion circuit and a resistor is not inserted in series with the input of the amplifier. Therefore, there is a degree of freedom in setting the input bias and the like, and a sufficient dynamic range can be secured. In addition, since direct control is used instead of direct control using a volume control, a circuit suitable for use in an IC and having a large S / N ratio can be obtained. As a result, a graphic equalizer circuit having a small number of pins and easy to miniaturize can be realized.

The operational amplifier inserted as an output of the graphic equalizer circuit has a first input and a second input having an opposite phase to the first input, that is, a (+) phase input and a (−) phase input. Since there is a short-circuit relationship, the equalized signal applied to the (-) phase input is equivalently added (subtracted because the phase is different, at the load resistor terminal) via the (+) phase input side. Will be. This results in all equalized input signals occurring at the terminals of the load resistor. Since the other terminal of the load resistor is connected to the reference bias line, all equalized signals are superimposed at the reference bias point. As a result, the fluctuation of the reference level is small, the S / N ratio is improved, and the dynamic range can be increased.

[Brief description of the drawings]

FIG. 1 is a basic block diagram of a graphic equalizer circuit to which the present invention is applied, FIG. 2 is a specific circuit diagram thereof, and FIGS. 3 (a) and 3 (b) are diagrams of a conventional graphic equalizer circuit. FIG. 1,28 operational amplifier, 2,16 volume, 3 series resonance circuit, 4, 5, 11, 13a, 14a V / I conversion circuit, 15 control circuit, 22 bandpass filter.

Claims (1)

(57) [Claims] 1. A first voltage-current conversion circuit receiving an input signal, an active filter receiving the output, and a load inserted between an output of the first voltage-current conversion circuit and a reference bias voltage line. A resistor and a voltage generated by the output generated at the load resistor are received at a first input, and an output is fed back to a second input of a phase opposite to the phase of the first input via a feedback resistor. An amplifier, an output side connected to a terminal side of the load resistor for generating a voltage based on the output, having a first variable current source, receiving an output of the active filter, and changing a current value of the first variable current source; A second voltage-current conversion circuit whose gain is controlled in accordance with the second filter, a second variable current source, an output side of which is connected to a second input side of the operational amplifier; Second variable current source Third voltage gain according to the current value is controlled - and a current conversion circuit, the graphic equalizer circuit current value of the first and second variable current source is being controlled from the outside.