JP2751703B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a dynamic random access memory device (hereinafter, referred to as DRAM).

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional DRAM has a memory cell comprising switching transistors 2, 3 and capacitors 4, 5, and a data signal line 101, 1.
02 is amplified by a sense amplifier. The word lines 201 and 202 control the gates of the switching transistors 2 and 3 and use the data bits stored as charges in the capacitors 4 and 5 as a voltage difference to generate data signal lines 101 and 1.
02 is read. The other ends of the data signal lines 101 and 102 are connected to a precharge level supply line 401 via Nch transistors 7, 8, and 9 to set the precharge level.

The word lines 201 and 202 are selected by a decoder 11 and supplied with a voltage raised by a booster circuit 12.

[0004]

However, in general, in a DRAM, the potential charged in the capacitor is VCC-VT (VCC: power supply voltage, V CC) when the word line is set to a high level.
T: the threshold value of the Nch transistor). To charge the potential of this capacitor to the power supply level as shown in FIG. 6, the word lines 201 and 202 are boosted to the power supply voltage or more (for example, VCC + VT or more). In order to realize this, it is necessary to provide the word line booster circuit 12. As a result, there is a problem that the circuit configuration of the DRAM becomes complicated.

[0005]

SUMMARY OF THE INVENTION The gist of the present invention is to provide a data line pair, a precharge circuit for precharging the data line pair, a cell transistor and a cell capacitor, and to generate a difference voltage between the data line pair. A memory cell, a sense amplifier that amplifies a difference voltage on the data line pair, a transfer gate connected between the data line pair and the sense amplifier,
In a semiconductor memory device having a word line for controlling a gate of a cell transistor, one of the pair of electrodes of the cell capacitor can be connected to one of a pair of data lines via a cell transistor, and the other electrode is connected to a data electrode. That is, it is connected to the other of the line pairs.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

First, the configuration of the first embodiment will be described. The input / output terminal of the sense amplifier 1 is Nch for a transfer gate.
The gates of the transfer gate transistors 9 and 10 are connected to a transfer gate control signal line 301. The sources of the Nch transistors 9 and 10 are connected to data lines 101 and 102, respectively. On the other hand, the other end of the data line 101 is connected to the drains of the Nch transistors 6 and 8,
The other end of the data line 102 is connected to the drain and source of the Nch transistors 7 and 8.
The gates of Nch transistors 6 to 8 are connected to data line balance signal line 401. Further Nc
The sources and drains of the h transistors 6 and 7 are connected to a precharge level supply line 501.

[0008] The word line 201 is connected to the gate of the cell transistor 2. The drain of the cell transistor 2 is connected to the data line 101, and the drain is connected to one end of the cell capacitor 4. The other end of the cell capacitor 4 is connected to the data line 102. On the other hand, the same applies to the word line 202, in which the gate of the cell transistor 3 is the word line 202, the source is the data line 102,
The drain is connected to one end of the cell capacitance 5, and the other end of the cell capacitance 5 is connected to the data line 101. Word line 20
1, 202 is selected by the decoder 11. A cell array is composed of a plurality of word line pairs for one sense amplifier 1 with a circuit including two word lines 201 and 202 each having a 1-bit cell on each of the data lines 101 and 102.

Next, the operation of the first embodiment will be described. As shown in FIG. 1, in the present embodiment, the counter electrodes of the cell capacitors 4 and 5 are connected to the pair of data lines 101 and 102, as shown in FIGS. Next, the data lines 101 and 102 are driven. That is, FIG. 4 shows a case where the cell capacities 4 and 5 are high-level data, and FIG. 5 shows a case where the cell capacities are low-level data. As shown in FIG. 4, when the word line 201 rises, the cell transistor 2
Turns on, and the potential difference between the data line 101 and the data line 102 is shown in detail. The sense amplifier 1 amplifies the data lines 101 and 102 to the power supply voltage and 0 V (GND), respectively, by the difference potential. As a result, the potential difference between the two poles of the cell capacitor 4 becomes VCC-0 = VCC.

Next, the word line 201 is lowered, and the data lines 101 and 102 are balanced by the balance Nch transistor 6-8 to have a voltage of 1/2 VCC. At this time, the counter electrode of the cell capacitor 4 changes from 0 to 1/2 VCC, and the potential charged in the cell is VCC-VT + 1 / 2VC.
The voltage is boosted to C = 3/2 VCC-VT. This is the restore level.

FIG. 2 shows a second embodiment of the present invention.
In the second embodiment, the transfer gate control signal 301,
302. As shown in FIG. 7, by controlling these two lines, a circuit that eliminates the drawback that the counter electrode of the cell capacitor 4 moves with the amplification when amplifying the difference potential and delays the sense speed is achieved. is there.

As shown in FIG. 4, when amplifying the high-level data of the cell capacitor 4, the data line 102 falls from 1/2 VCC to GND. Along with this, the cell capacitor 4 pulls the data line 101 to the GND side, thereby delaying the sensing speed. By lowering the data line 102 to a low level in the transfer gate control signal column 301 as shown in FIG.
To increase the sense speed.

[0013]

As described above, by connecting the opposite electrode of the cell capacitance to a pair of data lines, both electrodes of the cell capacitance are charged at the level of the data line amplified by the sense amplifier when the sense amplifier is activated. Is done. When the data line is balanced after the word line is lowered, the opposite electrode of the capacitance becomes 1/2 Vcc. When the cell level is high, the voltage is boosted, and when the cell level is low, the voltage is lowered and charged. This eliminates the need for a word line boosting circuit for increasing the efficiency of charging the conventional cell, and has the effect of simplifying the circuit configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment.

FIG. 2 is a circuit diagram of a second embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a waveform chart showing a voltage waveform of the first embodiment.

FIG. 5 is a waveform chart showing a voltage waveform of the first embodiment.

FIG. 6 is a waveform diagram showing a voltage waveform of a conventional example.

FIG. 7 is a waveform diagram showing a voltage waveform of the second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sense amplifier 2, 3 Cell transistor 4, 5 Cell capacitance 6, 7 Precharge transistor 8 Balance transistor 101, 102 Data signal line 201, 202 Word line 301 Transfer gate control line

Claims (3)

(57) [Claims] 1. A data line pair, a precharge circuit for precharging a data line pair, a memory cell including a cell transistor and a cell capacitor for generating a difference voltage between the data line pair, and a difference between the data line pair. In a semiconductor memory device provided with a sense amplifier for amplifying a voltage, a transfer gate connected between a data line pair and a sense amplifier, and a word line for controlling a gate of a cell transistor, a pair of the cell capacitances is provided. A semiconductor memory device, wherein one of the electrodes is connectable to one of a pair of data lines via a cell transistor, and the other electrode is connected to the other of the pair of data lines. 2. The word line rises to a power supply voltage at the time of selection, and a difference voltage generated in a data line pair is returned to a cell capacitance expanded to a power supply voltage and a ground potential by a sense amplifier via a transfer gate, 2. The semiconductor memory device according to claim 1, wherein when precharging the data line pair after lowering the voltage of the word line, the voltage of one electrode of the cell capacitor is boosted. 3. The transfer gate comprises a pair of transfer transistors interposed between a data line pair and a sense amplifier, wherein the pair of transfer transistors are independently controlled by a pair of control lines, During the differential amplification of the sense amplifier,
2. The semiconductor memory device according to claim 1, wherein the other electrode is cut off from the sense amplifier.