JP2752288B2 - Digital video camera - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video camera, and more particularly to a digital video camera which converts an output signal from a CCD having, for example, a mosaic type color filter into a digital signal by an A / D converter and processes the digital signal.

[0002]

2. Description of the Related Art In general, a consumer video camera uses a CCD provided with a mosaic type color filter as shown in FIG. The CCD outputs signals as shown in FIGS. 6B and 6C. This signal is passed through a correlated double sampling circuit and AGC circuit to A / D
It is converted to a digital signal by a converter.

When a high-luminance uniform subject is photographed by such a video camera, horizontal stripes having periodicity occur. This is because when a high luminance signal is input, A
This is because a signal exceeding the dynamic range of the / D converter is generated. More specifically, R = 10, G = 5
Assuming a uniform image such as B and B = 5, the level of the signal output from the CCD at this time is as shown in FIG.
It becomes like 1). At this time, if the levels of all the pixels do not exceed the dynamic range of the A / D converter, that is, if the dynamic range of the A / D converter is "3"
If it is "0" or more, the level of the converted digital signal is kept as it is. Since the luminance signal is obtained by the weighted average of the adjacent pixels, a uniform luminance signal is obtained as shown in FIG.

[0004]

However, in the above case, the dynamic range of the A / D converter is "25".
, The level of the converted digital signal is as shown in FIG.
-3). For this reason, the luminance signal is shown in FIG.
As shown in 4), a luminance difference occurs for each line. This brightness difference is further emphasized by the vertical aperture signal,
Therefore, periodic horizontal stripes are generated on the screen.

Therefore, a main object of the present invention is to provide a digital video camera capable of suppressing horizontal stripes.

[0006]

[Means for Solving the Problems] The output signal from the CCD is
It is converted to a digital video signal by an A / D converter,
A vertical aperture signal based on the digital video signal
A vertical aperture signal generating circuit,
Subtract predetermined threshold value from luminance signal separated from video signal
A plurality of bits receiving an output of the subtraction circuit.
Shift circuit, output of the plurality of bit shift circuits
A first selection circuit for selecting and outputting the first selection circuit;
An inverting circuit for inverting the output of the circuit, and an output of the inverting circuit.
Receiving a force and a predetermined constant, the borrow signal from the subtraction circuit.
And a second selection circuit that outputs one according to the signal.
A suppression gain calculating circuit, and a circuit for generating the vertical aperture signal.
Multiplying the output of the path by the output of the suppression gain calculation circuit
A multiplying circuit, and the dynamic level of the A / D converter is
When a luminance signal exceeding the
Characterized in that the level of the
Digital video camera.

[0007]

The changing means, for example, does not change the level of the vertical aperture signal when the luminance signal is smaller than a predetermined threshold, and reduces the level of the vertical aperture signal at a rate corresponding to the level of the luminance signal when the level is higher than the threshold. I do. As a result, only the signals of some pixels are A / D
Suppress horizontal stripes that occur when the dynamic range of the converter is exceeded.

[0008]

According to the present invention, even if there is a signal exceeding the dynamic range of the A / D converter, generation of horizontal stripes can be suppressed. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital video camera 10 of this embodiment shown in FIG.
It includes an A / D converter 12 received through a double sampling circuit and an AGC circuit. The digital video signal from the A / D converter 12 is applied to a vertical aperture signal generation circuit 14. The vertical aperture signal generating circuit 14 is configured, for example, as shown in FIG. 2 and generates a vertical aperture signal (a second-order differential signal in the vertical direction) as shown in FIG. Then, the vertical aperture signal is provided as one input of the multiplication circuit 16. Further, the Y signal (luminance signal) separated from the digital video signal from the A / D converter 12 is supplied to the suppression gain calculation circuit 18. The suppression gain calculation circuit 18 further includes a CPU 20
Threshold data TH and selection signal K are provided. In brief, the suppression gain calculating circuit 18 determines that the Y signal is CP
When the threshold value TH set by U20 is exceeded, a gain for reducing (suppressing) the level of the vertical aperture signal is calculated, and the calculated gain is applied to the other input of the above-described multiplication circuit 16. Therefore, the output vertical aperture signal corrected by the gain from the suppression gain calculation circuit 18 is obtained from the multiplication circuit 16.

The vertical aperture signal generating circuit 14 shown in detail in FIG. 2 includes an adder circuit 22 which receives a digital video signal from the A / D converter 12 at one input, and the digital video signal is provided by two 1H delay circuits. 24 and 26
And is applied to the other input of the adder circuit 22. The output of the adder circuit 22 is supplied to a subtraction input of a subtraction circuit 30 via a 1/2 circuit 28.
A digital video signal is provided through the step 4. Subtraction circuit 3
The output of 0 is output after being "× k" times more by the time constant circuit 32.

A vertical aperture signal generating circuit 1 shown in FIG.
The operation of No. 4 can be easily understood by referring to the waveform diagram shown in FIG. 3, and the detailed description thereof is omitted here. From the multiplication circuit 32 shown in FIG.
The vertical aperture signal shown in (f) is output, and is provided as one input of the multiplication circuit 16 described above. Also,
4 includes a subtraction circuit 36 for subtracting a threshold value TH set by the CPU 20 from the luminance signal. The output from the subtraction circuit 36 is supplied to the selection circuit 38 as it is and to the bit shift circuits 40, 42 and 44. The bit shift circuit 40 is a circuit for up-shifting the output of the subtraction circuit 36 by one bit and "doubling" the output. The bit shift circuits 42 and 44
Are up-shifted by 2 bits and 3 bits, respectively, to "4 times" and "8 times", respectively. The outputs of bit shift circuits 40-44 are also applied to selection circuit 38.

The upper one bit of the output from the subtraction circuit 36 is supplied to the selection circuit 48, and the upper two bits are output to the OR gate 4.
6a, and is supplied to the selection circuit 48 through the OR gate 46b.
The selection circuit 48 is further provided with “0”.
The 8-bit signal selected by the selection circuit 38 is supplied to the OR gate 50 together with the 1-bit signal selected by the selection circuit 48. The OR gate 50 functions as an overflow clip circuit, and the signal from the selection circuit 38 exceeds “255”.
This prevents the suppression gain output from 8 from becoming a negative value. This is because, if a negative value is handled, the number of processing bits increases by one. The output of the OR gate 50 is supplied to the upper input of the selection circuit 54 via the inversion circuit 52. A constant ("255" in this embodiment) is given to the lower input of the selection circuit 54. The selection circuit 54 selects the upper input, that is, the output of the inversion circuit 52, when the borrow signal of “1” is output from the subtraction circuit 36, and selects the lower input, that is, “255” when it is “0”.
Select

In the subtraction circuit 36 shown in FIG. 4, if the level of the luminance signal is "X", "X-TH" is obtained. This "X-TH" is used as it is or the bit shift circuit 4
The signal is supplied to the selection circuit 38 via 0-44. The selection circuit 38 is supplied with a selection circuit (2 bits) from the CPU 20. When the selection signal K is set to “00”, the selection circuit 38 outputs “X−
TH ”is output as it is. When the selection signal K is “0”
When given as “1”, the selection circuit 38 selectively outputs “2 (X−TH)” output from the bit shift circuit 40. When the selection signal K is set as “10”, the selection circuit 38 outputs “4 (X−TH)” output from the bit shift circuit 42, and when the selection signal K is set as “11”, the selection circuit 38 38 is a bit shift circuit 44
Is output as "8 (X-TH)". Therefore, “k (X−TH)” is output from the selection circuit 38. Since the output from the selection circuit 38 is inverted by the inversion circuit 52 through the OR gate 50,
As a result, the output of the inverting circuit 52 becomes "255-k (X
-TH) ". Then, the selection circuit 54 selects the upper input when there is a borrow signal of “1” from the subtraction circuit 36 and selects the lower input when it is “0”. ) Are as shown in FIG. That is, when the luminance signal level (X) exceeds the threshold value TH, a suppression gain that continuously decreases according to the level is output. Therefore, the level of the vertical aperture signal is not changed until the level of the luminance signal exceeds a predetermined threshold, but when the level exceeds the threshold, the level of the vertical aperture signal is gradually reduced according to the luminance signal level. Therefore, this threshold TH is set to A /
By setting in consideration of the dynamic range of the D converter 12, horizontal stripes that occur when there is a signal exceeding the dynamic range can be suppressed.

In FIG. 5, the gradient when the threshold value is exceeded is determined by the selection signal K output from the CPU 20 (FIG. 1). Therefore, this selection signal (gradient coefficient)
By changing and setting K as appropriate by the CPU 20,
The image quality can be adjusted more finely. in this way,
According to the embodiment of FIG. 1, by changing the level of the vertical aperture signal, it is possible to suppress the horizontal stripes of the image caused by the dynamic range of the A / D converter 12 without changing the level of the luminance signal itself. can do. This is because the gain in the high-level portion is compressed by the correction characteristics of the subsequent gamma correction circuit (not shown), so that even if there is a slight level difference, the horizontal stripes are not so conspicuous. Because the signal emphasizes the contours,
As a result, horizontal stripes become conspicuous. However, if the gain of the vertical aperture signal is reduced in the high-level portion as described above, the degree of emphasis by the vertical aperture signal decreases, and the horizontal stripes become inconspicuous in combination with the gamma correction characteristics.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a vertical aperture signal generation circuit of the embodiment in FIG. 1 in detail;

FIG. 3 is a waveform diagram showing an operation of the vertical aperture signal generation circuit of FIG. 2;

FIG. 4 is a block diagram showing in detail a suppression gain calculation circuit of the embodiment in FIG. 1;

FIG. 5 is a graph showing a gain output from a suppression gain calculating circuit according to a level of a luminance signal according to the embodiment.

FIG. 6 shows a mosaic type color filter and a CC having the same.
FIG. 4 is an illustrative view showing a signal output from D.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Digital video camera 12 ... A / D converter 14 ... Vertical aperture signal generation circuit 16 ... Multiplication circuit 18 ... Suppression gain calculation circuit 20 ... CPU

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Seiji Kawakami 2--18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Masao Takuma 2--18 Keihanhondori, Moriguchi-shi, Osaka (56) References JP-A-4-45686 (JP, A) JP-A-4-145792 (JP, A) JP-A-63-269873 (JP, A) (58) Fields investigated (Int.Cl. ⁶ , DB name) H04N 5/225-5/243 H04N 9/04-9/09 H04N 9/68 103

Claims (1)

(57) [Claims] An output signal from a CCD is supplied to an A / D converter.
Is converted to a digital video signal.
Vertical aperture that generates a vertical aperture signal based on the signal
And a luminance signal separated from the digital video signal.
A subtraction circuit for subtracting a predetermined threshold value, and receiving an output of the subtraction circuit.
Bit shift circuits, the plurality of bit shifts
A first selection circuit that selects and outputs one of circuit outputs;
An inverting circuit for inverting an output of the first selecting circuit;
Receiving the output of the inverting circuit and a predetermined constant,
Selection to output one according to the borrow signal from
And an output of the vertical aperture signal generation circuit and the suppression gain calculation circuit.
A multiplication circuit for multiplying the output of the A / D converter by a luminance signal exceeding the dynamic range of the A / D converter.
Signal is input, the level of the vertical aperture signal is changed.
Digital video camera characterized by being reduced
La.