JP2753789B2 - Manufacturing method of capacitive element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitance element used in a semiconductor device such as an integrated circuit, and more particularly to a method of manufacturing a capacitance element which can be easily formed without burdening a process in a multilayer wiring process. Things.

[0002]

2. Description of the Related Art When manufacturing a semiconductor integrated circuit, it is desired that a resistance element and a capacitance element can be easily manufactured.
In particular, in an analog circuit, a capacitor is indispensable. Conventionally, a capacitor has been manufactured by forming an insulating film on a polysilicon electrode and forming an electrode wiring thereon. In this case, the reason for manufacturing on polysilicon is
This is because an insulating film can be formed by high-temperature thermal CVD on polysilicon.

However, in recent years, in a method of manufacturing a semiconductor integrated circuit, high integration has progressed, and a multi-layer wiring step has become indispensable in the process. Therefore, if it can be easily formed in a multilayer wiring process, it goes without saying that there are many advantages in process and circuit design. However, it is impossible to form a high-quality insulating film at a low temperature on electrode wiring, particularly aluminum-based wiring, and even if deposited, forming a thick film covers poor film quality. Is the actual situation. In this case, it is needless to say that a large capacitance area is indispensable to obtain a desired capacitance value, and it is clear that this is an obstacle to high integration.

FIG. 5 shows current-voltage characteristics of an insulating film used in a wiring process. FIG. 5 shows characteristics 12 to 14 when the insulating film is formed at 500 [deg.] By CVD, ozone TEOS (tetraethoxysilane), and plasma TEOSCVD, respectively. In each case, the substrate heating temperature is 400 ° C., which is the limit temperature in the aluminum-based multilayer wiring process. The current-voltage characteristics were obtained by examining the current characteristics when a reverse voltage was applied in a MIS structure in which various insulating films were formed on a silicon substrate and metal electrodes were provided thereon. A large value means that the insulating properties of the insulating film are poor. FIG.
Thus, the electric field strength is on the order of several μA / cm ² at an electric field strength of 3 megavolts, and a smaller electric current value at a higher electric field strength is desired for the insulating film. The current-voltage characteristic is on a silicon substrate, and if it is on a metal, it is apparent that the characteristic is further degraded in consideration of surface roughness and the like.

[0005]

That is, in the case of an insulating film used in the current wiring process, it is impossible to form a thin insulating film on a metal and manufacture a capacitive element based on this.

The present invention has been made in view of such circumstances, and an object of the present invention is to form a high-quality thin insulating film on a electrode wiring by a bias ECR plasma CVD method in a multi-layer wiring process. Another object of the present invention is to provide a method for easily forming a capacitor without imposing a burden on circuit design.

[0007]

In order to achieve the above object, the present invention provides a method for forming a first electrode wiring layer, forming an interlayer insulating film, and forming a capacitor at a desired position on the first electrode wiring layer. In the step of removing the interlayer insulating film for forming an element, the interlayer insulating film is etched by tapering to form a tapered opening. Then, a SiO ₂ film for a capacitor is formed thereon by a bias ECR plasma CVD method at a temperature of 200 ° C. or less , and a second electrode wiring layer is formed after opening a through hole for interlayer connection. It is characterized in that a part of the second electrode wiring layer is electrically separated and a capacitor is formed using the second electrode wiring layer as one electrode.

[0008]

According to the present invention, a capacitance element can be easily formed only by increasing the number of steps of forming a capacitance element portion and an insulating film after forming a normal interlayer insulating film in a multilayer wiring process. In addition, by performing taper processing on the opening for the capacitor element, deterioration of the insulating film at the step is eliminated, and the thickness of the insulating film can be formed as thin as 2000 mm or less, so that there are very few process problems. A desired capacitance element can be realized.

[0009]

FIG. 1 is a sectional view of a main process for explaining an embodiment of the present invention. In FIG. 1A, reference numerals 1 and 3 denote respective interlayer insulating films, and reference numeral 2 denotes an electrode wiring layer. After a first electrode wiring layer 2 is selectively formed on a lower interlayer insulating film 1, it is formed thereon. Then, an interlayer insulating film 3 is formed by lamination. In this embodiment, the interlayer insulating films 1 and 3 are formed to have a thickness of 5000 ° by the CVD method. The electrode wiring layer 2 was formed by depositing Al (Si) at a thickness of 5000 ° by a sputtering method.

Next, referring to FIG. 1B, after the step of FIG. 1A, the interlayer insulating film 3 is etched by a taper process to form a capacitive element at a desired position on the first electrode wiring layer 2. A capacitor element region 4 is formed, and then an insulating film 5 for the capacitor element is formed thereon. That is, the capacitive element portion 4 is patterned and the interlayer insulating film 3 is etched by dry etching until the surface of Al (Si) as the electrode wiring layer 2 is exposed. In this etching step, taper etching is performed to form a tapered opening 6. Next, on the interlayer insulating film 3 including the opening 6, SiO _{2 is} formed as an insulating film 5 for a capacitor by a bias ECR plasma CVD method.
Form a film. In this embodiment, this SiO ₂ film 5
It was formed with a thickness of not more than 00 °.

However, it goes without saying that the thickness of the SiO ₂ film 5 for the capacitor element may be determined as long as it is possible from the viewpoint of the wiring process, reliability and yield. In general, a thinner one can obtain a larger capacitance in the same capacitance area. However, a thin film thickness may cause yield and reliability problems. On the other hand, a thick film may hinder the processing of the next through hole and the like. In this embodiment, the maximum film thickness was set to 2000 °.

Now, here, the bias ECR plasma C
The features of the VD method will be described. The method generates a plasma using electron cyclotron resonance method is a method for performing planarization and quality improved by applying sputter etching rf bias to the substrate holder to form a thin film, the gas pressure of 10 ^-5 to 10 ^{Since a} high quality thin film is formed at a low pressure of ⁻³ Torr and a low temperature of 200 ° C. or less , the lower layer
The insulating film 5 even if the electrode wiring layer 2 made of Al
Can be formed .

FIG. 2 shows this bias ECR plasma CV.
The current-voltage characteristics of the MIS diode are shown by comparing the SiO ₂ film formed by the method D with the above-mentioned normal SiO ₂ film (see FIG. 5), and reference numeral 11 denotes the SiO ₂ film according to the present embodiment. The characteristic (ECR) of
2 to 14 are characteristics of a normal SiO ₂ film (CVD, O ₃ TEO).
S, PTEOS). The thickness of all SiO ₂ films is 500 °. 2, the SiO ₂ film formed by the bias ECR plasma CVD method (characteristic 11)
It can be seen that the sample shows excellent insulating characteristics as compared with other insulating films (characteristics 12 to 14).

At this time, in this embodiment, an SiO ₂ film was formed under the conditions of microwave power of 700 W, rf power of 200 W, gas pressure of 1.0 mTorr using SiH ₄ and O ₂ . Under this condition, the rf power is applied, but since a high quality SiO ₂ film can be obtained without applying the rf power, the application of the rf power depends on the process. Further, when a film is formed by the bias ECR plasma CVD method, there is a disadvantage that the step side wall is thinner than the flat surface and the film quality is poor.

[0015] However, the present inventors have conducted various experiments in order to solve such a disadvantage, and as shown in FIG.
Assuming that the inclination angle (taper angle) of the opening 6 of the interlayer insulating film 3, that is, the step, is θ, it is found that the film quality can be improved if the inclination angle θ is 75 degrees or less. In this case, in this embodiment, taper etching is performed in the etching step of the opening 6 of the capacitive element portion, and the inclination angle θ is 6
0 degrees.

In this manner, the Si
After the O ₂ film 5 is formed, and then the through-hole opening step is performed, a second electrode wiring layer 7 is formed, thereby realizing a multilayer wiring and forming the capacitive element 8 as shown in FIG. be able to. That is, an SiO ₂ film 5 for a capacitive element is formed on an interlayer insulating film 3 having a tapered opening 6, a through hole for interlayer connection is patterned, and SiO ₂ is removed by dry etching to form an interlayer connection. Forming through hole portion 9 is formed. Then the second
After aluminum alloy Al (Si) is deposited at 5000 ° by a sputtering method as the electrode wiring layer 7, it is processed to form a part of the second electrode wiring layer 7 together with the multilayer wiring and the upper electrode 7.
This realizes the capacitive element 8 designated as “a”.

The characteristics of the capacitor manufactured in this embodiment will be described below. Bias film thickness of SiO _2, that ECR-SiO ₂ film formed by ECR plasma CVD method exhibits a leakage current yield characteristics when 1500Å in FIG.
FIG. 4 shows a comparison between the taper processing and the vertical processing. The solid line characteristic 21 indicates the case of taper etching, and the broken line characteristic 22 indicates the case of vertical etching. As is clear from the figure, 100% yield can be obtained even when 7 V is applied when taper processing is performed. However, in the case of vertical etching, the yield decreases as the applied voltage increases. That is, the ECR-SiO ₂ film 5 on the step side wall is formed by tapering the opening 6 of the capacitive element portion 4.
It is considered that the film quality has been improved and the withstand voltage has been improved, and at the same time the yield has been improved.

Thus, in the present invention, the bias ECR
In a capacitive element using a plasma CVD method, deterioration of an insulating film in a step portion can be prevented by tapering an opening in an element forming region, and a capacitive element having favorable characteristics can be realized. .

In the above-described embodiment, the case where the SiO ₂ film formed by the bias ECR plasma CVD method is used as the insulating film for the capacitance element has been described. However, the present invention is not limited to this. The same effect can be obtained by using a silicon nitride film or oxynitride that can be formed by the same ECR plasma CVD method.

[0020]

As described above, according to the present invention, an SiO ₂ film formed at a temperature of 200 ° C. or less by a bias ECR plasma CVD method is used as an insulating film of a capacitive element. By subjecting the opening to taper processing, deterioration of the SiO ₂ film at the step is eliminated. Therefore, the taper opening process of the capacitor element portion and the deposition process of the capacitor insulating film (SiO ₂ film) only increase in the multilayer wiring process, and the process is very easy. It is possible to provide a high-reliability, high-yield capacitive element.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main process for explaining an embodiment of the present invention.

FIG. 2 is a diagram showing current-voltage characteristics of a SiO2 film formed by a bias ECR plasma CVD method of the present embodiment and a normal insulating film in comparison.

FIG. 3 is an explanatory diagram of the present embodiment.

FIG. 4 is a diagram showing a leak characteristic of a capacitor obtained according to the present embodiment.

FIG. 5 is a diagram showing current-voltage characteristics of ordinary various insulating films.

[Explanation of symbols]

1, 3 interlayer insulating film 2 first electrode wiring layer 4 region of capacitive element 5 insulating film for capacitor (SiO ₂ film) 6 opening for capacitive element 7 second electrode wiring layer 8 capacitive element 9 interlayer connection Through hole for

Claims (1)

(57) [Claims] In a step of forming an interlayer insulating film after forming a first electrode wiring layer and removing the interlayer insulating film to form a capacitor at a desired position on the first electrode wiring layer, The interlayer insulating film is etched by a taper process to form a tapered opening, and then a SiO ₂ film for a capacitor is formed thereon at a temperature of 200 ° C. or less by a bias ECR plasma CVD method. Forming a second electrode wiring layer after opening of a through hole for use, electrically separating a part of the second electrode wiring layer and forming a capacitive element by using it as one electrode. A method for manufacturing a capacitive element, comprising: