JP2754764B2 - Hybrid integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit, and more particularly to a configuration of an inductance element of a hybrid integrated circuit.

[Conventional technology]

The inductance part of the conventional hybrid integrated circuit is composed of only the conductor layer 11 formed on the upper surface or the lower surface of the insulating substrate 1 as shown in the plan view of FIG.
Alternatively, as shown in the sectional view of FIG. 3B, a discrete component 12 such as a coil is provided between a conductor layer 11a and a conductor layer 11a independently formed on the upper or lower surface of the insulating substrate 1.
Are connected by a solder 13.

[Problems to be solved by the invention]

When the inductance portion of the conventional hybrid integrated circuit described above is formed only of the conductor layer pattern, it is necessary to increase the area occupied by the pattern in order to obtain a relatively large inductance. There is a disadvantage that it causes inconvenience in measuring.

Further, when the inductance portion is formed by discrete components such as coils, the thickness or height of the device is limited by the thickness of the discrete component used, and there is a drawback that the thickness of the device is disadvantageously reduced.

[Means for solving the problem]

The hybrid integrated circuit of the present invention has a plurality of first conductor layers and at least one second conductor layer independently formed on an upper surface of an insulating substrate, and the insulating substrate has a plurality of through holes (through holes). A third conductor layer is formed in each through hole, and a first conductor layer and a second conductor layer are formed on the lower surface of the insulating substrate via the third conductor layer formed in the through hole. There is a plurality of inductance units configured to be electrically connected to the fourth conductor layer, and the first conductor layer and the second conductor layer of the plurality of inductance units are formed on the upper surface of the insulating substrate by metal wires as necessary. Thus, an inductance portion is formed by bonding.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a view of a first embodiment of the present invention, FIG. 1 (a) is a plan view of an upper surface of an insulating substrate, FIG. 1 (b) is a plan view of a lower surface of the insulating substrate, FIG. FIG. 1 (c) is a cross-sectional view taken along the line AA 'in FIGS. 1 (a) and 1 (b).

A plurality of first conductor layers 2, 2a, 2b and a plurality of second conductor layers 3, 3a, 3b each having a thickness of about 12 μm are formed on an upper surface of an alumina insulating substrate 1 having a thickness of 0.635 mm. On the lower surface of the insulating substrate 1, a plurality of fourth conductor layers 4, 4a, 4b having a thickness of about 12 μm are provided.
Are formed.

The insulating substrate 1 has a plurality of through holes 5, 5a, 5b, 6, 6a, 6b (through holes) each having a diameter of 0.3 mm.
Conductor layers 2, 2a, 2b and fourth conductor layers 4, 4a, 4b and second conductor layers 3, 3a, 3b and fourth conductor layers 4, 4a, 4b
Electrical conduction is provided by third conductor layers 7, 7a, 7b and third conductor layers 8, 8a, 8b formed on the inner walls of a, 5b and through holes 6, 6a, 6b.

In this embodiment, on the upper surface of the insulating substrate 1, the first conductor layer 2a and the second conductor layer 3 and the first conductor layer 2b and the second conductor layer 3a are formed by the gold wire 9 and the gold wire 9a having a diameter of 30 μm. They are electrically connected by bonding.

With the above configuration, in the present embodiment, each of the conductor layers is defined as the first conductor layer 2, the third conductor layer 7, the fourth conductor layer 4, the third conductor layer 8,
The second conductor layer 3, the gold wire 9, the first conductor layer 2a, the third conductor layer 7a,
Fourth conductor layer 4a, third conductor layer 8a, second conductor layer 3a, gold wire 9
a, the first conductor layer 2b, the third conductor layer 7b, the fourth conductor layer 4b, the third conductor layer 8b, and the second conductor layer 3b are connected in this order to realize an inductance portion. .

FIG. 2 is a view of a second embodiment of the present invention. FIG. 2 (a) is a plan view of the upper surface of the insulating substrate, and FIG. 2 (b) is a line BB 'in FIG. 2 (a). FIG.

In the present embodiment, a plurality of first conductor layers 2, 2a, 2b and a plurality of second conductor layers 3, 3a, 3b having a thickness of about 12 μm are formed on an upper surface of an insulating substrate 1 made of alumina having a thickness of 0.635 mm. 3b is formed,
Further, the ferrite member 10 is fixed with an adhesive such as a resin. On the other hand, a plurality of fourth conductor layers 4, 4a, 4b each having a thickness of about 12 μm are formed on the lower surface of the insulating substrate 1.

The insulating substrate 1 has a plurality of through holes 5, 5a, 5b, 6, 6a, 6b (through holes) each having a diameter of 0.3 mm.
Conductor layers 2, 2a, 2b and fourth conductor layers 4, 4a, 4b and second conductor layers 3, 3a, 3b and fourth conductor layers 4, 4a, 4b
Electrical conduction is provided by third conductor layers 7, 7a, 7b and third conductor layers 8, 8a, 8b formed on the inner walls of a, 5b and through holes 6, 6a, 6b.

In this embodiment, on the upper surface of the insulating substrate 1, the first conductor layer 2a and the second conductor layer 3 and the first conductor layer 2b and the second conductor layer 3a are formed by the gold wire 9 and the gold wire 9a having a diameter of 30 μm. They are electrically connected by bonding.

With the above configuration, in the present embodiment, each of the conductor layers is defined as the first conductor layer 2, the third conductor layer 7, the fourth conductor layer 4, the third conductor layer 8,
The second conductor layer 3, the gold wire 9, the first conductor layer 2a, the third conductor layer 7a,
Fourth conductor layer 4a, third conductor layer 8a, second conductor layer 3a, gold wire 9
a, the first conductor layer 2b, the third conductor layer 7b, the fourth conductor layer 4b, the third conductor layer 8b, and the second conductor layer 3b are connected in this order to form a coil. The ferrite member 10 realizes an inductance part.

The inductance part of the present embodiment has the same effect as an inductance coil with a ferrite core used for preventing transmission of an electric circuit.

〔The invention's effect〕

As described above, according to the present invention, the inductance circuit is configured by the conductor patterns on the upper and lower surfaces of the insulating substrate, the metal wires, and the inner wall conductors of the through holes. It can be reduced below.

In addition, the thickness of the device composed of the hybrid integrated circuit can be drastically reduced as compared with the case where the discrete member such as the coil shown in FIG. 3B is mounted on the insulating substrate.

[Brief description of the drawings]

FIG. 1 is a view of a first embodiment of the present invention, FIG. 1 (a) is a plan view of an upper surface of an insulating substrate, FIG. 1 (b) is a plan view of a lower surface of the insulating substrate, FIG. 1 (c) is a sectional view taken along the line AA 'of FIGS. 1 (a) and 1 (b), FIG. 2 is a view of a second embodiment of the present invention, and FIG. 2 (a) is an insulating substrate. FIG. 2 (b) is a plan view of the upper surface of FIG.
FIG. 3 (a) is a cross-sectional view taken along the line B ', FIG. 3 (a) is a plan view showing an example of the prior art, and FIG. 1 ... insulating substrate, 2, 2a, 2b ... first conductor layer, 3, 3a, 3b ...
… Second conductor layer, 4, 4a, 4b… fourth conductor layer, 5, 5a, 5b,
6, 6a, 6b: Through-hole, 7, 7a, 7b, 8, 8a, 8b: Third conductor layer, 9, 9a: Gold wire, 10: Ferrite member, 11, 11a
... conductor layer, 12 ... discrete member, 13 ... solder.

Claims (1)

(57) [Claims] 1. A hybrid integrated circuit in which an electric circuit is formed on an upper surface and a lower surface of an insulating substrate and an inductance portion is formed on a part of the electric circuit, wherein a plurality of first conductors are provided on the upper surface of the insulating substrate. A layer and at least one second conductor layer are independently formed, and at least one of the first conductor layers and at least one of the second conductor layers are electrically connected by bonding metal wires; A plurality of through-holes formed in the insulating substrate, a third conductive layer formed in the through-hole, and at least one fourth conductive layer formed on the lower surface of the insulating substrate; Two said first conductor layers, at least one
One said metal wire, at least one said second conductor layer, at least two said third conductor layers, at least one
A hybrid integrated circuit, wherein an inductance section is formed by the four fourth conductor layers.