JP2762827B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor capacitor formed by a semiconductor layer.

[0002]

2. Description of the Related Art A semiconductor capacitor used in a conventional semiconductor integrated circuit device has two semiconductor layers opposed to each other via a thin insulating film serving as a capacitor insulating film, for example, a semiconductor substrate and a polysilicon layer or a polysilicon layer. It consists of a polysilicon layer.

[0003]

This conventional semiconductor capacitor requires a large plane area in a large planar shape in order to increase the capacitance value, and thus has a problem that it hinders an increase in the degree of integration of an integrated circuit.

[0004]

A feature of the present invention is that a plurality of polysilicon layers of the first conductivity type and a plurality of polysilicon layers of the second conductivity type are alternately formed on a semiconductor substrate via a capacitor insulating film. Each of the first conductivity type polysilicon layers is formed in a first direction perpendicular to a main surface of the semiconductor substrate.
A semiconductor device connected to a conductive type polysilicon region, wherein each of the second conductive type polysilicon layers is connected to a second conductive type polysilicon region formed vertically on a main surface of the semiconductor substrate; It is in. Here, the polysilicon region of the first conductivity type forms a PN junction with the polysilicon layer of the second conductivity type and penetrates the layer, and the polysilicon region of the second conductivity type is connected to the polysilicon layer of the first conductivity type. A PN junction can be formed and penetrate that layer. In addition, a diffusion layer of the second conductivity type is formed on the main surface of the first conductivity type of the semiconductor substrate, and a polysilicon region of the second conductivity type can be connected to the diffusion layer. The silicon region may be connected to the first conductivity type main surface of the semiconductor substrate.

In the above-described semiconductor capacitor element according to the present invention, since the capacitor electrode is formed by a plurality of vertically stacked polysilicon layers, the number of layers may be increased in order to increase the capacitance value. There is no need to increase the flat area. In addition, since it is difficult to connect a lead conductor to the side surface of the capacitor electrode, it is difficult to alternately take out the capacitor electrodes stacked in multiple layers. In this case, an extraction conductor must be connected to the upper surface of the periphery of each capacitor electrode. In this case, however, the area of the lower capacitor electrode becomes large, which limits the improvement of the degree of integration. However, in the present invention, a first conductivity type, for example, a P-type polysilicon layer and a second conductivity type, for example, an N-type polysilicon layer are alternately laminated, and P-type and N-type polysilicon regions are formed as extraction electrodes. Since it is used, the same conductivity type is continuously connected as it is, and PN junction separation between different conductivity types becomes possible,
As a result, even if all the capacitance electrodes have the same area without increasing the area of the lower capacitance electrode, the extraction electrode can be easily connected to the capacitance electrode, which also provides a highly integrated device.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a partial sectional view of a semiconductor wafer according to a first embodiment of the present invention. In manufacturing this semiconductor wafer, first, an N-type diffusion layer 2 is selectively formed on a P-type main surface of a silicon substrate 1, and a silicon oxide film 3 is formed as an insulating film over the entire main surface. An N-type polysilicon layer 5 having a thickness of 100 nm is formed thereon, and a 10-nm thick silicon oxide film 4 is formed on the surface of the polysilicon layer 5 by thermal oxidation.
To form Next, a P-type polysilicon layer 6 having a thickness of 100 nm is formed thereon, and a silicon oxide film 14 having a thickness of 10 nm is formed on the surface of the polysilicon layer 6 by thermal oxidation. Similarly, an N-type polysilicon layer 15 having a thickness of 100 nm, a silicon oxide film 24 having a thickness of 10 nm,
P-type polysilicon layer 16 having a thickness of 100 nm and a thickness of 10 n
A silicon oxide film 34 having a thickness of m and an N-type polysilicon layer 25 having a thickness of 100 nm are sequentially laminated (FIG. 1).
(A)).

Next, using a photolithography technique, the polysilicon laminate pattern obtained by patterning all the polysilicon layers and all the silicon oxide films of the laminate into the same plane shape is oxidized, and the top and side surfaces thereof are oxidized. A silicon oxide film 7 is formed on the entire surface (FIG. 1B).

Next, an opening is formed through the portion of the N-type diffusion layer 2 of the polysilicon laminate pattern using photolithography, and then a phosphorus-doped polysilicon film is formed on the entire surface and etched. Is performed so that the N-type polysilicon region 8 as one extraction electrode is left only in the opening on the diffusion layer 2 (FIG. 1C).

Next, an opening is provided in another region of the layered polysilicon layer. This opening is formed by etching so as to reach the P-type polysilicon layer 6 from above. After that, a boron-doped polysilicon film is formed in advance, and unnecessary portions are removed using photolithography technology, so that the P-type polysilicon as the other extraction electrode is formed between the inside and the outside of the opening. A silicon region 9 is formed (FIG. 1D).

Here, when the potential of the P-type polysilicon region 9 is set to the negative direction with respect to the N-type diffusion layer 2, the N-type polysilicon region 8 in contact with the N-type diffusion layer 2 becomes Although they are electrically conductive with the P-type polysilicon layers 6, 16, they are electrically insulated from each other because a depletion layer is formed at the contact portion. On the other hand, the P-type polysilicon region 9
Is electrically connected to the P-type polysilicon layers 6 and 16,
Since a depletion layer is formed at the contact portion with the N-type polysilicon layers 15 and 25, they are electrically insulated.

The N type polysilicon layer and the region and the P type polysilicon layer and the region are
The capacitance is formed by being insulated by the depletion layer and the depletion layers. That is, four MOS capacitors connected in parallel by the upper and lower polysilicon layers to the capacitance insulating films 4, 14, 24, and 34 are formed to overlap. Plane area of each polysilicon layer is 10
At the time of 0 μm ² , that is, on a 100 μm ² area of the semiconductor substrate, a capacitance element having a capacitance value of 1.4 pF is obtained. To obtain the same capacitance value by the conventional two-layer polysilicon technology, a plane area of 400 μm ² is required. Further, in this embodiment, the PN junction capacitance is added in parallel with the MOS capacitance, albeit slightly, so that the overall capacitance value further increases.

If this structure is used for a storage element of a dynamic RAM, a required capacity can be obtained in a small plane area, and high integration can be achieved.

Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 2, the same or similar parts as those in FIG. 1 are indicated by the same reference numerals. In the first embodiment, the P-type polysilicon region 9 is drawn out of the capacitive element. In the second embodiment, the P-type polysilicon region 19 as a corresponding lead electrode is extended vertically as it is. It is connected to the P-type surface of the semiconductor substrate 1.
As described above, since one of the extraction electrodes is connected to the substrate 1 under the formation of the capacitor, there is an advantage that the size of the plane area functioning as the capacitor is further reduced.

[0014]

As described above, the present invention provides a P-type, N-type
A capacitor electrode is formed by alternately stacking multiple polysilicon layers, and a P-type polysilicon region and an N-type
Since the polysilicon region is formed as a lead electrode, a large-capacitance element can be formed on a small flat area by a simple process. Therefore, when the present invention is applied to an integrated circuit, a highly integrated semiconductor device can be obtained by easy manufacture.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type semiconductor substrate 2 N-type diffusion layer 3 silicon oxide film 4, 14, 24, 34 capacitance insulating film 5, 15, 25 N-type polysilicon layer 6, 16 P-type polysilicon layer 7 silicon oxide film 8 N-type poly Silicon region 9,19 P-type polysilicon region

Claims (4)

(57) [Claims] A plurality of polysilicon layers of a first conductivity type and a plurality of polysilicon layers of a second conductivity type are alternately stacked on a semiconductor substrate via a capacitor insulating film; Are connected to a first conductivity type polysilicon region formed in a direction perpendicular to the main surface of the semiconductor substrate, and each of the second conductivity type polysilicon layers is connected to the main surface of the semiconductor substrate. A semiconductor device connected to a second conductivity type polysilicon region formed in the vertical direction. 2. The polysilicon region of the first conductivity type forms a PN junction with the polysilicon layer of the second conductivity type and penetrates the layer, and the polysilicon region of the second conductivity type is the first conductivity type polysilicon region. 2. The semiconductor device according to claim 1, wherein a PN junction is formed with the conductive type polysilicon layer and penetrates the layer. 3. A diffusion layer of a second conductivity type is formed on a main surface of a first conductivity type of the semiconductor substrate, and a polysilicon region of the second conductivity type is connected to the diffusion layer. The semiconductor device according to claim 1 or 2, wherein 4. The semiconductor device according to claim 1, wherein said first conductivity type polysilicon region is connected to a first conductivity type main surface of said semiconductor substrate. Semiconductor device.