JP2763019B2 - Frame pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse generator used for signal processing using a clock signal and a frame pulse signal, and more particularly, to a frame capable of monitoring a clock abnormality with respect to a frame pulse period. The present invention relates to a pulse generator.

[0002]

2. Description of the Related Art In general, a frame pulse generator of this type includes a clock generator and a signal processor. The clock generator generates a clock signal and n times the clock signal (n is an integer of 2 or more). Is generated. The signal processing unit operates by the clock signal and the frame pulse signal, and performs signal processing of the input digital signal. When performing the signal processing of the input digital signal according to the clock signal and the frame pulse signal as described above, it is necessary to synchronize the clock signal and the frame pulse signal. That is, it is necessary to detect an abnormality in the clock signal.

Here, a conventional frame pulse generator will be outlined with reference to FIG. As shown in the figure, the frame pulse generator includes a clock generator 11 and a signal processor 12, and the signal processor 12 operates by a clock signal and a frame pulse signal supplied from the clock generator 12.

[0004] The clock generator 11 is a clock generator 1
The clock generation circuit 13 generates a clock signal having a predetermined cycle. The clock signal is supplied to the counter 14 and the signal processing unit 12. The counter 14 receives the clock signal, counts the number of clocks, and outputs a count value. The count value is given to the decoder 15, and the decoder 15 sends out a timing signal of a predetermined cycle according to the count value. That is, the decoder 15 decodes the count value, generates a frame pulse signal having a cycle of a predetermined cycle (for example, n (n is a power of 2) times the cycle of the clock signal), and supplies the frame pulse signal to the signal processing unit 12.

The signal processing section 12 is provided with a signal processing circuit 16, and the signal processing circuit 16 performs signal processing of an input digital signal (not shown) based on a clock signal and a frame pulse signal. The clock signal and the frame pulse signal are supplied to the counter 17 as a reception clock signal and a reception frame pulse signal, respectively. The counter 17 counts the number of clocks of the reception clock signal and sends out a count value. Then, this count value is reset by the received frame pulse signal.

The counter value is provided to a decoder 18, which decodes the count value and generates a frame pulse signal (hereinafter referred to as a generated frame pulse signal). That is, the decoder 18 outputs a generated frame pulse signal having a cycle n times the cycle of the received clock signal. Then, the generated frame pulse signal is provided to the comparing unit 19.

The received frame pulse signal is also given to the comparing section 19, and the comparing section 19 compares the generated frame pulse signal with the received frame pulse signal. The detection result is given to the detection unit 20, and if there is a mismatch, the abnormality detection unit 20 is informed of “abnormality” and the abnormality detection unit 2
Give to 0. Upon receiving the notification of the “abnormality”, the abnormality detecting section 20 displays the notification to the outside and notifies the signal processing circuit 16, for example.

Here, referring to FIG. 4, for example, if it is assumed that a waveform abnormality occurs in the clock signal from the clock generation unit 11 to the signal processing unit 12 (that is, FIG. 4A) Assuming that a waveform abnormality occurs in the received clock signal and the clock is increased by one clock as shown by A), the counter 17 increases the count value earlier by the amount of the received clock signal increased by one clock. . Therefore, in the decoder 18, the output timing of the generated frame pulse signal is shifted by one clock as shown in FIG. As a result, the received frame pulse signal and generating a frame pulse signal as shown in ^FIG. 4 (c) A so that the abnormality becomes mismatch is detected in the comparator unit 19.

[0009]

By the way, the timing of abnormality detection is limited to the timing at which the comparator 19 compares whether the generated frame pulse signal matches the received frame pulse signal. Therefore, when an abnormality occurs in the received clock signal, the timing at which the abnormality is detected is the timing at which the next received frame pulse signal is compared with the generated frame pulse signal as described above. As a result, since the period of the reception frame pulse signal is longer than the period of the reception clock signal, the longer the period of the reception frame pulse signal, the longer the time from the occurrence of the abnormality of the reception clock signal to the detection of the abnormality. .

As described above, in the conventional frame pulse generating device, after the generated frame pulse signal is generated in the signal processing unit (for example, after the generated frame pulse signal becomes low level), an abnormality occurs in the received clock signal. Then, there is a problem that the abnormality of the clock signal cannot be detected until the next generated frame pulse signal is generated (until the next generated frame pulse signal becomes low level).

An object of the present invention is to provide a frame pulse generating apparatus in which the time from the occurrence of a reception clock signal abnormality to the detection of an abnormality is extremely short.

[0012]

According to the present invention, there is provided a frame pulse generator used for performing signal processing using a clock signal and a frame pulse signal generated based on the clock signal, An alternating signal generating means for generating an alternating signal having a predetermined alternating component based on the clock signal, and a frame pulse signal generating means for receiving the alternating signal and receiving the clock signal as a received clock signal to generate the frame pulse signal Timing extracting means for extracting a timing cycle of the frame pulse signal based on the received clock signal to obtain a timing cycle signal, and detecting an abnormality of the received clock signal according to the timing cycle signal and the frame pulse signal Frame pulse generating apparatus, comprising: Obtained.

[0013]

According to the present invention, a frame pulse signal is generated based on an alternating signal having a predetermined alternating component, a timing cycle of the frame pulse signal is extracted by a received clock signal, and a clock abnormality is detected based on the timing cycle. Thus, occurrence of a clock abnormality can be detected at the next rising edge of the clock. That is, the time from the occurrence of the clock abnormality to the detection of the abnormality can be extremely shortened.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

Referring to FIG. 1, in the illustrated frame pulse generator, the same components as those in the frame pulse generator shown in FIG. 3 are denoted by the same reference numerals.

Referring also to FIG. 2, the clock generator 21 includes an n (n is a power of 2) frequency dividing circuit 23 and a frequency dividing circuit 2. A clock signal (FIG. 2A) having a predetermined cycle is supplied from the clock generation circuit 13 to the n-divider circuit 23 and the divide-by-2 circuit 24. The divide-by-two circuit 24 divides the clock signal by two and outputs a divide-by-two signal (hereinafter, this divide-by-two signal is referred to as a first divide-by-two signal) (FIG. 2B). On the other hand, the n-frequency dividing circuit 23 divides the clock signal by n and sends out the n-frequency dividing signal shown in FIG. 2C (in the n-frequency dividing circuit 23, according to the required period of the frame pulse signal). The clock signal is frequency-divided by n, that is, n is set according to the required period of the frame pulse signal.
6). These 16 frequency-divided signals and the first 2
The frequency-divided signal is applied to an exclusive-OR circuit (EX-OR) 25, where it is subjected to an exclusive-OR operation. And EX-OR
From 25, a first exclusive OR signal (EX-OR signal)
Is transmitted (FIG. 2D). The first EX-OR signal is an alternating signal having a predetermined alternating component (alternating cycle) as shown in FIG.

The signal processing unit 22 includes a divide-by-2 circuit 26, an exclusive OR circuit (EX-OR) 27, a flip-flop circuit 28, and an exclusive NOR circuit (EX-NOR) 29. The clock signal from 13 is supplied to the divide-by-2 circuit 26 as a reception clock signal.
The divide-by-2 circuit 26 divides the frequency of the received clock signal by 2, and sends out a divide-by-2 signal (hereinafter this divide-by-2 signal is referred to as a second divide-by-2 signal) (FIG. 2 (e)). . EX-OR2
7 is supplied with a first EX-OR signal and a second divided-by-2 signal, and an EX-OR 27 outputs an EX-OR signal (hereinafter, this EX-OR signal is referred to as a second EX-OR signal). ) To the flip-flop circuit 28 and the EX-NOR 29
(FIG. 2 (f)).

The flip-flop circuit 28 operates according to the received clock signal. The flip-flop circuit 28 delays the second EX-OR signal by one clock cycle and outputs the delayed signal as a delay signal (FIG. 2 (g)). Then, this delay signal is provided to EX-NOR 29. EX-NO
The second EX-OR signal and the delay signal are provided to R29, and an EX-NOR signal is output (FIG. 2 (h)). Then, this EX-NOR signal is sent to the signal processing circuit 16 as a frame pulse signal, and is also given to the counter 17 and the comparison unit 19.

The counter 17 is provided with a reception clock signal. The counter 17 counts the number of clocks of the reception clock signal in accordance with the EX-NOR signal and sends out a count value (FIG. 2 (i)). That is, the counter 17 is EX
When the NOR signal goes low, the count is reset and the count is started again. The counter value is provided to the decoder 18, and the decoder 18 decodes the count value to generate a frame pulse signal (hereinafter, referred to as a generated frame pulse signal). For example, when the decoder 18 receives the count value “0” after the count value becomes “7”, the decoder 18 changes the generated frame pulse signal to a low level as shown in FIG. That is, the decoder 18 outputs a generated frame pulse signal having a period eight times as long as the period of the received clock signal (that is, a signal that goes low every eight bits). Then, the generated frame pulse signal is provided to the comparing unit 19.
Thus, the counter 17 and the decoder 18 are EX-N
This means that the timing cycle (regularity) of the OR signal (frame pulse signal) is extracted, and a signal indicating this timing cycle is output as the generated frame pulse signal.

The comparator 19 is also supplied with an EX-NOR signal, and the comparator 19 generates the generated frame pulse signal and the E-NOR signal.
The X-NOR signal is compared, and if they match, the result is given to the abnormality detection unit 20 to indicate “normal”, and if they do not match, the abnormality detection unit 20 is notified to indicate “abnormal”. give. For example, the comparator 19 sends a low level signal when the generated frame pulse signal and the EX-NOR signal match, and sends a high level signal when the generated frame pulse signal and the EX-NOR signal do not match. (Figure 2
(K)). Upon receiving the notification of the “abnormality”, the abnormality detecting section 20 displays the notification to the outside and notifies the signal processing circuit 16, for example.

Here, the clock signal is supplied to the clock generator 2.
Assume that an abnormality occurs in the clock signal while the clock signal is transmitted from 1 to the signal processing unit 22 (for example, as shown by a symbol A in FIG. ), The second
In the frequency-divided-by-2 signal, the two pulses are continuous with a slight gap as shown by a symbol B in FIG. As a result, the second EX-OR signal rises (high level) at the trailing edge of the gap as shown in FIG. 2 (f). As a result, the EX-NOR signal goes low in a short cycle as shown in FIG.

As described above, the counter 17 has EX-NO
When the R signal becomes low level, the count is reset and the count is started again. Therefore, as shown in FIG.
When the X-NOR signal goes low in a short cycle, the count value is reset to "7" without becoming "7". As a result, the decoder 18 keeps the generated frame pulse signal at the high level. Accordingly, the comparison unit 19 detects a mismatch between the EX-NOR signal and the generated frame pulse signal, and the comparison unit 19 performs the operation shown in FIG.
The high level is output as shown in FIG. That is, the EX-NOR signal and generating a frame pulse signal becomes inconsistent with the position indicated by reference numeral ^A, in FIG. 2 (k), the abnormality detecting section 20 portion A abnormal reception clock signal is ^generated,
An abnormality is detected at the rising edge of the next clock.

[0023]

As described above, according to the present invention, a frame pulse signal having a predetermined cycle is generated based on an alternating signal having a predetermined alternating component, and the regularity (timing cycle) of the frame pulse signal is generated. Because it monitors the abnormality of the received clock signal by monitoring,
An abnormality in the reception clock signal can be detected at the next rising edge of the clock, and the time from the occurrence of the abnormality in the reception clock signal to the detection of the abnormality can be extremely shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a frame pulse generator according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the frame pulse generator shown in FIG.

FIG. 3 is a block diagram showing a conventional frame pulse generator.

FIG. 4 is a timing chart for explaining the operation of the frame pulse generator shown in FIG. 3;

[Explanation of symbols]

 11, 21 clock generation unit 12, 22 signal processing unit 13 clock generation circuit 14, 17 counter 15, 18 decoder 16 signal processing circuit 19 comparison unit 20 abnormality detection unit 23 n frequency dividing circuit 24, 26 2 frequency dividing circuit 25, 27 EX-OR 28 Flip-flop 29 EX-NOR

Continuation of front page (58) Fields investigated (Int.Cl. ⁶ , DB name) H04L 25/00 G06F 1/04 302 H04L 7/00

Claims (7)

(57) [Claims] 1. A frame pulse generator used when performing signal processing using a clock signal and a frame pulse signal generated based on the clock signal,
An alternating signal generating means for generating an alternating signal having a predetermined alternating component based on the clock signal, and a frame pulse signal generating means for receiving the alternating signal and receiving the clock signal as a received clock signal to generate the frame pulse signal Timing extracting means for extracting a timing cycle of the frame pulse signal based on the received clock signal to obtain a timing cycle signal, and detecting an abnormality of the received clock signal according to the timing cycle signal and the frame pulse signal A frame pulse generator comprising: 2. The frame pulse generator according to claim 1, wherein said alternating signal generating means divides the clock signal by two to obtain a first divide-by-2 signal. N frequency dividing means for dividing the clock signal by n (n is a power of 2) to obtain an n frequency divided signal;
And a first EXOR means for obtaining the first EXOR signal by performing an exclusive OR operation on the divided-by-2 signal and the divided-by-n signal to output the first EXOR signal as the alternating signal. A frame pulse generator. 3. The frame pulse generating device according to claim 2, wherein said frame pulse generating means receives said reception clock signal and divides said reception clock signal by two to obtain a second divide-by-2 signal. 2, the exclusive-OR operation of the alternating signal and the second frequency-divided signal by 2
A second EXOR signal for obtaining the EXOR signal, and an output means for obtaining the frame pulse signal based on the received clock signal and the second EXOR signal. 4. The frame pulse generating apparatus according to claim 3, wherein said output means includes a second EXOR.
Delay means for delaying the signal in accordance with a predetermined delay amount to obtain a delayed signal; exclusive NOR of the second EXOR signal and the delayed signal to obtain an EXNOR signal and outputting the EXNOR signal as the frame pulse signal Exclusive NO
A frame pulse generator, comprising: R means. 5. The frame pulse generating apparatus according to claim 4, wherein said delay means is a flip-flop, and said delay amount is one clock cycle of said received clock signal. . 6. The frame pulse generator according to claim 3, wherein said timing extracting means is reset by said frame pulse signal, counts said reception clock, and outputs a count value. And a decoding means for decoding the count value to obtain a decoded signal and outputting the decoded signal as the timing period signal. 7. The frame pulse generating device according to claim 6, wherein the detecting unit compares the frame pulse signal with the timing period signal and outputs a mismatch signal if the timing pulse signal is not matched, An abnormality detecting means for determining that the reception clock is abnormal when receiving the mismatch signal.