JP2764579B2 - High-speed tracking PLL device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-speed tracking type PLL device. [Prior Art] FIG. 2 is a diagram showing an example of a conventional PLL device.
In the figure, 71 is an input terminal, and the input supplied to the input terminal 71 is
The force signal is supplied to one input terminal of the phase comparator 72. The other input terminal of the phase comparator 72 has a frequency divider described later.
75, and the phase comparator 72
Phase of the signal input to the input terminal and input to the other input terminal
The phase of the input signal is compared with the phase of the
The phase error signal corresponding to the difference is converted to a low-pass filter
LPF) is output to 73. LPF73 removes high frequency components
The phase error signal is a voltage controlled oscillator (VCO).
4 is supplied as a control signal. VCO74 is used for phase error signal
Outputs a signal of the corresponding frequency to frequency divider 75 and output terminal 76
I do. Divider 75 divides the signal output from VCO 74
Then, the divided signal is phase-compared as described above.
Supply 72. [Problems to be Solved by the Invention] However, the conventional PLL device is not suitable for the time axis fluctuation such as jitter.
Large signal, that is, low frequency fluctuation
Phase synchronization (locking) for signals with large phase fluctuations.
H) was difficult. One of the reasons is,
Even if the frequencies are the same, to achieve phase synchronization
Shifts the frequency once to approach the relative phase
And do not repeat the frequency matching.
Because it must be. The present invention aims to solve the above problems.
It is. [Means for Solving the Problems] In the first invention of the present invention, the oscillation frequency is controlled by a control signal.
M times the frequency of the correction output signal to be controlled and required (m
Is an integer greater than or equal to 2).
A control oscillator; and an output signal of the voltage-controlled oscillator as a reference signal.
By shifting the phase of the received reference signal.
Delay circuit for producing sub-reference signals having two or more different phases
And a trigger signal from the trigger input terminal, and
Divides these sub-reference signals by 1 / m
Divider and the logical output of the divided signal
Synchronization signal selection circuit composed of logic circuits;
A second frequency divider for dividing the output signal of the signal selection circuit;
Receiving the output signal of the second frequency divider at the first input terminal.
Receives an external input signal at a second input terminal,
Detects the phase difference between the output signal of the
Phase comparison that outputs a phase error signal corresponding to the phase difference between signals
And a phase error signal supplied from the phase comparator.
To remove the frequency component to control the voltage-controlled oscillator.
A high-speed tracking type PLL device consisting of a low-pass filter
You. In the second invention, the oscillation frequency is controlled by a control signal.
M times the frequency of the required correction output signal (m is 1 or more)
Voltage-controlled oscillator that outputs a signal with an oscillation frequency of
And receives the output signal of this voltage-controlled oscillator as a reference signal.
The phase of the received reference signal is shifted by two or more
And delay circuit to create sub-reference signals with different phases
A trigger signal is received from the input terminal, and the trigger signal is received.
From the time, these sub-reference signals start to be divided by 1 / 2m
And the OR of the inverted signal of each signal after the frequency division.
A first logic circuit for outputting a logical product and a non-
Second logic circuit that outputs a logical sum or a logical product of inverted signals
And the logic of receiving the OR output of the first and second logic circuits
The logical product circuit or the logical product output of the first and second logic circuits is received.
A synchronizing signal selection circuit composed of a logical sum circuit
Second frequency divider for dividing the output signal of the synchronization signal selection circuit
Receiving the output signal of the second frequency divider at the first input terminal
And an external input signal received at a second input terminal.
Detects the phase difference between the output signal of the frequency divider and the external input signal.
Output the phase error signal corresponding to the phase difference between the two signals.
A phase comparator; and a phase error signal supplied from the phase comparator.
Control signal of the voltage-controlled oscillator by removing high-frequency components of the signal
-Speed PLL with low-pass filter
Place. EXAMPLES The present invention will be described below with reference to the illustrated examples. The circuit of the high-speed tracking PLL device shown in FIG.
Frequency and phase accuracy for input signal S1 applied to 1
High, but do not change the frequency significantly
The frequency and the frequency of the input signal S1
Is configured to obtain an output signal having a constant phase relationship
I have. Specifically, as shown in FIG.
The voltage control oscillator (VCO) 6 and the synchronization signal selection circuit
7, a phase shifter 8, a frequency divider 9, a phase comparator 2,
The analog switch 3B in front of the
Low-pass filter (LP) that also functions as a pressure holding circuit
F) It has 4, 5 and a timing extraction circuit 10,
The correction output signal S15 to be output is obtained at the output terminal 15. VCO6 converts control signal S34 from analog switch 3B to LPF
4 after receiving the signal S4 after removing the high frequency component,
The oscillation frequency is controlled and required by the signal S4
M times the frequency f of the corrected output signal S15 (m is an integer of 2 or more)
The signal S6 of the oscillation frequency mf of (number) is sent to the synchronization signal selection circuit 7.
It is a circuit to give. The synchronization signal selection circuit 7 receives the output signal S6 of VCO6.
While the trigger input terminal 12 synchronizes with the trigger signal S12.
The signal S7 having a frequency 1 / m of the signal S6 (frequency mf).
(Frequency f). Note that the trigger signal S1
2 is extracted from the input signal S1 by the timing extraction circuit 10.
Will be issued. The output signal S7 from the synchronization signal selection circuit 7 is a correction output terminal
15 appears, but is actually taken out from this synchronization signal selection circuit 7.
The signal S7 generated depends on the external conditions.
It will be slightly out of phase. The phase shifter 8 corrects this shift.
The phase of the output signal S7 is for compensation.
When it deviates from the expected constant phase relationship for
Works to return this to the correct phase relationship. Therefore,
The phase shifter 8 is used when the phase shift accuracy is not required very much.
Can be omitted. In any case, the output signal S7 from the synchronization signal selection circuit 7
Passes through the phase shifter 8 and is correct as the corrected output signal S15.
Appears at output terminal 15 in phase relationship. The frequency divider 9 synchronizes with the trigger signal S12 to output the corrected output signal.
Start the frequency division of signal S15 and compare the phase
Input to the container 2. The frequency divider 9 mainly outputs the correction output signal.
The frequency of the input signal S1 is (1 / n) f with respect to the frequency f of the signal S15.
And when both are different and phase comparison is not possible
It is. Therefore, if the frequency is the same, the frequency divider 9 is 1
The division ratio can be set to one. here
Description will be made on the assumption that the frequencies are different. Next, the phase comparator 2 outputs the output of the frequency divider 9 and the input signal S1.
And the phase difference between the two signals.
The corresponding phase error signal S2 is output. The floating circuit 3A is connected to the input signal S1 or the frequency divider.
Floating circuit when the signal S9 from 9 is lost
Flow through the input terminal of analog switch 3B connected to 3A
And the input terminals of LPF4 and 5 are floated as a result.
It plays the role of making a state. This means that LPF4 and LPF5
If it is composed of circuits,
Means that the input value is held by the sensor. This meaning
In taste, LPFs 4 and 5 also function as voltage holding circuits.
I do. The analog switch 3B is connected via the floating circuit 3A.
Receiving the phase error signal S2 from the phase comparator 2
An alternative is to supply the error signal S2 to one of the LPFs 4 and 5 alternatively.
It has a selection function. This switching order is determined by the phase error signal S2
Is supplied to the LPF5 side for phase correction first, and then the frequency
Supply to LPF4 side for correction. Phase correction
Supply to the LPF5 side is superior to supply to the LPF4 side for frequency correction.
The first step is to set the position even though the frequency variation is not large.
This is because phase change often occurs. For example, floppy
-Disk devices such as disks or video tape recorders
Motors are used for the
The frequency is constant because an oscillator such as crystal is used.
Despite the existence of motor wow and flutter (rotation
Wobble), the phase fluctuation will inevitably increase.
I will. There is also a method of pulling the phase after changing the frequency first
However, with this method, the frequency
Nevertheless, the frequency must be changed.
The time is longer. However, in the above method, the phase is
, So if the frequency matches, the more
, The retraction is completed, and the retraction time is greatly reduced. Floating circuit 3A is in non-floating state
In some cases, LPFs 4 and 5 are output signals according to the input signal.
Is output. The LPFs 4 and 5 have a floating circuit 3A.
When switching to the floating state,
Holds the output value that was changed. LPF4 is the high frequency range from the output signal S34 of the analog switch 3B.
The components are removed and supplied to VCO6, which is obtained by LPF4.
Signal whose oscillation frequency is controlled by the magnitude of the DC component
Outputs S6. LPF5 is connected to analog switch 3B.
High frequency components are removed from the output signal S35 and supplied to the phase shifter 8.
Work. The phase shifter 8 controls the direct current obtained from the LPF 5
Depending on the magnitude of the component, the
The phase amount of the signal S7 to be maintained in a fixed relationship with the input signal S1.
The output is output to the correction output terminal 15 in such a manner. The timing extraction circuit 10 receives the signal from the initial signal input terminal 11
After receiving the initial signal S11, the input signal S1
, And generate the switching signals S12, S13, and S14. FIG. 5 shows an input signal S1 of a color television.
Burst separation from color burst and carrier color signal (VS)
Color burst signal extracted by an amplification circuit (not shown)
(BS) and demodulates the carrier color signal
Synchronization circuit that generates the necessary reference subcarrier (SBS)
This is an example of functioning as Of course, the circuit of FIG.
In addition to this, for example, a clock signal for writing a color video signal
Signal generation circuit and conversely, a clock for reading color video signals
Signal generation circuit, frequency counter for burst signal,
For reading in so-called disk devices such as floppy disks
Or a clock signal generating circuit for writing or a disk device
Synchronization signal detection circuit or decoding circuit, etc.
Is a frequency hopping communication method (frequency is kept for a certain time)
And changing the frequency sequentially,
Synchronization signal detection circuit).
Or synchronous signal generation circuit or serial data transmission system
Signal detection circuit, decoding synchronization signal generation circuit, etc.
Is also applicable. However, for convenience of explanation here
The above description will focus on the color synchronization circuit. As shown in FIG. 5, in the case of the color synchronization circuit, the timing
Initial signal S11 from initial signal input terminal 11 of extraction circuit 10.
Is a burst sampling pulse (BT). And Thailand
The first timing signal S12 of the timing extraction circuit 10 is
Color berth after the strike extraction pulse (BT) is input
Signal BS was detected for a certain period of time or a certain number of repetitions.
If the output goes to L level,
H level again when the sampling pulse (BT) is input.
Reset signal (K). Second timing signal S1
3 is when the state of the reset signal K changes,
Signal BS is detected for a certain period of time or a certain number of repetitions.
Is an analog select signal (AS) output during the period.
The third timing signal S14 is an analog select signal (A
When the burst signal BS is constant after the state of S) changes
Output until the number of repetitions is detected
This is a floating select signal (FS). Next, in the case of this color synchronization circuit, the circuit of FIG.
The operation will be described with reference to FIG. This Figure 5
Shows the operation after the second burst signal S1 has arrived
Things. As long as the second burst signal S1 has not yet arrived,
Second timing signal S13 (AS) of the trimming extraction circuit 10
Is at the L level, so that the floating circuit 3A
In the loading state. The timing extraction circuit 10
The third timing signal S14 is also at the L level,
As a result, the analog switch 3B is switched to the LPF4 side. Taimi
About the first timing signal S12 of the timing extraction circuit 10,
L level. As a result, the synchronization signal selection circuit 7
The prohibition has been released, and the correction output signal S1 is output to the output terminal 15.
5 has occurred. First, burst sampling prior to the second burst signal S1
The pulse BT arrives (time t10). This allows
The first timing signal S12 of the logic extraction circuit 10 goes high.
Changes, the synchronizing signal selection circuit 7 is inhibited, and its output is stopped.
Stop. Next, the second burst signal S1 in question is
Arrives (point P in FIG. 5). Therefore, the phase comparator 2
The inhibition of the period signal selection circuit 7 is released and the output of the frequency divider 9 is output.
It is in a state of waiting for the input of the signal S9. Taimin
The burst extraction circuit 10 counts the burst signal S1 from point P.
When it reaches a constant value, in this embodiment, when it counts 3
At the point (time t11), the first timing signal S12 is set to L level.
The second timing signal S13 and the third timing signal
The signal S14 is set to the H level. The first timing signal S12 (L
Level), the inhibition of the synchronization signal selection circuit 7 is released.
At the same time, the frequency divider 9 starts the frequency dividing function. As a result,
The phase comparator 2 compares the output signal S9 of the frequency divider 9 with the second bar
The phase comparison with the strike signal S1 is started. Also, the second Thai
Floating circuit 3 by the timing signal S13 (H level)
A switches to the non-floating state and the third timing
The signal S14 switches the analog switch 3B to the LPF5 side.
Therefore, the output of the phase comparator 2 is
A, supplied to LPF5 through analog switch 3B,
The component is removed and added to the phase shifter 8 as a phase correction signal.
You. The phase shifter 8 receives the phase correction signal,
The output signal of the selection circuit 7 is twice the output signal S9 of the frequency divider 9
In the direction to reduce the phase error with the burst signal S1,
Phase shift. However, here, the output signals S9 and S2 of the frequency divider 9 are
The phase error with the second burst signal S1 is zero or 90 degrees.
Or if a certain relationship such as 180 degrees is maintained,
Think there is no. Originally, the phase relationship between the output of the synchronization signal selection circuit 7 and S1 is
Originally the phase error should be zero, but the circuit element
Due to the inherent delay time, the output signal is delayed,
A phase shift occurs as shown by tp in FIG. The phase shifter 8
The error of these phases is calculated from the time t11 by the second burst signal.
The number BS is a constant count number (3 counts in Fig. 5)
Phase error (time t11 to time t12)
Reduce the difference. Of course, besides this, power supply voltage fluctuation,
Phase error due to phase fluctuation due to environmental temperature change, etc.
However, in the long run, such phase errors
The difference will also be corrected as a result. Fifth
In the figure, the phase error is shown to be zero at time t12.
However, in practice, the phase error is not always eliminated at t12
Not necessarily. The timing extraction circuit 10 outputs the burst signal S1 from point P
When the count reaches a fixed value, in this embodiment, 5
At the point of time (time t12), the third timing signal S14
To L level. The third timing signal S14 causes
The analog switch 3B switches to the LPF4 side. Therefore, the phase comparison
The output of switch 2 is a floating circuit 3A, analog switch.
Is supplied to LPF 4 through switch 3B, and the high-frequency component is removed.
It is added to O6 as a frequency correction signal S4. VCO6 has this frequency
Receiving the number correction signal S4, the output signal of the synchronization signal selection circuit 7
With the output signal S9 of the frequency divider 9 and the second burst signal S1
Output frequency to reduce the frequency error of
To By the way, the analog switch 3B switches to the LPF4 side,
F5 is disconnected, but the previous analog switch 3B is disconnected.
The correction amount immediately before switching is determined by the capacitor that is a component of LPF5.
Is stored. Therefore, after time t12
The phase correction is still performed. The timing extraction circuit 10 outputs the burst signal S1 from point P
When the count reaches a constant value, in this embodiment, 8
At the point in time (time t13), the second timing signal S13
To L level. The second timing signal S13 causes the
The loading circuit 3A switches to a floating state. Obedience
Therefore, the output of the phase comparator 2 is supplied to the floating circuit 3A.
It is further separated and not supplied to the analog switch 3B.
As a result, the correction amount immediately before switching to the floating state
Is stored in a capacitor that is a component of LPF4.
I have. Therefore, even after time t13, the frequency is corrected.
Is continued. The phase and frequency correction described above is performed for each
It is repeated each time a burst signal arrives. This
Phase changes at a constant frequency,
When the phase and frequency are not maintained in a fixed relationship
Also keeps the phase constant without changing the frequency first.
Only instantaneous phase pull-in
Can be completed. Therefore, even if there is not much frequency fluctuation,
If the phase change occurs, for example,
Information such as disk device or video tape recorder
If applied to the signal system, the motor drive source wow and flutter
Even if it is large, this can be corrected instantaneously in a circuit.
Wear. In the above embodiment, the floating circuit 3A is
Switching with the output signal S9 of the frequency divider 9 or the input signal
Floating circuit 3A can be switched by force signal S1.
Can also be. Also, the input terminal 11 is omitted, and the input signal S1
Thus, a necessary timing signal can be obtained. In addition, another circuit is added to the above-described embodiment, for example, a floppy
-Sync signal detection circuit for disk devices, etc.
It can be applied to signal generation and decoding circuits and decoding circuits.
is there. Furthermore, synchronous signals in frequency hopping communication systems
Signal generation circuit, decoding circuit in the same system, etc.
Wear. These floppy disk drives and frequency hopping
In the case of application to the communication system, etc., the circuit of FIG.
It can be modified and applied as follows. That is, in the above embodiment, the input of the phase comparator 2 is
Connected only to the switching circuit 3A, but the phase comparator
2 outputs are newly provided in addition to the floating circuit 3A
Connected to an isolation amplifier (not shown)
Output of the other isolation amplifier
Filter (not shown) so that the low-pass filter
When the filter output reaches a certain voltage level
Is the voltage ratio assuming that the frequency or phase is out of synchronization.
The comparator is configured to output a signal. As a result, the synchronization signal (information
(Information signals are generally called sync signals.)
Changes in the state of the
Determines the differential of the
Circuit that detects when a signal is coming
Can also be used. Next, the configuration of the synchronization signal selection circuit 7 will be described.
You. First, as a first embodiment, a required output signal
A reference signal of m times the repetition frequency (m is an integer of 2 or more)
The number of received reference signals is shifted by n
(N is an integer of 2 or more) with sub-reference signals having different phases
From the time when the trigger is received,
1 (that is, 1 / p = 1 / m) starts to be divided, and the logic of the divided signal
A synchronizing signal selection circuit that takes out the sum as an output will be described.
You. FIG. 3 shows a specific circuit when m = p = 2 and n = 3.
You. That is, the reference signal of the repetition frequency 2f applied to the input terminal 23
Using the signal S0, the phase is sequentially delayed by 1/3 and
Create reference signals SA, SB, SC and divide them by half
It is an example of a circuit configured as described above. Delay device 30 has two delays
The circuits DL1 and DL2 are connected in series, and the selection circuit 40
The frequency divider 41 of the
FF frequency dividers 43, 44, 45 consisting of FF1, FF2, FF3
And the OR circuit 42
It consists of an OR gate 46 that takes the outputs of FF1, FF2, and FF3 as three inputs.
It has been done. 4) 1) to 8) of the circuit of FIG.
The operation of each unit will be described. The desired repetition frequency f for the output signal S is 2 MHz.
The reference signal S0 of the repetition frequency 2f (4 MHz)
FF1 is used as the sub-reference signal SA from the device 30 as it is.
Lock input CK, on the other hand, delay circuits DL1, DL2
Through the sub-reference signals SB and SC
Then, they are input to frequency dividers 44 and 45, respectively. Sub reference signal
SA, SB, and SC are out of phase with each other by 1/3 of one cycle.
(2 in FIG. 4) to 4)). Now, the trigger signal G is
24 and therefore its inverted signal from inverter 47
Is the preset input PR of the flip-flops FF1, FF2, FF3
When applied to each flip-flop, each flip-flop is
Falling of the trigger signal G (inverted signal shown in FIG. 4)
From the rising edge), each flip-flop performs frequency division operation
It becomes possible (point a in FIG. 4). That is, FF1, FF2, FF3
The output is the sub-reference signal input to the clock input terminal CK
Invert every time SA, SB, SC falls, and 1/2
The lap starts (5 in FIG. 4) to 7)). OR gate 46
The output of these FF1, FF2, FF3, that is, the signal after 1/2 frequency division
(2MHz) OR, and output signal S to terminal 25
Output (8 in FIG. 4). The repetition period T of the output signal S is 2) to 2 in FIG.
As is clear from 8), the periods TA, TB,
2 times TC (ie, the period of the reference signal S0),
The desired repetition frequency f (2 MHz) as the output signal S
Will be obtained. On the other hand, jitter
Sub-reference signals SA and S delayed by 1/3 of one cycle of reference signal S0
Since B and SC are used, the jitter is simply
1/3 compared to using one signal that doubles the number f0
To decrease. Moreover, the first rising of the output signal S is 3
Of the trigger signal among the two sub-reference signals SA, SB, SC
The sub-reference signal SA having the earliest temporal relationship with the rising point
Is obtained on the basis of FIG. 6 is a specific circuit when m = p = 2 and n = 3.
AND gate 52 configured as AND circuit 51 of selection circuit 40
Is used. Therefore, the operation of each part of the circuit of FIG.
These are 1) to 7) and 9) in FIG. Next, as a second embodiment, the required output signal
A reference signal of m times the repetition frequency (m is an integer of 1 or more)
And a voltage-controlled oscillator as the reference signal source.
By shifting the phase of the digitized reference signal, n (n is
Create sub-reference signals with different phases (integer of 2 or more),
These sub-reference signals are reduced to 1 / 2m
(1 / p = 1 / 2m), and the inverted signal of each signal after frequency division
Output the logical sum of the signals and the logical sum of the non-inverted signals.
Synchronous signal selection circuit for taking the logical product of the sum signal as output
Will be described. This circuit, as already evident,
This holds when p is an even number. FIG. 8 is a specific circuit in the case of m = 1, n = 3, p = 2.
A road example is shown. The circuit shown in FIG. 8 comprises 1/2 frequency dividers 43, 44, 4
Q output of flip-flops FF1, FF2, FF3 that constitute 5
The force is not only calculated by OR gate 46, but also output.
The power is also ORed by another OR gate 48, and both OR gates 4
Outputs 6 and 48 to terminal 25 through AND gate 49
It is configured as follows. 9) 1) to 13) show the operation of each part of the circuit of FIG.
Show the work. 9) to 11) of FIG. 9 use the frequency dividers 43, 44 and 45.
These are the outputs of FF1, FF2, and FF3 that make up
Q output is inverted. In addition, 12) in FIG.
The output waveform of the AND gate 49 is shown in FIG.
The output waveform is shown. As is clear from the relationship between 1) to 4) and 13) in FIG.
The period T of the output signal S obtained from the AND gate 49 is
Are the periods TA, TB, TC of the sub-reference signal (that is, the reference signal S0
Cycle). Therefore, the output signal is
Use the same repetition frequency f as the repetition frequency f of signal S
do it. For example, the desired repetition as output signal S
Assuming that the frequency f is 2 MHz, the reference signal S0 has a frequency of 2 MHz.
You can use This means that in the circuit of FIG.
Reference for lower repetition frequency than in FIGS. 3 and 6.
This means that the signal S0 can be used. In spite of
And the jitter (tj in Fig. 9) corresponds to the number n of sub-reference signals
Of course, the output signal S
Of the three sub-reference signals SA, SB, SC
The rising time of the trigger signal (point a in FIG. 9)
Is the earliest in time relationship, based on the sub-reference signal SA.
can get. FIG. 10 is a specific circuit in the case of m = 1, n = 3 and p = 2.
A road example is shown. The circuit shown in FIG. 10 includes 1/2 frequency dividers 43, 44, and 4
Q output of flip-flops FF1, FF2, FF3 that constitute 5
In addition to ANDing the power with the AND gate 52,
The output is also ANDed by another AND gate 53, and both AND gates are used.
The outputs of ports 52 and 53 are output to terminal 25 through OR gate 54.
It is configured as follows. 11) to 13) of FIG. 11 show the operation of each part of the circuit of FIG.
Show the work. 9) to 11) in FIG. 11 use the frequency dividers 43, 44 and 45.
These are the outputs of FF1, FF2, and FF3 that make up
Q output is inverted. 11) in Fig. 11 is AND
The output waveform of the gate 53 is shown in FIG.
4 shows a force waveform. As apparent from the relationship between 1) to 4) and 13) in FIG.
The period T of the output signal S obtained from the OR gate 54
Are the periods TA, TB, TC of the sub-reference signal (that is, the reference signal S0
Cycle). Therefore, the reference signal S0 is
Set the repetition frequency to the same as the repetition frequency f of S
No. For example, the desired repetition frequency f as the output signal S
Is 2MHz, use 2MHz reference signal S0
do it. This is the case in the circuit of FIG.
6 and the reference signal S0 having a lower repetition frequency
Means that it can be used. Nevertheless,
(Tj in FIG. 11) is 1/3 corresponding to the number n of the sub-reference signals.
Of course, the output signal S
The falling edge of the three sub-reference signals SA, SB and SC
Time relative to the rising point of the Riga signal (point a in FIG. 11)
The fastest relationship is obtained with reference to the sub-reference signal SA.
You. In the above-mentioned synchronizing signal selection circuit 7, the flip
Instead of flops FF1, FF2, FF3, the amount that can be preset
Use a frequency divider and preset it to the desired value.
, The phase position from the trigger signal is 90 degrees, 180 degrees, 270
It is possible to set it like a degree. [Effect of the Invention] Since the phases are matched first, if the frequencies match.
If that is the case, the withdrawal will be completed and the withdrawal time will be significant
Is shortened to

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing an embodiment of a high-speed tracking type PLL device of the present invention, FIG. 2 is a diagram showing a conventional PLL device, and FIG. 3 is a specific example of a synchronization signal selection circuit. 4 is a diagram showing the operation of each part of the synchronization signal selection circuit of FIG. 3, FIG. 5 is a diagram showing the operation of the high-speed tracking type PLL device of FIG. 1, and FIG. 6 is a synchronization signal selection circuit. FIG. 7 is a diagram showing the operation of each part of the synchronization signal selection circuit in FIG. 6, FIG. 8 is a diagram showing still another implementation example of the synchronization signal selection circuit, FIG. Is a diagram showing the operation of each part of the synchronization signal selection circuit of FIG. 8, FIG. 10 is a diagram showing another specific example of the synchronization signal selection circuit, and FIG. 11 is a diagram of each part of the synchronization signal selection circuit of FIG. It is a figure showing an operation.

Claims (1)

(57) [Claims] A voltage-controlled oscillator whose oscillation frequency is controlled by a control signal and outputs a signal having an oscillation frequency that is m times (m is an integer of 2 or more) the frequency of a required correction output signal; Received as a signal,
A delay circuit for generating a sub-reference signal having two or more different phases by shifting the phase of the received reference signal; receiving a trigger signal from a trigger input terminal; A synchronizing signal selecting circuit composed of a frequency divider that starts dividing by 1 and a logical circuit that takes out a logical sum or a logical product of the frequency-divided signals; and an output signal of the synchronizing signal selecting circuit is frequency-divided. A second frequency divider that receives an output signal of the second frequency divider at a first input terminal and an external input signal at a second input terminal of the second frequency divider. A phase comparator for detecting a phase difference from the input signal and outputting a phase error signal corresponding to the phase difference between the two signals; and removing the high-frequency component of the phase error signal supplied from the phase comparator to remove the voltage. A low-pass filter that outputs the control signal of the control oscillator; Ranaru high-speed tracking type PLL device. 2. A voltage-controlled oscillator whose oscillation frequency is controlled by a control signal and outputs a signal having an oscillation frequency that is m times (m is an integer of 1 or more) the frequency of a required correction output signal; Received as a signal,
A delay circuit for creating a sub-reference signal having two or more different phases by shifting the phase of the received reference signal, and receiving a trigger signal from a trigger input terminal; A frequency divider that starts dividing by a factor of 1, a first logic circuit that outputs a logical sum or a logical product of inverted signals of the signals after the frequency division, and a non-inverted signal of the signals after the frequency division. A second logic circuit that outputs a logical sum or a logical product;
A synchronizing signal selecting circuit comprising an AND circuit receiving the OR output of the first and second logical circuits or an OR circuit receiving the AND output of the first and second logical circuits; A second frequency divider for dividing an output signal of the circuit; a second input terminal receiving the output signal of the second frequency divider at the first input terminal and an external input signal at the second input terminal; A phase comparator that detects a phase difference between the output signal of the frequency divider and the external input signal and outputs a phase error signal corresponding to the phase difference between the two signals; and a high frequency range of the phase error signal supplied from the phase comparator. A high-speed tracking type PLL device comprising a low-pass filter that removes a component and outputs the signal as a control signal of the voltage-controlled oscillator.