JP2765232B2 - Semiconductor logic integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic integrated circuit, and more particularly to a semiconductor logic integrated circuit for high-speed operation.

[0002]

2. Description of the Related Art A conventional semiconductor logic integrated circuit (hereinafter referred to as logic I)
C), when evaluating the operation speed, generally, the clock frequency supplied to the logic IC is gradually increased, and the clock frequency when the output state does not match the expected value is set to the maximum operation frequency of the logic IC. Is defined as logical I
If the operating frequency of C is higher than the measurable frequency of the LSI tester, it cannot be evaluated.

For this reason, for example, as shown in FIG. 6, an oscillation circuit section 5 formed by connecting an inverter element 4 as a basic circuit element in series in an odd-numbered loop form, and an oscillation circuit section for lowering a measurement frequency. A circuit constituted by connecting a frequency dividing circuit section 6a for dividing the signal S5 from the section 5 to an IC chip as an auxiliary circuit for speed evaluation is provided separately from a function circuit for realizing a desired function by a logic IC. By measuring the oscillation frequency of this accessory circuit using a measuring instrument such as a synchroscope or a frequency measuring instrument, it was used as a measure to indirectly guarantee the operating speed of the original functional circuit of the manufactured logic IC. .

[0004]

In this conventional semiconductor logic integrated circuit, in order to guarantee the operation speed of the original functional circuit of the logic IC, the oscillation frequency of an accessory circuit for speed evaluation is measured by a synchroscope or a frequency measuring device. Since the measurement must be performed using a measuring device such as a tester, for example, a logic I
There is a disadvantage that the operating speed of C cannot be evaluated.

[0005]

A semiconductor logic integrated circuit according to the present invention comprises a functional circuit for realizing a predetermined function and an odd number of inverters as an auxiliary circuit for evaluating the operation speed of the functional circuit. An oscillation circuit unit connected in a loop, a frequency dividing circuit unit for counting a pulse signal of a predetermined oscillation frequency output by the oscillation circuit unit, and an input terminal to which a clock signal of a predetermined frequency is externally supplied. In a semiconductor integrated circuit integrally provided in a chip together with a functional circuit, the frequency divider circuit is reset in a first half cycle of a signal obtained by delaying the clock signal by a predetermined time, and is input in a second half cycle after reset release. Counting means for counting the pulse signal and outputting one of two logical levels if the value is equal to or greater than the value corresponding to the predetermined oscillation frequency. Ri, the accessory circuit means includes frequency discrimination means comprising a delay element to provide a flip-flop delay of the predetermined time to store the other hand level in response to the change timing of the late period after an edge of said clock signal, If the predetermined oscillation frequency is normal, the frequency
Number discriminating means outputs the one-level signal from the flip-flop.
Is output . Further, inputs a signal of the logical product result of the pulse signal and the clock signal to a count signal input terminal of the frequency division circuit portion, and, in place of the delay element, the signal for the reset from the clock signal A one-shot circuit portion to be generated can be used.

[0006]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a speed evaluation accessory circuit according to a first embodiment of the present invention. FIG. 2 is a schematic plan view of an IC chip having the speed evaluation accessory circuit of FIG. The auxiliary circuit 3 includes an oscillation circuit section 5 in which inverters 4 of inverting logic elements are connected in series in a 51-stage loop, and a frequency dividing circuit section in which flip-flop circuits are connected in series in four stages to form a 4-bit binary counter. And a frequency discriminating circuit section 10 comprising a delay element 7 for resetting the count value of the frequency dividing circuit section 6 and a flip-flop circuit 9 for storing the most significant bit 8 of the frequency dividing circuit 6.

FIG. 3 is a block diagram showing an input terminal of the block shown in FIG.
Clock signal CLK to be applied to output
9 is an operation timing chart of FIG. In the frequency dividing circuit section 6, the delay element 7 receiving the clock signal CLK is "Low".
The signal is reset when the signal is at the high level, and the signal from the oscillation circuit section 5 is counted when the signal is at the high level. The flip-flop circuit 9 stores and outputs the state of the most significant bit 8 of the frequency divider 6 at the rising edge of the clock signal CLK.

Therefore, the output signal Q of the flip-flop 9
1, Q2 and Q3 are inputted from the oscillation circuit unit 5 at t1, t2 and t3 from the time when the output signal of the delay element 7 rises and the reset of the frequency dividing circuit unit 6 is released to the time when the clock signal CLK falls. If the number of pulses is 8 or more, "H
If the number of pulses output from the oscillation circuit unit 5 per unit time is 8 or more, it is easy to determine whether the number is 8 or less. .

The delay time of inverter 4 is 0.1 nsec.
At this time, the delay of 51 stages for one round of the oscillation circuit unit 5 in this embodiment is 5.1 nsec, and the oscillation frequency at this time is about 100 MHz. To check this frequency,
A clock signal CLK of about 6.25 MHz having a half cycle of a delay value of about 80 nsec for eight pulses of the oscillation frequency is applied to the input terminal 11 and the output signal of the flip-flop 9 is set to “H”.
What is necessary is just to confirm that the i ″ level is maintained.

In the present embodiment, a 4-bit counter is used for the frequency dividing circuit 6. However, if the number of bits is increased and the clock frequency applied according to the count is adjusted, more accurate discrimination can be performed. Obviously.

In this embodiment, the clock frequency to be applied is specified in advance to determine the frequency. However, the clock frequency to be applied to the input terminal 11 is changed to change the output signal S9 of the flip-flop 9 from "Hi" level to "Hi". Lo
If the clock frequency at the time of changing to the w ″ level is obtained, the oscillation frequency of the oscillation circuit unit 5 can be obtained.

FIG. 4 is a block diagram of a speed evaluation accessory circuit according to a second embodiment of the present invention. The accessory circuit 3 of this embodiment includes an oscillation circuit section 4 and a frequency dividing circuit 6 as in FIG.
A two-input NAND gate 15 that interrupts / continues a signal S5 from the oscillation circuit unit 4 with a clock signal CLK from an input terminal 11, a one-shot circuit 16 that receives a clock signal CLK and outputs a one-shot pulse signal S16, and frequency division The circuit 6 includes a frequency discriminating circuit unit 10a including a flip-flop 9 for storing the most significant bit 8 of the circuit 6.

FIG. 5 is an operation timing chart of the clock signal CLK supplied to the input terminal 11, the output signal S15 of the two-input NAND 15, the output signal S16 of the one-shot circuit 16, and the output signal S9 of the flip-flop circuit 9.

The frequency dividing circuit 6 is reset by the "Low" pulse of the one-shot circuit 16, and receives the clock signal CLK.
Is "Hi" level, the signal S15 from the oscillation circuit section 4 coming through the two-input NAND 15 is counted.

For this reason, since the count times t1, t2 and t3 are just half the cycle of the clock signal CLK, the circuit configuration is slightly complicated, but the frequency can be determined more accurately than in the first embodiment. .

[0017]

As described above, according to the present invention, the per-unit-time speed evaluation circuit of the basic element provided separately from the original functional circuit for realizing the predetermined function as the semiconductor logic integrated circuit is provided. A frequency discriminating circuit that calculates the count value of the frequency divider circuit and then keeps the count state steadily is added, so that the frequency of the basic element circuit can be easily calculated without preparing a measuring device such as a frequency measuring device. Has the effect of being able to determine

[Brief description of the drawings]

FIG. 1 is a block diagram of a speed evaluation accessory circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic plan view of the semiconductor chip of the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the block in FIG. 1;

FIG. 4 is a block diagram of a speed evaluation accessory circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining the operation of the block in FIG. 4;

FIG. 6 is a block diagram for explaining an example of a conventional semiconductor logic integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC chip 2 Function circuit 3 Speed evaluation accessory circuit 4 Inverter element 5 Oscillation circuit part 6 Divider circuit part 7 Delay element 8 Most significant bit 9 Flip-flop circuit 10, 10a Frequency discriminating circuit 11 Input terminal 15 2-input NAND element 16 One shot circuit

Claims (2)

(57) [Claims] A functional circuit for realizing a predetermined function;
As an attached circuit means for evaluating the operation speed of this functional circuit, an oscillator circuit section in which inverters are connected in an odd-numbered loop, and a frequency divider circuit for counting a pulse signal of a predetermined oscillation frequency output from the oscillator circuit section A semiconductor integrated circuit having a unit and an input terminal to which a clock signal of a predetermined frequency is externally provided together with the functional circuit in a chip. The pulse signal is reset in the first half cycle of the delayed signal and is input in the second half cycle after the reset is released, and outputs one of the binary logic levels if the value is equal to or more than the value corresponding to the predetermined oscillation frequency. The attached circuit means responds to the change timing of the trailing edge of the latter half cycle of the clock signal. Comprising a frequency discriminating means consisting of a delay element to provide a flip-flop delay of the predetermined time to store the long said is normal predetermined oscillation frequency
Frequency discriminating means outputs the one-level signal from the flip-flop.
A semiconductor logic integrated circuit that outputs a bell . 2. A signal obtained as a logical product of the pulse signal and the clock signal is input to a count signal input terminal of the frequency dividing circuit unit, and the clock signal is output from the clock signal instead of the delay element. 2. The semiconductor logic integrated circuit according to claim 1, wherein a one-shot circuit unit for generating the reset signal is used.