JP2765862B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device suitable for an extremely large-capacity memory.

[Conventional technology]

First, a memory device having a conventional configuration will be described to explain the basic functions of the present invention. Conventionally, in a semiconductor memory device, a defect remedy method as shown in FIG. 12 has been used (Example 1).

An example of this is ISSC, Digest of Technical Papers, February 1981,
Pages 80 to 81 (ISSCC DIGEST OF TECHNICAL PA
PERS, February 1981, pp. 80-81).
In this example, a method of comparing an external address on a chip with a defective address written in an internal program element and selecting a spare memory is used.

That is, the specific external address signals X _0, X _1, ..., X _n transistors Q ₀ of the decoder in response to, ..., to constitute a program element to Q _n are all turned off, the specific external address signals X ₀ , X ₁ ,..., X _n , the node A goes high, and the spare memory is selected.

On the other hand, redundancy on a full wafer has been implemented in memory block units. Examples of this include IEE, Journal of Solid State Circuits, SC-15, Vol. 1, 4db, August 1980, pp. 677-686 (IEEE, Journal of Solid State Circuit). Solid-State Circuits
Vol.S-15, No.4 August 1980, pp.677-686) (Example 2).

In this method, an external controller is used to switch to a good memory block when a defect exists in an individual memory block. As described above, storage control of the bad block is required outside.

Also, as described in JP-B-46-25767 and JP-B-47-6534, the address of the defective bit is stored in the associative memory, the coincidence between the stored contents of the external address and the defective bit address is detected, and the new address is stored in the spare memory. A redundant method of outputting and reading a normal bit has been proposed (Example 3).

Furthermore, Japanese Patent Application Laid-Open Nos. 53-32633 and 53-32633 disclose inventions for reading out either the output from the main memory or the output from the spare memory in accordance with the result of comparison between the address of the memory access and the defective address. No. 56-134399.

[Problems to be solved by the invention]

A first problem common to the above prior arts is that the amount of spare memory is limited. For example, in Example 1, at most
A memory in which only about 10-bit defects can be remedied and failed to be remedied, or a multi-bit defective memory that cannot be remedied has been discarded. On the other hand, in order to increase the number of relief bits, the size of the redundant circuit increases, and the yield of the semiconductor memory device decreases.

The problem in the second conventional example is that, in the repair in memory block units, the amount of the spare memory used for the repair is large, and the occupancy of the spare memory on the wafer is increased. In other words, practical use is difficult due to the complexity of the defect remedy method and the external controller. On the other hand, when one memory block contains one defective cell, this memory block is replaced with another memory block. There is a problem that there are many.

A problem in the third conventional example is that an associative memory is used as an address translation device. This associative memory cell requires 8 to 10 transistors per cell, which further increases the logic around the memory device. Such an associative memory is expensive, and the price of the entire system becomes extremely expensive. On the other hand, the associative memory has a circuit configuration that stores an address of a defective bit, detects coincidence between an external address and the address of the defective bit, and outputs a new address of the spare memory, so that it is difficult to cope with an increase in the number of defective bits. There is.

Accordingly, it is a basic object of the present invention to provide a semiconductor memory device in which a method for relieving a defective bit is relatively simple and hardware for realizing the rescue is relatively simple. It is in.

Means for Solving the Problems An object of the present invention is to provide a semiconductor memory device, comprising: (1) a plurality of memory cells, the plurality of memory cells corresponding to a word line address signal and a data line address signal; And (2) a spare memory for relieving a defect of the main memory, and (3) the word line address signal is supplied to an input thereof and supplied to the spare memory. A word line address conversion unit for generating a spare word line address signal to be output at a first output thereof; and (4) a spare data line address signal supplied to the spare memory, the input of which is supplied with the data line address signal. And a data line address conversion unit that generates the first output from the semiconductor memory device (see FIGS. 1 and 2).

[Action]

When the word line address signal designates a word line having a defect in the main memory word line direction, the word line address conversion unit supplies the spare word line address signal to the spare memory, and the data line address signal is When designating a data line having a defect in the data line direction, the data line address converter supplies a spare data line address signal to the spare memory.

Therefore, a defect in the word line direction and a defect in the data line direction of the main memory can be remedied by the spare word line and the spare data line of the spare memory, respectively.

Further, the word line address conversion unit and the data line address conversion unit are general semiconductor memories of a multi-bit output format,
For example, non-volatile semiconductor memory (EPROM, EEPROM, fuse R
OM) or a semiconductor memory backed up by a battery (such as an SRAM with a battery-backed amplifier), and there is no need to use an associative memory as in the related art. As a result, defect repair of the main memory can be realized by a relatively simple method and hardware (see FIGS. 1 and 2).

Other objects and novel features of the present invention will become apparent from the embodiments described in detail below.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram for simply showing the principle of the semiconductor memory device of the present invention. In the figure, reference numeral 20 denotes a memory block chip for storing the upper part, 1 denotes a main memory which is a set of the block chips, 7, 8 denotes an address translation device, and 9, 1
0 indicates a spare memory. 2 is a data line address direction, 3 is a word line address direction, and 11 and 12 are spare address signals of the spare memories 9 and 10.

Next, the operation of this block diagram will be described. In the same figure, the defective line indicates each of the defective bits 13.
It is assumed that there are four or five defects in the word line direction (W1 and Wk in the figure) and six defects in the data line direction (D1 in the figure).

That is, in the block chip 20 of the main memory 1,
Since at least two memory cells 13a and 13b become defective bits in relation to the word line W1 (4), these defective bits 13a and 13b are defined as defective in the word line direction, and It is relieved by two spare memory cells related to word W1. Also, the data line D1
At least two memory cells 13c and 13d related to (6)
Are defective bits, so these defective bits 13c, 13d
Is defined as a defect in the data line direction, and is relieved by two spare memory cells related to the spare data line d1 of the spare memory 10. The defective bit cell 13e is not defined as a defect in the word line direction or a defect in the data line direction, but is originally defined as a bit defect. However, the defective bit cell 13e is regarded as a defect in the word line direction for convenience, and is relieved by one spare memory cell of the spare memory 9 related to the spare word line Wk.
The defective bit cell 13e can be regarded as a defect in the data line direction and can be relieved by the spare memory cell in the spare memory 10.

Inspection of all the memory cells in the block chip 20 of the main memory 1 is performed by scanning in the word line direction and scanning in the data line direction. This inspection and a method of relieving defects by writing a spare address signal and a failure detection signal to the address conversion devices 7 and 8 based on the inspection result will be described later in detail.

FIG. 2 is a block diagram for explaining the semiconductor memory device of the present invention in detail. In the figure, 1 is a main memory comprising one or a plurality of memory block chips, 7 and 8 are word line and data line address conversion units, respectively, 9 and 10 are spare memory for word line rescue and data line rescue, respectively. 108 is an input / output (I / 0) signal, 109 is a control signal of a memory device, 110 is a data line address signal (AX), 111 is a word line address signal (AY), 112 is a memory block selection signal (AZ). . Reference numerals 115 and 117 denote input / output signals (I / 0) of the address conversion units 7 and 8, respectively, which are defect detection lines. Also, 107
Is a priority determination circuit that receives the output and determines whether a word line address and a data line address fail simultaneously and determines the presence or absence of a defective address. Reference numeral 102 denotes an input / output switching circuit for switching between the input / output line 119 of the main memory 1 and the input / output line 120 of the spare memories 9 and 10. One is selected and connected to the common input terminal 108.

Since the main memory 1, the spare memories 9, 10 and the address conversion units 7, 8 have already been described in detail, next, referring to FIGS. 1 and 2, all the memory cells of the main memory 1 will be described. The defect inspection method by writing the spare address signal and the defect detection signal to the address conversion devices 7 and 8 based on the inspection result of the pass / fail and the inspection result will be described in detail.

That is, when a word line direction defect is detected for the word line W1 (4) by scanning the main memory 1 in the word line direction, the word line address signal 111 corresponding to the selection of the defective word line W1 (4). (AY) and a spare word line address signal 114 (ay) for selecting the spare word line W1 of the spare memory 9 at a plurality of addresses of the word line address conversion device 7 determined by the memory block selection signal 112 (AZ). And the word line defect detection signal 115 are written. Further, when a data line direction defect is detected for the data line D1 (6) by scanning the main memory 1 in the data line direction, the data line address signal 110 corresponding to the selection of the defective data line D1 (6) is detected. (AX) and a spare data line address signal 116 (ax) for selecting the spare word line d1 of the spare memory 10 at a plurality of addresses of the data line address converter 8 determined by the memory block selection signal 112 (AZ). And the data line defect detection signal 117 are written.

When the word line address signal 111 (AY) and the memory block selection signal 112 (AZ) corresponding to the selection of the defective word line W1 (4) of the main memory 1 are supplied, these signals (AY + A
Z), the spare word line address signal 114 (a
y) and the word line defect detection signal 115 are read in a multi-bit output format. Therefore, the spare word line W1 of the spare memory 9 is selected by the spare word line address signal 114 (ay), and the spare memory cell on the spare word line W1 is selected in response to the data line address signal 110 (AY). Defect relief is performed.

When the data line address signal 110 (AX) and the memory block selection signal 112 (AZ) corresponding to the selection of the defective data line D1 (6) of the main memory 1 are supplied, these signals (AZ + A
A spare data line address signal 116 and a data line defect detection signal 117 are read out in a multiple bit output format from a plurality of addresses of the data line address conversion device 8 determined by Z). Therefore, this spare data line address signal 116
The spare data line d1 of the spare memory 10 is selected by (ax), and the spare memory cell on the spare data line d1 is selected in response to the word line address signal 111 (AY) to execute the defect relief.

Therefore, in FIG. 2, the input / output switching circuit is usually used.
Reference numeral 102 designates the input / output line 119 of the main memory 1, but when a defective portion of the main memory 1 is selected, the failure detection signal 11
The input / output switching signal 118 is activated via the priority determination circuit 107 which responds to 5, 117, and selects the input / output line 120 of the spare memories 9, 10. That is, in FIG.
Reference numeral 08 denotes a common input / output (I / 0) terminal of the entire semiconductor memory device, through which digital information is written into memory cells in the main memory 1 or the spare memories 9 and 10 via the common input / output terminal 108. Meanwhile, digital information is read from the memory cells of the main memory 1 or the spare memories 9 and 10 via the input / output terminal 108.

FIG. 3 shows an EPROM (Electrica) in which the address conversion units 7 and 8 can be electrically written and which can be erased by ultraviolet rays.
FIG. 4 is a block diagram of an embodiment constituted by an address translation unit.
EEPROM that can electrically write and erase 7, 8
(Electrically Erasable and Programmable Read Only
FIG. 5 is a block diagram of an embodiment in which the address converters 7 and 8 are configured by SRAM (Static Random Access Memory) with a battery back-amplified. In particular, the circuit 5 switch in Figure 5 when the power supply V _A is interrupted, and supplies the voltage V _B of the battery to SRAM, the resulting loss of spare address signals 114, 116 and defect detection signals 115 and 117 held in the SRAM This is to avoid it. Note that these address conversion units 7 and 8 can use a nonvolatile memory such as a fuse type ROM.

FIG. 6 is a block diagram of a semiconductor memory device according to another embodiment of the present invention, which differs from FIG. 2 only in that a latch circuit 200 is added to the data line address conversion unit 8, and the other is the same as in FIG.
It is the same as the figure. As shown in FIG.
Are supplied with a data line address signal 110 (AX) and a memory block selection signal 112 (AZ), and an output line 202 of the latch circuit 200 is connected to an input / output line (I / 0) of the data line address converter 8. ) 116, 117 are connected. This latch circuit 20
By using 0, the spare data line address signal 116 and the data line defect detection signal 1
Writing with 17 becomes easy. That is, based on the inspection result of the main memory 1, the spare data line address signal 116 and the data line failure detection signal 117 are latched by the latch circuit 200 via the input line 201, and then the latch circuit 200 is output via the output line 202. From 200, the spare data line address signal 116 and the data line failure detection signal 117 can be written to a plurality of addresses of the data line address conversion unit 8. The plurality of addresses of the data line address conversion unit 8 where the writing is performed can be determined by the data line address signal 110 (AX) and the memory block selection signal 112 (AZ). Incidentally, in operations other than such a write operation,
The latch circuit 200 is controlled so as not to operate.

It goes without saying that a latch circuit similar to this latch circuit may be added to the word line data address conversion unit 7 and this latch circuit may be operated in the same manner as described above.

FIG. 7 is a block diagram of a semiconductor memory device according to another embodiment of the present invention. The data line defect detection signal 117 of the data line address converter 8 has a multi-bit format, and the decoder circuit 214 has a multi-bit format. The switch circuit 216 controlled by the data line defect detection signal 117 and controlled by the decode output signal 215 of the decoder circuit 214 selects the input / output line 213 of the spare memory 9 and
The difference from the embodiment of FIG. 2 is that the switch circuit 217 controlled by the 14 decode output signals 215 selects the input / output line 119 of the main memory 1 at the same time.
For example, if the semiconductor memory device of FIG. 7 has an 8-bit input / output (I / 0) configuration, the second and third I / Os are used as spare memory.
10 and the first and fourth to eighth main memories 1 can share.

FIG. 8 is a block diagram of a semiconductor memory device according to another embodiment of the present invention, and FIG. 2 is different from FIG. 2 in that a third spare memory 11 for relieving a memory cell of the main memory 1 having a bit defect is added. This is a difference from the embodiment of FIG. In the semiconductor memory device shown in FIG. 8, as shown in FIG. 9, in the case of bit defect repair, both the word line defect detection signal 115 and the data line defect detection signal 117 become "1" level, and the spare memory selection signal 403 becomes “1” level and the third spare memory 1
1 is selected.

FIG. 10 is a block diagram showing a semiconductor memory device according to another embodiment of the present invention. This figure shows the spare memory 414, new internal addresses (114, 116) output from the word line and data line address conversion units 7, 8 so as to remedy the word line and data line defects with one chip, and the new internal addresses (114, 116) applied to the semiconductor memory device. The difference from the embodiment shown in FIG. 2 is that an internal / external address switching circuit (406, 408) for switching between external addresses (110, 111) is added. In the semiconductor memory device of FIG. 10, in the case of the data line rescue failure mode as shown in FIG. 11, the word line failure detection signal 115 becomes "0" and the data line defect rescue signal 117 becomes "1" level, and the priority is given. The output 118 of the judgment circuit 107 becomes “0” level. As a result,
The external address switching circuit 406 has an external word line address A
Y is connected to spare memory address signal line 410.
To the word line address (ay) of the spare memory 414. Also, an internal / external address switching circuit 408
Is connected to the new internal data line address ax, and its output is connected to the spare memory 414 via the spare memory address signal line 412.
Data line address (ax). Further, the spare memory 414 is in the selected state because the chip select signal ▲ ▼ is at the “0” level, and the input / output switching circuit is similarly set.
At 102, the input / output signal 120 of the spare memory 414 is selected. With the above operation, defect relief is performed, and normal cells are read / written from / to the spare memory. Also, in the case of word line rescue, the word line defect detection signal 115 becomes "1" level and the data line defect rescue signal 117 becomes "0" level, and the same operation is performed. Further, in the case of the defect mode of the bit defect, the word line defect detection signal 115 is at the “0” level, the data line defect rescue signal 117 is at the “0” level, and the spare memory 414 has a new internal data line address ax and a new internal Word line address ay
Are connected, and defect relief is performed.

On the other hand, when the main memory 1 is in the normal mode of non-defective cells,
Both the word line defect detection signal 115 and the data line defect relief signal 117 become “1” level, and the output 118 of the priority determination circuit 107 becomes “1”.
Level, that is, the chip selection signal of the spare memory 414
▼ becomes “1” level, and is in a non-selected state. Further, in the input / output switching circuit 102, the input / output line 119 on the main memory 1 side is selected, and a normal memory cell is read / written.

In the above description, for example, a memory having the same configuration as the main memory 1 is used as the spare memory 414, and the left memory array of the X decoder of the same memory is allocated for data line defect relief, and the right memory array is allocated for word line defect relief, One to several line relief lines or word line relief lines are allocated for bit defect repair. Thus, three failure modes of a data line defect, a word line defect, and a bit defect can be relieved by one chip, and the use efficiency of the spare memory used for the rescue can be improved. Further, the expansion of the spare memory chip in the present embodiment can be performed by first increasing the number of failure detection bits in the address conversion unit and controlling the additional memory chip selection signal based on the information of the bits.

FIG. 10 shows the advantage that the spare memory may be one chip as described above, and the number of wires between the spare memory and the redundant control circuit is smaller than that of FIG. have. Therefore, it is suitable for a relatively small-capacity semiconductor memory device.

〔The invention's effect〕

The spare memories 7, 8, 414 for relieving a defect in the main memory 1 can be constituted by a general semiconductor memory of a multi-bit output format, the method of relieving defective bits is relatively simple, and this remedy is realized. It is possible to provide a semiconductor memory device in which the hardware for performing the operation is relatively simple.

[Brief description of the drawings]

FIG. 1 is a block diagram for simply showing the principle of the semiconductor memory device of the present invention, FIG. 2 is a block diagram for explaining the semiconductor memory device of the embodiment of the present invention in detail, and FIG. FIG. 4 is a block diagram of an embodiment in which the address conversion unit is configured by an EPROM, FIG. 4 is a block diagram of an embodiment in which the address conversion unit of FIG. 2 is configured by an EEPROM, and FIG. 5 is a block diagram of the address conversion unit in FIG. 6 to 8 are block diagrams each showing a semiconductor memory device according to another embodiment of the present invention, and FIG. 9 is an operation of the embodiment of FIG. FIG. 10 is a block diagram showing a semiconductor memory device of another embodiment of the present invention, FIG. 11 is a state diagram for explaining the operation of the embodiment of FIG. 10, and FIG. The figure shows a conventional semiconductor memo It is a block diagram for explaining the device.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Osamu Minato, Inventor 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-198348 (JP, A) JP-A-57 JP-A-179998 (JP, A) JP-A-60-160100 (JP, A) JP-B-57-32440 (JP, B2) (58) Fields investigated (Int. Cl. ⁶ , DB name) G11C 29/00 603 G11C 16/06

Claims (7)

(57) [Claims] 1. A semiconductor memory device comprising: (1) a plurality of memory cells, and a predetermined memory cell is selected from the plurality of memory cells in response to a word line address signal and a data line address signal; (2) a spare memory for relieving a defect in the main memory; and (3) a word line address signal supplied to an input of the spare memory, and a spare word line address signal supplied to the spare memory. A word line address conversion section generated at the first output; and (4) the data line address signal is supplied to the input thereof, and the spare data line address signal supplied to the spare memory is generated at the first output. The spare memory comprises first and second spare memories, and the data line address signal and the word line address converter are provided. The generated spare word line address signal is supplied to the first spare memory, and the word line address signal and the spare data line address signal generated by the data line address conversion unit are sent to the second spare memory. A semiconductor memory device, which is supplied. 2. The semiconductor memory device according to claim 1, wherein said main memory comprises a plurality of memory chips, said spare memory comprises a memory chip different from said main memory, and said word line address converter. Generates, at a second output thereof, a word line defect detection signal indicating the presence of a defective memory cell of the main memory related to the word line address signal, wherein the data line address conversion unit outputs the data line address signal. Generating a data line defect detection signal at its second output indicating the presence of a defective memory cell in the main memory, the common input terminal and the word line defect detection signal generated by the word line address converter. And the input / output line of the main memory or the spare memory in response to the data signal and the data line defect detection signal generated from the data line address conversion unit. The semiconductor memory device characterized by further comprising one of the output lines and input and output switching circuit connected to the common input-output terminal. 3. The semiconductor memory device according to claim 1, wherein said plurality of addresses of said word line address conversion unit are determined by said word line address signal. The spare word line address signal for selecting a spare word line of the spare memory is written, and spare data of the second spare memory is stored in a plurality of addresses of the data line address conversion unit determined by the data line address signal. A semiconductor memory device wherein the spare data line address signal for selecting a line is written. 4. The semiconductor memory device according to claim 1, wherein said word line address conversion section and said data line address conversion section are constituted by a semiconductor memory of a multi-bit output format. A semiconductor memory device. 5. The semiconductor memory device according to claim 4, wherein said address conversion unit electrically writes and erases data by an EEPROM, and electrically writes and erases data by ultraviolet rays.
EPROM, fuse ROM, or battery-backed SRAM
A semiconductor memory device comprising: 6. A main memory having a plurality of memory cells, wherein a predetermined memory cell is selected from the plurality of memory cells in response to a word line address signal and a data line address signal. A chip, a spare memory chip for relieving a defect of the main memory chip, a common input / output terminal for inputting / outputting a signal of the main memory chip and the spare memory chip, and the word line address signal is supplied to the input. A spare word line address signal supplied to the spare memory chip is generated at a first output thereof, and a word line defect detection signal indicating the presence of a defective memory cell of the main memory is outputted to a second output thereof.
A word line address conversion unit generated at the output of the memory cell, wherein the data line address signal and the spare word line address signal generated by the word line address conversion unit are supplied to the spare memory, An input / output switching circuit for connecting either the input / output line of the main memory or the input / output line of the spare memory to the common input / output terminal in accordance with the word line defect detection signal generated from the unit. A semiconductor memory device characterized by the above-mentioned. 7. A main memory having a plurality of memory cells, wherein a predetermined memory cell is selected from the plurality of memory cells in response to a word line address signal and a data line address signal. A chip, a spare memory chip for relieving a defect of the main memory chip, a common input / output terminal for inputting / outputting signals of the main memory chip and the spare memory chip, and the data line address signal being supplied to the input. A spare data line address signal supplied to the spare memory chip is generated at a first output thereof, and a data line failure detection signal indicating presence of a failed memory cell of the main memory is transmitted to a second output thereof.
A data line address conversion section generated at the output of the memory cell, wherein the word line address signal and the spare data line address signal generated by the data line address conversion section are supplied to the spare memory; An input / output switching circuit for connecting either the input / output line of the main memory or the input / output line of the spare memory to the common input / output terminal in accordance with the data line defect detection signal generated from the unit. A semiconductor memory device characterized by the above-mentioned.