JP2770565B2 - Music synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a musical sound synthesizer suitable for use in synthesizing musical tones such as plucked string instruments and stringed musical instruments, and providing various acoustic effects. 2. Description of the Related Art Conventionally, synthesis of musical tones by delayed feedback type attenuation sound synthesis has been known. FIG. 8 shows a delay feedback type tone synthesizer constituted by a digital circuit. In this figure, first, tone waveform data is supplied to an adder 1. The adder 1 adds the musical tone waveform data and the musical tone waveform data to be fed back to be described later, supplies the resultant to the shift register 2, and takes out the combined musical tone waveform data. Next, the shift register 2 functions as delay means, outputs musical tone waveform data at every predetermined delay time, and the filter 3 feeds back to the adder 1 via the multiplier 4. Since the shift register 2 operates as a delay circuit, the tone waveform data fed back to the adder 1 has a time delay element. That is, the delay feedback type tone synthesizer synthesizes a variety of tones (temporarily changes the volume and tone) by changing the tone waveform data over time. [Problem to be Solved by the Invention] By the way, the larger the number of bits of the above-mentioned musical sound waveform data, the smaller the quantization noise, and the musical sound waveform synthesized in the device approaches a more natural musical sound waveform. However, when the number of bits is increased, the storage capacity of a shift register, a separately provided storage device, or the like must be increased, which causes a problem of increasing costs. Also, if the number of bits of musical tone waveform data to be processed is reduced in order to avoid an increase in cost, the proportion of quantization noise in the output waveform increases as the waveform attenuates, causing a problem of distortion. The present invention has been made in view of the above-described problems, and provides a tone synthesizer capable of reducing the number of bits without increasing quantization noise and reducing the size of shift registers and storage devices. [Means for Solving the Problems] In order to solve the above-described problem, the invention according to claim 1 converts musical tone waveform data having a predetermined number of bits into digital data in a floating-point format. Floating-point conversion means for adding random number data at the time of the conversion, tone processing means for processing and outputting the digital data in the floating-point format as musical sound waveform data, and floating-point format output by the tone processing means. And linear conversion means for converting musical tone waveform data into linear data. According to a second aspect of the present invention, in the first aspect of the present invention, the floating point conversion means reduces bits correlated with the sign bit when converting the digital data into floating point digital data. . According to the invention, random number data is added to musical tone waveform data having a predetermined number of bits when the data is converted into digital data in a floating point format by the floating point conversion means. Next, the digital data in the floating-point format is processed as musical sound waveform data by musical sound processing means, and various sound effects are provided. Then, the floating point digital data output by the musical tone processing means is converted to linear data by the linear conversion means. In this case, since the random number data is added to the musical tone waveform data, the quantization error is reduced. According to the second aspect of the present invention, in the first aspect of the present invention, when the musical tone waveform data is converted into digital data in a floating point format by a floating point converting means,
Bits correlated with the code bits are reduced and compressed. "Example" Next, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In this figure, reference numeral 5 denotes a floating converter, which adds dither (hereinafter referred to as a random number) when converting externally supplied linear data into floating-point floating data. Also, in this example,
The 2's complement format linear data is 27 bits, and the floating point format floating data is 16 bits. Here, a method of converting linear data into floating data will be described with reference to FIG. The two's complement digital data has a sign bit. Normally, when this linear data is converted to floating data, one bit is generated by inverting the sign bit having exactly the same information as the sign bit. One of the features of the present application is to reduce the unnecessary bits and contribute to the reduction of the number of bits. Next, an example shown in FIG. 2 will be described. For example, two-complement linear data with a positive sign bit of “00000011111” has a sign “0”, a mantissa part “11111”, and a shift amount “6” in the floating-point format. Further, the linear data “00011101000” has a code “0”, a mantissa part “11101”, and a shift amount “3”. Here, the shift amount is the number of bits until the bit is inverted when viewed from the most significant bit MSB. Therefore,
The MSB of the mantissa always has the sign bit inverted. Next, an example of linear data having a minus sign will be described. The linear data “11111100000” has a code “1”, a mantissa “00000”, and a shift amount “6”. The linear data “11100010111” has a code “1”, a mantissa part “00010”, and a shift amount “3”. Also in this case, as in the case where the code is “0”, the MSB of the mantissa always becomes the code bit inverted. As a result, when the linear data is converted to the floating-point format, the most significant bit MSB of the mantissa is deleted, and for example, in the first example, the sign “0”, the mantissa “1111”, and the shift amount “6” And can be handled as data with one bit reduced. The bits that can be reduced are called hidden bits. Also, when returning floating-point format data to linear data, the sign bit can be inverted and added to the most significant bit MSB of the mantissa to restore the data without destroying the information. Next, regarding the configuration of the floating converter 5, the third
This will be described with reference to the block diagram shown in FIG. In the figure,
An exclusive OR circuit 5a performs an exclusive OR operation on the most significant bit MSB of the linear data described above and each of the other 26 bits, and outputs the result to the priority encoder 5b. That is, the exclusive OR circuit 5a inverts negative data by the above logical operation. The priority encoder 5b converts the sign-inverted data into the most significant bit MSB of the data.
From how many bits, the same value as the sign bit continues,
The data is output to the shift table 5c as 4-bit shift data. This shift data is the shift amount of the floating-point format data described above. This count value becomes the exponent part of the floating data. Next, shift table 5c
Converts the bits into data indicating how many bits should be shifted up in accordance with the shift data, and outputs this to the upshift 5d. The upshift 5d shifts up the linear data according to the above data, and moves the mantissa to the upper bits. This up-shifted 27-bit data is
It is supplied to one input terminal of the full adder 5e. In the full adder 5e, a random number R is added to the up-shifted data. This is to compensate for information on bits that are truncated other than the mantissa when converting to floating data. If a very large random number R is added, data information is lost. Therefore, in this embodiment, the random numbers R
Of the bits, the upper 13 bits are set to “0”, and only the lower 14 bits have a value. This random number R is supplied to the other input terminal of the full adder 5e. Full adder 5e
Adds the data and the random number R and outputs the result of the operation. In addition, the full adder 5e includes an overflow protector (not shown). In the above-described operation, if data overflows, a carry bit is generated, and the mantissa part is largely changed due to carry. I will. Therefore, in the present embodiment, a carry bit is detected by the overflow protector, and overflow of the mantissa is prevented. The result of the above operation includes the most significant bit MSB representing the code, the lower-order hidden bit, and the lower-order 11 bits having information on the mantissa. Therefore, only the hidden bit is truncated, and the remaining 12 bits (the most significant bit MS
B and mantissa) and the priority encoder 5
The 4-bit exponent part output by b is supplied to the shift register 6 shown in FIG. 1 as 16-bit floating data. The shift register 6 corresponds to, for example, a sound source delay circuit including the delay feedback circuit 10 described above or described below. The floating data is supplied to the linear change unit 7 after being delayed for a predetermined time. FIG. 4 shows an example of the configuration of the linear converter 7. In this figure, a linear converter 7 is a well-known circuit, and is composed of a shift register 7a. By linearly converting floating data by shifting down 4 bits of an exponent part as a count value and 12 bits of a mantissa part by a count value. Convert to data.

APPLICATION EXAMPLE 1 Next, the floating converter 5 and the linear converter 7 described above are replaced with a conventional delay feedback circuit shown in FIG.
The case where the present invention is applied to an electronic musical instrument having 10 will be described with reference to a block diagram shown in FIG. In this figure, a floating converter 5 is an adder 1
Is inserted in the previous stage. The tone waveform data is added to dither (random value) by the floating converter 5 and converted to 16-bit floating data, and then supplied to the adder 1. The tone waveform data output from the delay feedback circuit 10 is supplied to the linear converter 7. The linear converter 7 converts the musical tone waveform data into 27-bit linear data again, and then supplies the linear data to a subsequent sound system (sound generation circuit) or the like. Note that a storage device may be inserted between the floating converter 5 and the adder 1. The storage device temporarily stores floating data, and the data is supplied to the delay feedback circuit 10 at a predetermined timing. Next, the results according to this embodiment will be described with reference to the waveform diagrams shown in FIGS. 6 (a) and 6 (b). The difference between the waveform of the synthesized sound by the conventional delay feedback circuit 10 (large amplitude) and the original waveform, that is, the waveform indicating the error (small amplitude)
And FIG. 6 (a). FIG. 6 (b) shows a waveform of the synthesized sound according to the present embodiment (a large amplitude) and a waveform indicating an error (a small amplitude). Note that the error waveform is enlarged 200 times. In addition, as the initial input waveform supplied to the floating converter 5, a SIN wave having a cycle matching the delay time of the delay feedback circuit 10 is used. In a conventional circuit, noise having a period twice as long as the fundamental tone is generated,
When produced as a musical tone, it has a relatively audible component consisting of harmonics and uncorrelated noise. On the other hand, in the circuit according to the present embodiment, since the average of the error component becomes “0” due to the addition of the random number R, the looping is repeated while the tone waveform data is smoothed by the low pass of the delay feedback circuit 10. At some point, the error component is almost eliminated. As a result, the error becomes small in absolute value, and the noise becomes uncorrelated noise that is inconspicuous to the audibility.

[Application Example 2] Next, another embodiment will be described with reference to a block diagram shown in FIG. In this embodiment, the floating converter 5 and the linear converter 7 are applied to a well-known IIR filter 11. Reference numerals 10 and 10 denote shift registers which operate as delay circuits for time-division multiplexing of 16 channels. In the case of this embodiment, the floating converter 5 and the linear converter 7
Are interposed before and after the shift registers 10 and 10 and converted to floating-point data having a reduced number of bits, supplied to the shift register 10, and output from the shift register 10. To return to linear data. Thus, when the same hardware is applied to a time-division multiplexed circuit, the effect of register reduction is great. Note that the data bit width in the above-described embodiment is
Any other numerical value may be used as long as the magnitude relationship and the addition / subtraction relationship are preserved. Further, the bits to be added as the random number R do not need to generate all the bits, but may only generate the upper few bits of the random number bits. Further, the shift operation may be performed after the random number is added first. Further, the above-described embodiments may be executed by a microprogram or software. Also, when a random number R is added and a carry occurs,
The exponent may be incremented and the mantissa may be shifted down by one bit. Further, the present application is not limited to the embodiment, and may be used for a digital filter, a sound effect device, a sound field effect device, an envelope generator, and the like. The format of the numerical representation is two's complement, one's complement,
It may be a SIN amplitude or a radix other than binary (such as decimal). [Effects of the Invention] As described above, according to the first aspect of the present invention, random number data is added when converting musical tone waveform data into digital data in a floating-point format. Can be reduced. According to the second and third aspects of the present invention, when converting musical tone waveform data into digital data in a floating-point format, the number of bits is reduced because bits correlated with code bits are reduced and compressed. Therefore, the advantage that the shift register, the storage device, and the like can be reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention,
2 is an explanatory diagram of the linear-floating conversion, FIG. 3 is a block diagram showing the configuration of the floating converter in FIG. 1, FIG. 4 is a block diagram showing the configuration of the linear converter 7 in FIG. FIG. 5 is a block diagram showing a configuration in a case where the delay feedback circuit 10 is used as a first application example, and FIG. 6A is a conventional delay feedback circuit.
FIG. 6 (b) is a waveform diagram showing the synthesized sound waveform and the error waveform in FIG. 5, and FIG. 7 is a IIR filter 11 as a second application example. FIG. 8 is a block diagram showing a configuration of a tone synthesizer using a conventional delay feedback circuit 10. As shown in FIG. 5. Floating converter (floating point conversion means),
6 shift register (music processing means), 7 linear conversion unit (linear conversion means), 10 delay feedback circuit (music processing means), 11 IIR filter (music processing means).

Claims (2)

(57) [Claims] 1. Floating point conversion means for converting musical tone waveform data having a predetermined number of bits into digital data in a floating point format and adding random number data at the time of the conversion, and converting the digital data in the floating point format into a musical tone. A tone synthesizer comprising: tone processing means for processing and outputting as waveform data; and linear conversion means for converting floating-point tone waveform data output by the tone processing means into linear data. 2. The tone synthesizer according to claim 1, wherein said floating-point conversion means reduces bits correlated with a sign bit when converting the digital data into floating-point digital data.