JP2774565B2 - Image reduction device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reducing apparatus that converts pixel density of binarized image data to obtain reduced image data of an original image.

2. Description of the Related Art Conventionally, an original image binarized as an image reduction method is divided into blocks composed of a required number of pixels, and the number of white or black pixels in the block is counted. A majority decision method in which the value of a pixel that closes a majority of the total number of pixels is obtained as the value of the corresponding pixel of the reduced image, or a low-pass filter is applied to the pixels in the block, and the result is binarized with a threshold to obtain the value of the relevant pixel. A known method (for example, a projection method) is known.
However, this means that the density information of the image is relatively easy to be stored even in a reduced image, but in an image containing characters and line figures, thin lines are lost and details are lost, information is lost, and the image quality and quality of the reduced image are reduced. Had been lowered.

[Problems to be Solved by the Invention] Further, in the above-mentioned conventional example, since an input image is reduced as it is because a thin line, especially a character or the like is often formed of a black thin line, a case where the input image is once negative-positive There is a disadvantage that the state of information storage is different in a reduced image when the image is reduced after inversion.

Here, an example will be described using a configuration in which the image size is reduced to half by the projection method. The low-pass filter used in the projection method has a weight coefficient as shown in FIG. A reduced image having an image size of 1/2 can be created by performing filtering by matching the center of the filter with the o mark shown in FIG. 12 and binarizing the result to a threshold of 8/16.

Here, it is assumed that the detection of the line segment is performed by the 3 × 3 pixel block of the low-pass filter. FIGS. 13 (a) and 13 (b) show examples of line segments.
Shown in In FIG. 13 (a), this is a portion like the intersection of each line segment of the character "K", and even if binarization is performed using the result of the low-pass filter, the result is "black", which is a desirable result.

However, the original image shown in FIG. 13 (b) is, for example, a part of a circular arc, and becomes "white" when binarized by the result of the low-pass filter, which is not a preferable result. Therefore, this is corrected and the result is set to “black”.

Thus, (a) and (b) show the block in which the inside of the block is negative-positive reversed. However, when creating a reduced image, the same method may be suitable for one or the other. is there. That is, if the same processing is performed on a negative image as a positive image, if the character image of the original image is a negative image such as a microfilm, white thin lines of characters lose information due to the disappearance of the thin lines. There were drawbacks.

[Means for Solving the Problems] The present invention has been made in view of the above points, and an apparatus for reducing the image size of binarized image data includes:
A means for externally inputting or detecting image attribute information from an input image; a reducing means for performing reduction processing on image data; and a means for inverting image data before the reducing means; The present invention provides an image reducer in which the attribute of image data input to the reduction means is constant by inverting image data having a specific attribute according to the following.

[First Embodiment] FIG. 1 is a block diagram of a reduction apparatus to which the present invention is applied. In FIG. 1, reference numeral 1 denotes a frame memory for storing an original image; An image reducer 5 suitable for an image is a frame memory for storing the reduced image. The image is a binary image with 1 for black and 0 for white. The image data from the frame memory 1 is input to the negative / positive inverter 2 via a 1-bit data line 11 in the order of raster in units of pixels. The negative / positive inverter 2 determines whether an input image is a negative image or a positive image via a 1-bit signal line 15 from outside.
Receive N / P signal. The N / P signal may be input by the user, or may be added to the image as an image attribute in advance.

FIG. 4 shows a configuration example of the negative / positive inverter 2. Data line
22 is the data line 11 in FIG. 1, and the signal line 22 is the signal line 15 in FIG. 20 is an exclusive OR (XOR) circuit. The N / P signal is input to the XOR circuit 20 via the signal line 22.
The N / P signal is 0 when the input image is a positive image, and 1 when the input image is a negative image. When the N / P signal is 0, the XOR circuit 20
The input from the data line 21 is output to the data line 23 as it is, and when the N / P signal is 1, the input from the data line 21 is inverted to
Output to 23. As a result, the image data output from the data line 23 is all positive image data.

This hoji image data is sent via the data line 12 to the image reducer 3.
Is input to FIG. 5 is a detailed configuration example of the image reducer 3. Here, a projection method and a method having its correction means will be described as an example. Also, the size of the reduction will be described by 1/2. The data line 40 is the data line 12 in FIG. 30a
.About.c is a line buffer, which is composed of a FiFo memory or the like. 31a to i are 1-bit latches, 32 is a low-pass filter, and 33 is a line segment detector. Lowpass filter 3
2. The line segment detector 33 can be realized by a look-up table (LUT) constituted by a ROM, for example. Numeral 34 denotes a negative / positive inverter, and numeral 35 denotes a latch which operates at a cycle twice as long as the pixel clock.

As the image data input from the data line 40, data for three lines is stored using the line buffers 30a to 30c.
The latches 31a to 31i latch the pixel data output from the line buffers 30a to 30c to create a 3 × 3 pixel block as a whole.

The LUT of the low-pass filter 32 applies a low-pass filter as shown in FIG. 11 to the 3 × 3 pixel data from the latches 31a to 31i, and binarizes the image data at a threshold of 8/16 to the data line 41. Output.

The LUT of the line segment detector 33 is 3 LUTs from the latches 31a to 31i.
Nine pixels in a block of × 3 pixels are input as a 9-bit address. This LUT has a line segment in the pixel block, and the result of binarization by applying a low-pass filter to this pixel block does not reproduce the line segment, that is, when correction is required, 1 is output to the data line 42. If no correction is required, 0 is output.

The negative / positive inverter 34 can be realized with the same configuration as the negative / positive inverter in FIG. That is, in the detailed view of FIG. 4, the output from the low-pass filter 32 is input from the data line 21, the output from the line detector 33 is input from the signal line 22, and the input is inverted only when correction is necessary. The output of the negative-positive inverter 34 is input to the latch 35 via the data line 43, and the data is latched twice at the cycle of the pixel clock, that is, at the center position of the filter shown in FIG. Sub-sampling in the main scanning direction is realized. The sub-sampling in the sub-scanning direction can be realized by ignoring data for one line using a line counter (not shown).

This result is output from the data line 44 (the data line 13 in FIG. 1). In this manner, a reduced positive image is obtained via the data line 13, but it is necessary to perform positive / negative inversion of the input image with a negative image. Therefore, the output of the image reducer 3 is input to the negative / positive inverter 4. This means that a signal having the same function as the negative / positive inverter 2 is input to the N /
It can be realized by operating with the P signal.

In this way, if the original image is a negative image, it is converted to a positive image and reduced, so that the image reducing unit 3 for reducing the positive image is used to reduce not only the positive image but also the negative image. A reduction process that leaves information such as a white or black thin line can be executed. Here, the detection of line segments has been described, but it is of course possible to detect dither and the like.

Thereby, it is possible to create a reduced image with better image quality, regardless of whether the attribute of the image is negative or positive.

[Second Embodiment] A case in which the attributes of an image are not known in advance unlike the first embodiment described above will be described below. FIG. 2 is a block diagram for realizing this. Reference numeral 101 denotes a frame memory storing an original image, 102 and 104 denote negative / positive inverters, 103 denotes an image reducer, 105 denotes a frame memory for storing a reduced image, and 106 denotes a negative / positive determiner.

The image data stored in the frame memory 101 is input to the negative / positive determiner 106 via the data line 111. FIG. 6 is a detailed block diagram of the negative / positive judgment unit 106. 1
20 is a NOT circuit, 121 and 122 are counters, and 123 is a comparator. The counters 121 and 122 are first reset to 0 and the data line 1
Image data is read sequentially from 25. The counters 121 and 122 count the number of 1s input. Since the pixel data input to the counter 121 is inverted by the NOT circuit 120, the counter 121 counts white pixels, and
Reference numeral 22 counts black pixels.

This is performed for all or part of the original image, and the final count value is transmitted from the data lines 126 and 127. The comparator 123 compares the obtained number of black and white pixels. If the number of white pixels is large, it is determined that the image is a positive image. If the number of black pixels is equal or large, the negative image is output. Is determined, and 1 is output.

The output signal is supplied to the negative / positive inverters 102 and 104 via the signal line 115 as the N / P signal described in the first embodiment.

Next, the original image data from the frame memory 101 is sequentially transferred from the beginning in the main scanning direction via the data line 111 to the negative / positive inverter 1.
Enter in 02. The negative / positive inverter 102 may be exactly the same as that of the first embodiment, and the description is omitted. Negative / positive inverter 10
The output of 2 is always a positive image, and this data is
The signal is input to the image reducer 103 through 12.

FIG. 7 is a detailed configuration example of the image reducer 103. Although the image reducer shown in FIG. 5 may be used as the image reducer, here, a majority decision method and a method having its correction means are taken as an example.
In order to simplify the explanation, the size of the reduction will be described as 1/3.

The data line 90 is the data line 112 in FIG.
Is a 1-bit latch.
The method of forming a 3 × 3 pixel block using these is the same as in the first embodiment. 82 is a counter, 83 is a line segment detector, 84 is a comparator, 85 is a negative / positive inverter, and 86 is a latch.

The counter 82 counts the number of black pixels in the 3.times.3 pixel block from the latches 81a to 81i and inputs the counted number to the comparator 84 via the data line 91. The comparator 84 checks whether or not the number of input black pixels is a majority. If the number is a majority, the comparator 84 outputs 1 indicating a black pixel to the data line 92, and otherwise outputs 0.

Negative / positive inverters for line segment detectors 83 and 85, and latch 86
The operation and configuration are the same as those of the line segment detector 33, the negative / positive inverter 34, and the latch 35 of the first embodiment, and a positive reduced image is obtained from the data line 95. The negative / positive inverting unit 104 converts the positive image into the original image attribute. The negative / positive inverting unit 104 also executes the conversion based on the N / P signal from the negative / positive determining unit 106.
This makes it possible to obtain a high-quality reduced image 105 that does not depend on the attributes of the image even when the attributes of the image are not known in advance.

[Third Embodiment] Hereinafter, a description will be given of an embodiment of a hierarchical encoding method in which an image is hierarchically repeatedly encoded several times by using the reduction device described in the first and second embodiments. . FIG. 3 is a block diagram for realizing this. 50a to 50c are frame memories, 51 is an input / output selector, 52 is a negative / positive inverter, 53 is an image reducer, and 54 is an encoder.

The data line 60 is an image input device such as a scanner (not shown).
Alternatively, a binarized image is input from another frame memory, a recording medium (not shown), or the like. The input original image data is first stored in the frame memory 50a. Hierarchical reduction of an image is generally performed at the same reduction ratio. Here, it is set to 1/2. First, in the first stage of the hierarchical minute, the frame memory 50a
The original image stored in the
Let's follow the operation of each block for the case of storing in. The input / output selector 51 connects an output data line 62 of the original image data and a data line 70 output from the frame memory 50a from a controller (not shown) via a signal line 61, and outputs the minute image data from the image minute device 53. And the input data line 71 to the frame memory 50b.

As a result, the original image data from the frame memory 50a is input to the negative / positive inverter 52 via the data line 62. Here, the negative / positive inversion is performed by an N / P signal obtained by the first or second embodiment and indicating the attribute of the original image data input from the signal line 63. Therefore, only the positive image data is output from the data line 64. The positive image data is input to the image miniaturization device 53 via the data line 64, subjected to the reduction processing of the reduction type 1/2 as shown in the first embodiment, and output to the data line 65. The reduced image data is input to the input / output selector 51 via the data line 65, and stored in the frame memory 50b via the data line 71. In this way, all the 1/2 reduced image data is stored in the frame memory 50b.

Next, the second stage of the hierarchical minute is performed. The input / output selector 51 is controlled by a control signal input via a signal line 61 to 1 /
(2) The output data line 72 of the frame memory 50b storing the reduced image data is connected to the data line 62, and the input data line 65 of the 1/4 reduced image data is connected to the input data line 73 of the frame memory 50c. Connect. 1 from frame memory 50b
The / 2 reduced image data is transmitted via a data line 62 to a negative / positive inverter 52.
Is input to Here, since the 1/2 reduced image data is a positive image, a signal representing a positive image is input to the signal line 63, and the negative / positive invertor 52 passes the image data as it is, and the image Enter 53. The image reducer 53 performs a 1/2 reduction process to obtain a reduced image having a 1/4 image size with respect to the original image, and transfers the reduced image to a frame memory via a data line 65, an input / output selector 51, and a data line 73. 50c
To be stored.

With this operation, the original image, the 1/2 reduced image, and the 1/4 reduced image can be stored in the frame memories 50a, 50b, and 50c, respectively. Next, when encoding, the frame memory
The 1/4 reduced image data stored in 50 c is connected to the data line 74 and the data line 62 by the input / output selector 51 and input to the negative / positive reactor 52. This time, the signal input from the signal line 63 is for performing conversion to the original image attribute. Therefore, since the 1/4 reduced image data is a positive image, if the original image is a positive image, the input from the signal line 63 is 0, and the 1/4 reduced image is directly passed through the data lines 64 and 66 to the encoder 54. Is input to Conversely, if the original image is a negative image, the input from the signal line 63 is 1, and the input image data is inverted and input to the encoder 54.

The encoder 54 is coded by a coding method of binary information (for example, the MMR method) and is output to the communication line 67.

After that, the 1/2 reduced image stored in the frame memory 50b is similarly input to the data lines 72 and 62 by the input / output selector 51.
Is input to the negative / positive inverting device 52, and if necessary, similarly, converted to the attribute of the original image, input to the encoder 54 via the data lines 64 and 66, encoded and output to the communication line 68. .

Finally, the original image data stored in the frame memory 50a is connected to the data line 70 by the input / output selector 51.
The signal is input to the negative / positive inverter 52 via 62. This time, since the input is the original image data, the signal input via the signal line 63 indicates a positive image and the negative / positive inverter 52 passes the original image data as it is and inputs it to the encoder 54 via the data lines 64 and 66. The encoded data is output to the communication line 67 and a series of hierarchical encoding processes is completed.

In this way, application to hierarchical coding is also possible,
At this time, the transmitted reduced image can maintain high image quality.

Fourth Embodiment Next, unlike the second embodiment, unlike the case where the attribute of the image is determined before the start of the processing, an embodiment in which the attribute is sequentially determined at the time of reduction is described. Further, in this embodiment, the output of the low-pass filter is corrected by referring to the already-subsampled reduced pixels.

FIG. 9 is a block diagram for realizing this. 20
1a-c are line buffers, 202a-i are latches, 203a-c
Is a run length counter, 204 is an attribute determiner, 205a, b and 209 are negative / positive inverters, 206 is a low-pass filter, 207 is a corrector, 208 is a determiner, 210 and 213 are latches, and 211a and 211b are line buffers of reduced images. .

The reduction method uses a low-pass filter, and a method of correcting a pattern that cannot be reproduced by the low-pass filter will be described as an example. Also, here, we will proceed with the reduced size set to 1/2.

When the low-pass filter shown in FIG. 11 is applied to the input as shown in FIG. 10 (a) and binarized, the output result is black. By the way, FIG. 10 (b) shows a reduced image,
The portions marked with * are the pixels to be processed. Where the
10 When black is output in response to the input in FIG. 10A, text at intervals of one line is not reproduced. Thus, by referring to the reduced pixels and correcting the output of the low-pass filter, such periodicity can be reproduced even with the reduced pixels.

That is, the pixel data input via the data line 200 forms a 3 × 3 pixel block as described above using the line buffers 201a to 201c and the latches 202a to 202i. These 3x3
Are input to the negative / positive inverters 205a and 205b.

The run length counters 203a to 203c count white and black run lengths in each line buffer. The attribute determiner 204 performs processing when these run lengths exceed a certain threshold value, for example, when there is a line buffer of two or more lines whose black run length exceeds 2/3 of the size of the image in the main scanning direction. It is determined that the image is a negative image. Conversely, if there is a line buffer with two or more lines exceeding one third of the size in the main scanning direction in a line buffer of two or more lines, it is determined that the image is a positive image. The conditions for determining the negative / positive may be the same or different for either of the negative / positive.

With this determination, the negative / positive inverters 205a and 205b operate to invert the pixel values input to the low-pass filter 206 and the corrector 207. As described above, the negative / positive inverters 205a and 205b invert the input and output when the attribute is determined to be negative.

The low-pass filter 206 performs a calculation based on the weight of the low-pass filter shown in FIG. 11 on the pixel data unified into the positive image, and performs binarization using a threshold.

211a and b are line buffers of the reduced image, and the line buffer 211a stores the pixel data of the reduced image line being processed.
The line buffer 211b stores the line data of the small gap image one line before. A latch 213 latches data in order to input an upper left pixel to a pixel (*) undergoing the reduction process in FIG. 10B.

Here, the corrector 207 refers to the 3.times.3 pixel block from the latches 202a to 202i and the three reduced pixels from the line buffers 211a and 211b and the latch 213, and is not reproduced by the low-pass filter alone. Black thin line,
A correction value for reproducing the periodicity shown in FIG. 10A is output. That is, for an input pattern as shown in FIGS. 13 (a) and 13 (b), irrespective of the state of the reduced pixel, 1 indicating black and a flag indicating that correction has occurred are set to 1, and FIG. For the input pattern as in a), if the state of the reduced pixel is 10th
In the case of FIG. 2B, 0 representing white and a correction flag of 1 are set. If the reduced pixel is in any other state, 1 representing black is output, and a correction flag is set to 0 to indicate that no correction is performed.
And

The determiner 208 receives the data of the reduced pixel from the low-pass filter 206 and the corrector 207, and receives the correction flag from the corrector 207. When the correction flag is 1, the decision unit 208
Sends the output of the corrector 207 to the next negative / positive inverter 209. Conversely, if it is 0, the output of the low-pass filter 206 is sent out. The negative / positive inverting unit 209 inverts the data from the judging unit 208 according to the judgment result of the attribute judging unit 204. The latch 210 latches the result and outputs it to another external device, for example, the encoder 54 in the third embodiment.

In this way, the periodicity is reproduced by referring to the reduced pixels, and there is no need to input attribute information from others.
Further, since it is not necessary to perform prescanning or the like, the hardware configuration is simplified, the time can be reduced, and better reproduction is possible even when a negative image and a positive image are mixed in one image.

As described above, the present invention has been described using some preferred embodiments. However, the present invention is not limited to these embodiments. For example, the image reduction method is not limited to this. A reduction method that does not save, in other words, a non-symmetry negative / positive image when determining reduced pixels depending on the surrounding reference pixels or the status of reduced pixels that have already been obtained may be used. For example, a recursive filter including reduced pixels A and B as shown in FIG. 10 may be used and the reference pixels may be set to 11 pixels. Further, the configuration of the negative-positive inverter is not limited to this.

Furthermore, the configuration is not limited to this in the reduction in the hierarchical coding. For example, one frame memory can be selectively used by an address operation. Further, the negative / positive inversion is not limited to the pixel unit, and a plurality of pixels such as a block unit may be simultaneously performed. The output of the image reduction is not limited to the pixel unit but may be a block unit smaller in size than the input.

[Effects of the Invention] As described above, in a reduction method that is not symmetrical for a negative / positive image, a means for performing inversion that can be easily configured before the reduction apparatus is provided, and the attribute of the input image is input or input from outside. By automatically detecting and controlling the reversing means based on the result, it is possible to improve the image quality of the reduced image because the attribute of the image data to be reduced is kept constant. It is possible to completely equalize the image quality. In addition, even in a hierarchical coding method or the like in which this is repeatedly applied several times, there is an effect of improving the image quality of a negative-positive image regardless of the respective attributes.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image reducing apparatus embodying the present invention, FIG. 2 is a block diagram of an image reducing apparatus embodying the present invention, and FIG. 3 is a block diagram when the present invention is applied to a hierarchical coding method. FIG. 4, FIG. 4 is a detailed configuration diagram of a negative-positive inverter, FIG. 5 is a detailed configuration diagram of an image reducer, FIG. 6 is a configuration diagram of a negative-positive inverter, FIG. 7 and FIG. 8 is a diagram showing weights of other recursive filters, FIGS. 10 and 13 are diagrams showing pattern examples of 3 × 3 pixel blocks, and FIG. 11 is a diagram of a low-pass filter. FIG. 12 is a diagram showing the center pixel position of the low-pass filter, 1, 101 is a frame memory, 2, 4, 102, 104 are negative / positive inverters, 3, 103 is an image reducer, 30a to c, 80a to c are line buffers, 31a-i, 81a-i are latches, 32 is a low-pass filter, 33,83 are line segment detectors, 54 is The encoder 106 is a negative / positive determiner.

Continuation of the front page (72) Inventor Tadashi Yoshida 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/387-1 / 393 G06T 5/00

Claims (2)

(57) [Claims] An apparatus for reducing the image size of binarized image data, a means for externally inputting image attribute information or a means for detecting image attribute information from an input image, and a reduction method for performing reduction processing on image data Means, and means for inverting image data before the reducing means, and inverting image data of a specific attribute according to the attribute information, so that the attribute of the image data input to the reducing means is constant. An image reducer comprising: 2. A reduction device for reducing the image size of binarized image data and further reducing the size of the obtained reduced image, wherein means for externally inputting attribute information indicating negative / positive of the image or Means for detecting from an input image, reduction means for performing reduction processing on image data, and first inversion for inverting image data of a specific attribute in accordance with the attribute information before the first reduction by the reduction means Means,
An image reducing apparatus, comprising: a second inverting unit that inverts image data having a specific attribute according to the attribute information after the final stage of reduction.