JP2774597B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a method for manufacturing a field effect transistor,
In particular, the present invention is applied to the manufacture of a field-effect transistor including a step of thinning a semiconductor substrate such as a via hole and a plated heat sink (hereinafter abbreviated as PHS).

(Conventional technology) Via hole formation technology and PHS formation technology are important technologies for increasing the output and the frequency of microwave field effect transistors such as GaAs FETs.

In the case where a plurality of FETs each having a source electrode, a drain electrode, and a gate electrode are formed on the surface of the GaAs substrate, the via hole is provided with a through hole extending from the back surface of the substrate to the source electrode on the substrate surface. The source electrodes are electrically connected to each other by the metal provided on the back surface of the substrate via the through holes. Since the source electrodes are connected to each other by via holes, it is not necessary to perform bonding to each source electrode, so that the parasitic inductance caused by the bonding wire can be reduced and high-frequency operation can be performed. In the PHS, the GaAs substrate is made thinner, and a metal (usually, gold) provided on the back surface of the GaAs substrate is thickly plated. With such a structure, heat generated from the FET is efficiently transmitted to the back metal,
As a result of improving heat dissipation, higher output is achieved.

To form the via hole and the PHS structure, it is necessary to make the semiconductor substrate thinner. Hereinafter, a process for manufacturing a GaAs FET having a via hole and a PHS structure will be described with reference to FIG.

As shown in FIG. 2A, an n-type GaAs layer 2 is formed on the upper surface of a semi-insulating GaAs substrate 1, and the source electrodes 3a and 3a are formed on the n-type GaAs layer 2 by a known method. 3b, a plurality of FEs composed of drain electrodes 4a, 4b and gate electrodes 5a, 5b
T (FIG. 2 illustrates two cases). next,
The GaAs substrate 1 is fixed to a jig (not shown) with wax or the like, and the back surface is polished to the position shown by the broken line in the figure, and the GaAs substrate 1 is thinned to a thickness of about 30 μm. Next, patterning is performed on the back surface of the thinned GaAs substrate 1a to form a source electrode.
An opening is provided immediately below each of 3a and 3b, and a through hole (via hole) 6 reaching the source electrodes 3a and 3b from the opening is formed by etching (FIG. 2 (b)). Subsequently, gold is vapor-deposited on the entire back surface of the substrate and further plated to form a gold plating layer 7 having a thickness of 30 to 40 μm as shown in FIG. 2 (c), and the via hole and PHS forming steps are completed. .

In the above-described series of steps, a substrate back surface polishing step greatly affects the element yield. That is, in order to obtain a high yield, it is necessary to uniformly reduce the thickness of the entire substrate to about 30 μm, but this involves some difficulties as described below. First, when the substrate is fixed to a jig with wax, unevenness of about ± 5 μm is unavoidable due to thickness unevenness generated at the time of applying the wax, and this unevenness is directly affected by the thickness of the GaAs substrate after polishing. Leads to variation in the length. Second, in the polishing step, the GaAs substrate is likely to be cracked or chipped. In particular, the cracks and chips become more serious as the substrate is made thinner in order to reduce the thermal resistance. . Third, the polishing step is for mechanically shaving the GaAs substrate by friction with a material of high hardness such as alumina powder.
It is inevitable to give processing strain to the substrate, and after the above-described process described with reference to FIG.
When the substrate is removed, the substrate often breaks due to thermal stress.

As described in detail above, in the production of a field-effect transistor including a step of thinning a semiconductor substrate such as a via hole or a PHS, the yield is significantly lower than in the production of an element that does not require much thinning. This was a major obstacle to reducing prices.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problems, and the present invention provides a thin layer having extremely good thickness uniformity and no processing strain. A GaAs substrate is obtained, and as a result, a field-effect transistor having a via hole and a PHS structure with a high yield can be provided.

[Configuration of the invention]

(Means for Solving the Problems) A method for manufacturing a field-effect transistor according to the present invention includes a step of epitaxially growing a first compound semiconductor layer and a second compound semiconductor layer on a semiconductor substrate;
Forming a field-effect transistor on the second compound semiconductor layer; and removing the first compound semiconductor layer by etching to separate the second compound semiconductor layer from the semiconductor substrate. . In this case, the semiconductor substrate and the second compound semiconductor layer are both gallium arsenide, and the first compound semiconductor layer is aluminum arsenide.

(Operation) By using the method for manufacturing a field-effect transistor of the present invention, the thickness of a compound semiconductor substrate having extremely good uniformity in thickness and no processing strain can be reduced, and therefore, a high level is achieved. It is possible to provide a field-effect transistor having a via hole and a PHS structure with a high yield.

EXAMPLES Hereinafter, as one example of the present invention, GaAs is used as a semiconductor substrate and a second compound semiconductor layer, AlAs is used as a first compound semiconductor layer, and GaAs having a via hole and a PHS structure is used.
The process of manufacturing the sFET will be described with reference to the drawings.

As shown in FIG. 1 (a), on a semi-insulating GaAs substrate 11, a thickness of 20 μm is formed by metal organic chemical vapor deposition (MOCVD).
An undoped AlAs layer 12, a 30 μm thick undoped (high resistance) GaAs layer 13, and a 0.1 μm thick n-type GaAs layer 2 are successively grown. In FIG. 1A, a GaAs substrate
Reference numeral 11 denotes a semiconductor substrate in the present invention, AlAs layer 12 corresponds to a first compound semiconductor layer, and undoped GaAs 13 and n-type GaAs layer 2 correspond to a second compound semiconductor layer.

On the epitaxial wafer formed as shown in FIG. 1A, a plurality of FETs comprising source electrodes 3a, 3b, drain electrodes 4a, 4b and gate electrodes 5a, 5b are formed by a known method (FIG. 1). (B)). Next, the wafer is fixed to a jig (not shown) with wax or the like, and immersed in a mixed solution of hydrofluoric acid / hydrogen peroxide / water. Since the above mixed solution etches only the AlAs layer 12 and hardly damages the GaAs layer 2, the GaAs substrate
11 are separated, and the structure shown in FIG. 1 (c) is obtained. Subsequent steps are the same as in the conventional example shown in FIGS. 2B and 2C, and a through-hole (via hole) 6 reaching the source electrodes 3a and 3b from the back surface of the undoped GaAs layer is formed (FIG. (FIG. 1 (d)), a gold deposition and a gold plating layer (7) are provided to complete the field effect transistor having the structure shown in FIG. 1 (e).

In the above step, since substrate polishing is not required, cracking, chipping, and processing distortion of the substrate due to polishing do not occur at all. Since the thickness of the GaAs layer after thinning is determined by the thickness of the grown layer during epitaxial growth, the controllability of the thickness is increased, and the thickness uniformity is ± 3% (when the GaAs layer thickness is 30 μm, Is within ± 1 μm).

In the embodiment described above, a GaAs substrate is used as a semiconductor substrate, an AlAs layer is used as a first compound semiconductor layer, and a second
Although the case where a GaAs layer is used as the compound semiconductor layer has been exemplified, the present invention is not limited to these semiconductor materials. For example, the case where Si is used as the semiconductor substrate or the case where an InGaAs layer is used as the second compound semiconductor layer The present invention can be applied to the case of using the method.

In addition, it goes without saying that the crystal growth method and the crystal layer thickness described in the embodiments are not restricted.

〔The invention's effect〕

As described above, according to the present invention, in the production of a field-effect transistor including a step of thinning a semiconductor substrate, the semiconductor substrate can be thinned without using mechanical means. The effect is remarkably improved, and remarkable effects such as the quality of the field effect transistor can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a field-effect transistor according to the present invention in the order of steps, and FIG. 2 is a sectional view showing a method of manufacturing a conventional field-effect transistor in the order of steps. 1,11 ... semi-insulating GaAs substrate (semiconductor substrate), 3a, 3b ... source electrode, 4a, 4b ... drain electrode, 5a, 5b ... gate electrode, 6 ... through hole, 12 ... undoped AlAs Layer (first compound semiconductor layer) 13... Undoped GaAs layer (second compound semiconductor layer)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812 H01L 21/78-21/786 H01L 21/306-21/3063 H01L 21/308 H01L 21/465-21/467

Claims (2)

(57) [Claims] A step of epitaxially growing a first compound semiconductor layer and a second compound semiconductor layer on a semiconductor substrate; and a step of forming a field-effect transistor on the second compound semiconductor layer. A method for manufacturing a field-effect transistor, comprising a step of removing the first compound semiconductor layer by etching to separate the second compound semiconductor layer from the semiconductor substrate. 2. The method according to claim 1, wherein the semiconductor substrate and the second compound semiconductor layer are both gallium arsenide, and the first compound semiconductor layer is aluminum arsenide.