JP2783045B2 - Ultraviolet erasing nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultraviolet-erasable nonvolatile semiconductor memory device, and more particularly to an ultraviolet-erasable nonvolatile semiconductor memory device requiring erasure confirmation after an operation test of each memory cell at the time of manufacturing.

[0002]

2. Description of the Related Art A conventional ultraviolet erasing type nonvolatile semiconductor memory device is, as shown in FIG. 3, as an example, a plurality of ultraviolet erasing type nonvolatile semiconductor memory devices arranged in a matrix in a row direction and a column direction and formed of floating gate transistors. Memory cells (MC1, M
Cx, MCy, MCz) and a plurality of word lines (WL, WL) connected to the gates of these memory cells for each row.
x), a memory cell array 1 including a common connection line commonly connected to the source of each memory cell, and a plurality of digit lines (DL1, DLy) connected to the drain of each memory cell for each column, and the memory cell array 1 A test memory cell TMC provided outside and formed with the same characteristics simultaneously with the memory cells (MC1, MCx, MCy, MCz)
And pads PD1, PD2 respectively connected to the drain, gate, and source of the test memory TMC.
PD3.

A characteristic test of the memory cell itself can be performed by bringing a contact needle of a test apparatus into contact with each of the pads PD1, PD2, and PD3.

In general, after forming the memory cell array 1 and the like, ultraviolet erasure is performed, and after erasure of all memory cells is confirmed, an operation test is performed. Since writing is also performed in this operation test, ultraviolet erasing is performed again and the package is assembled.

In the ultraviolet erasing nonvolatile semiconductor memory device, the ultraviolet irradiation window is covered with a cover film, and the erasing time varies depending on the material of the cover film. Particularly in the case of mold assembly, SiON with excellent moisture resistance due to the problem of moisture resistance
It is common to use a system cover.

[0006] When the thickness of the SiON-based cover is increased, the amount of transmitted ultraviolet light is reduced, and the erasing time is prolonged. Therefore, the first confirmation of the ultraviolet erasure is that each pad of the semiconductor chip has P
The erase needle is checked for all addresses by contacting the contact needle of the ROM tester. The second erasure check is performed in such a manner that if the contact needle is brought into contact many times, the surface of the pad will be damaged and a bonding failure will occur.
Confirmation of erasure is often completed.

[0007]

The above-mentioned conventional ultraviolet erasing type nonvolatile semiconductor memory device includes a memory cell array 1
After the formation and the like, and after the operation test, ultraviolet erasing is performed. The first erasing confirmation is also performed on the address of the memory cell array 1, but the second erasing confirmation is because the bonding pad is damaged. However, since the test is performed using the test memory cells TMC, there is a disadvantage that the erasure of the memory cells in the memory cell array 1 itself cannot be confirmed.

An object of the present invention is to provide an ultraviolet-erasable nonvolatile semiconductor memory device in which erasure confirmation and characteristic test of a memory cell of a memory cell array itself cannot be performed without damaging bonding pads.

[0009]

According to the present invention, there is provided an ultraviolet-erasable nonvolatile semiconductor memory device comprising a plurality of ultraviolet-erasable memory cells formed of floating gate transistors arranged in a matrix in a row direction and a column direction. A plurality of word lines connected to the gate of each memory cell for each row, a common connection line commonly connected to the source of each memory cell, and a plurality of digit lines connected to the drain of each memory cell for each column are provided. Memory cell array, and a first test word line for connection to a predetermined word line of the plurality of word lines.
, A second test pad connected to a predetermined digit line of the plurality of digit lines, and a third test pad connected to the common connection line.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The memory cell array 1 of this embodiment has a structure shown in FIG.
Is the same as the conventional example shown in FIG. In this embodiment, the conventional test memory cell TMC and the pads PD1 to PD3 shown in FIG. 3 are not formed. Instead, the test pad PDw connected to the word lines WL1 and WLx
1, PDwx, a test pad PDd connected to the digit line DLk, and all memory cells (MC1, MCj, M
A test pad PDg connected to a ground line commonly connected to the source of Cx) is provided.

These pads PDw1, PDwx, PD
Using d and PDg, a threshold voltage can be measured at the time of writing, reading, and writing of the memory cell (MC1, MCx) in the memory cell array 1, and a threshold voltage after erasing can be measured.

In FIG. 1, word lines WL1 and WLx connected to pads PDw1 and PDwx are, for example, word lines 150
Although this is set to every book, this is because the pads PDw1 and PDw
Since it is determined based on the size of x, PDd, PDg and the size of the memory cell, it may be provided as needed as far as possible.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In the first embodiment, one digit line DLk is used.
While the characteristics of a plurality of memory cells (MC1, MCx) connected to a single word line WL1 can be measured, the characteristics of a plurality of memory cells (MC1, MCx) connected to one word line WL1 can be measured.
The characteristics of y) can be measured.

In this embodiment, pads are provided every 100 digit lines.

In the first and second embodiments, a pad is also provided for the source of the memory cell. However, the source of a normal memory cell is generally grounded. In this case, the pad PDg is omitted. be able to. In this case, another ground pad, a pad for a reference potential point, or the like may be used.

[0019]

As described above, the present invention provides a word line connected to a gate of a memory cell in a memory cell array,
By providing first, second, and third pads for testing that are respectively connected to a digit line connected to a drain and a common ground connection line connected to a source, a memory cell array according to a conventional example is provided. There is an effect that erasure confirmation and measurement of various characteristics of the memory cell of the memory cell array itself, not the external test memory cell, can be performed without damaging the bonding pad.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional ultraviolet erasing nonvolatile semiconductor memory device.

[Explanation of symbols]

1 Memory cell array DL1, DLk, DLy Digit lines MC1, MCj, MCk, MCx, MCy, MCz
Memory cells PD1 to PD3, PDd, PDd1, PDdy, PD
g, PDw, PDw1, PDwx pad TMC test memory cell WL, WLj, WLx word line

Claims (2)

(57) [Claims] A plurality of ultraviolet erasing memory cells arranged in a matrix in a row direction and a column direction and formed of floating gate transistors; a plurality of word lines connected to the gates of these memory cells for each row; A memory cell array including a common connection line commonly connected to a source of each of the memory cells, and a plurality of digit lines connected to a drain of each of the memory cells for each column; and a predetermined word among the plurality of word lines. A first test pad connected to a line, a second test pad connected to a predetermined digit line of the plurality of digit lines, and a third test pad connected to the common connection line An ultraviolet-erasable nonvolatile semiconductor memory device comprising a pad. 2. The ultraviolet-erasable nonvolatile semiconductor memory according to claim 1, wherein at least one of the first and second pads is connected to at least two word lines and digit lines, respectively. apparatus.