JP2783138B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a semiconductor device.
Especially suitable for battery (battery) backup operation.
The present invention relates to a conductor device. [0002] 2. Description of the Related Art A so-called information storage device represented by a memory.
In semiconductor devices that have the ability to
Electronic devices such as power supplies for driving semiconductor devices.
In the so-called power failure state at the time of failure, the above information storage device
It is generally desired that the information stored in
You. For this purpose, the electrical characteristics in normal operating conditions and the shutdown
In order to satisfy both the information retention characteristics during power transmission,
A battery (battery) is provided in the electronic device,
The battery supplies operating power with this battery, a so-called battery.
Terry backup method is adopted. In the above-mentioned battery backup system, the power
In order to extend the operation duration of the pond, semiconductor devices
Information holding state (hereinafter simply referred to as information holding state)
Power consumption) should be as small as possible.
It is necessary. The low power consumption characteristic in this information holding state is as described above.
In addition to the battery backup method during a power outage,
There is a case where only the information needs to be stored stably for a long time.
Or small electronic devices that are easy to carry
Carry the device with only information stored at low power consumption
And perform various processes at any location based on the information stored above.
It is also very convenient in the case of nau. [0004] SUMMARY OF THE INVENTION Static RAM
When the power supply voltage supplied to the memory cell is selected
Or, switch when not selected to reduce the power consumption of the memory cell.
Japanese Patent Application Laid-Open No.
JP-A-5884 / 8884
In Japanese Unexamined Patent Application Publication No. 4 (1999) -2004, non-selected memory cells, that is, signal transmission
It merely discloses the reduction of power consumption of circuits without
Power consumption of the circuit that transmits signals even when the power supply voltage drops.
No consideration was given to empowerment. You
That is, in the semiconductor device according to the related art, the power supply voltage drops.
Most measures have been taken for low power consumption characteristics.
Is not sufficient, and if any, it is insufficient.
It was not suitable for use like the re-backup method. Accordingly, an object of the present invention is to reduce the power supply voltage.
Providing semiconductor devices with even lower power consumption
Is to do. [0006] An object of the present invention is to reduce a power supply voltage.
Power supply wiring (3) to be supplied,
Power supply voltage converting means for reducing and outputting the above power supply voltage
(200), the power supply voltage from the power supply wiring and the reference
Comparing means (110) for comparing a voltage with the power supply wiring;
Pulse generating circuit to which the power supply voltage is supplied
(PG1) and the power supply voltage is supplied from the power supply wiring.
A second pulse generation circuit (PG2),
The power supply voltage from the source wiring has dropped below the reference voltage
In response to the output of the comparing means, the second pulse
The power supplied from the power supply wiring to the power supply
Switching from voltage to output voltage of the power supply voltage conversion means
(See FIG. 4).
To FIG. 11). It is another object of the present invention to provide a first pulse generating circuit.
(PG1) and a second pulse generation circuit (PG2).
Semiconductor device, the second pulse generation circuit
Signal delay time is large and power consumption is small.
Pulse generation circuit (PG2 ') and the second pulse generation circuit
Either the raw circuit or the third pulse generation circuit
A switch provided to be connected to the first pulse generation circuit.
Switch means (SW502, SW502 ').
(FIG. 11)
reference). [0008] The power supply voltage from the power supply wiring is equal to the reference voltage.
Depending on the output of the comparison circuit when the pressure drops below
The power supply voltage supplied to the second pulse generation circuit is changed to the first voltage.
Make it lower than the power supply voltage supplied to the pulse generation circuit.
As a result, the operation can be stopped without stopping when the power supply voltage drops.
It is possible to further reduce the power consumption of the second pulse generation circuit.
it can. The second pulse generating circuit or the second pulse generating circuit
Either of the third pulse generation circuits is set to the first pulse
The switch means provided to be connected to the generating circuit
When the power supply voltage drops, the third pulse generation circuit is raised.
It is connected to the first pulse generation circuit. The third pulse above
The generator consumes less power than the second pulse generator.
Therefore, when the power supply voltage drops, further reduction of semiconductor device consumption
Electricity can be achieved. [0010] DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to embodiments.
You. FIG. 1A illustrates the basic concept of the present invention.
This is an example. In FIG. 1, reference numeral 1 denotes an LSI chip.
Is an LSI chip having an information storage function.
Random access memory such as Mick and Static
(RAM) or read-only memory (ROM),
Furthermore, a logic LSI such as a microcomputer
Any type of LSI chip may be used. Also,
Its components are bipolar transistors and MOS transistors.
Transistors, combinations of these elements, or Si
For example, a GaAs transistor using an external material
Any of these may be used. Reference numeral 2 denotes a circuit unit. 3 is power supply
Line, V_INTIndicates the voltage, here 3 is the external power supply
Pressure V_EXTIs applied. That is, V_INT= V_EXTTona
You. Here, for simplicity, only one power supply is shown.
However, even when a plurality of types of power are externally applied,
Absent. This is the same in the following embodiments. 4 is
This is the signal input / output wiring. In the figure, 5 is a battery, V_BTIs that
Voltage, and this battery is used as a power source in the information retention state.
The whole top works. 6 is current from 3 to 5 during normal operation
Is a diode for preventing backflow. here
Then, for simplicity of explanation, reference numeral 6 indicates that the forward voltage is 0 V,
Directional impedance 0Ω, reverse impedance ∞Ω (no
Suppose an ideal diode having the characteristic of (maximum). What
These are external power sources in the battery backup system.
An example of one connection method between a power source and a battery.
The device is equipped with a power failure detection means so that 3 and 5 can be automatically
It is also conceivable to make a connection. In the following example
The connection of these batteries is not shown for simplicity. Numeral 100 denotes an information holding state from a normal operating state.
Operating state detecting means for detecting that the
Is output to 101 as a signal “1” or “0”.
Power. In this case, the above detection means is provided inside the LSI chip.
Although a stage is provided, an input terminal as shown by a broken line 7 in FIG.
And the detection by the power failure detection means of the electronic device described above.
The result may be input as a signal. This is described below
The same applies to each embodiment. [0013] Here, 100 is the voltage or voltage of 3
Detects changes in flow and changes from normal operating state to information holding state
Recognize that the transition to. Hereinafter, in each embodiment, the voltage change
The explanation focuses on the method of detecting
Of course, other physical quantities caused by the characteristics of the LSI chip
Changes, eg temperature, humidity, volume, light intensity, speed, acceleration
Such a change may be detected. In addition, the LSI chip
Not a physical quantity change of the body, but an electronic device or LSI chip
Operating state affects the operation of other devices, resulting in
Means for detecting a change in physical quantity may be used. Stated above
Speed, acceleration, etc. are generally examples. Either
But is each physical quantity converted to an electrical quantity once?
Therefore, any of the methods for detecting a voltage change described below
Also applicable to cases. Hereinafter, a case where 100 detects a voltage change of 3 will be described.
An example will be described. 100 is generally V_BT<V_EXT3 if
That the voltage of_BT> V_EXTIn the case of 3
The fact that the voltage has increased_BT≒ V_EXTIn case of
Noise (such as glitch noise)
) And outputs a signal to 101.
To reduce power consumption in the information retention state
Is V_EXT> V_BTIs better
The operation of the present embodiment will be described with reference to FIG.
Will be explained. Note that in this embodiment, V_EXT> V_BTof
It is not necessary to meet the condition, which will be
It is the same as above. As shown in FIG. 1B, for example,
Power outage (power failure due to power failure, intentionally turning off the power
If a power failure occurs, the voltage of 3_INT
Is V_EXTTo V_BTIt gradually drops toward the voltage of. This
Is a predetermined fixed reference voltage, for example, V
_BC1If it becomes lower (time t₁), State detecting means 100
Is φ_BC(Change from “0” to “1”), φ
_{BC ~}(Change from “1” to “0”).
That is, the operating state is communicated by the state detecting means 100.
Recognition of transition from normal state to information holding state
It is. In response to the signal 101, the circuit unit 2
Switch the state to the minimum power consumption required to retain information.
Reduce to force. Voltage V of 3_INTIs the time t₁To t_TwoShy
, But V_BTWhen the voltage of the diode 6
(Assuming that the forward voltage is 0 V as described in (2)).
That is, electric power is supplied from 5 and a voltage V of 3_INTDecrease in V
_BTAnd then continue the information retention operation at this voltage
You. On the other hand, when the power failure recovers or the external power is turned on,
Voltage V of 3_BTRises to a constant reference voltage V_BC2Higher
When it becomes_BC, Φ_{BC ~}Signal of the original normal operating state.
As described above. As a result, the circuit unit 2
Return to normal operation. According to the above-described embodiment, the change of the operation state is performed.
Information is detected and power consumption is retained in the information retention operation state.
To the minimum required for operation of the
When operating in the backup mode, or when using a portable battery
Battery operation time when carrying
You. In this embodiment, a change in the operating state is detected internally.
I mentioned the method of issuing
Even when the status change is indicated by signals from the
Similar effects can be obtained. Also, the detection of state changes was described earlier.
Physical quantity other than voltage change, such as current change
May be detected. In voltage change detection, the detection reference voltage
Voltage VBC when the voltage falls and rises._BC1, V_BC2Made
However, this varies depending on the design, and may vary.
And V_BC= V_BC1= V_BC2It may be. Also, these
Value is V_EXTAnd V_BTEach normally possible voltage of
It is desirable to set in consideration of fluctuation. For example, VEXT
Is 5V, the fluctuation is ± 0.5V, and the center value of VBT is
3V, and if the fluctuation is ± 0.3V, V_BC1, V_BC2
Such as V_BCOf 3.3V <V_BCSet as <4.5V
If it does, V which can usually occur_EXT, V_BTFluctuations
To eliminate the problem of detection as a change in operating state
it can. FIG. 2 shows another specific embodiment.
You. 1 have the same contents. same
In the figure, the circuit part 2 is divided into 2a and 2b,
Mainly different, 2a is in the information holding state such as at the time of power failure
The circuit section 2b not related to information retention is related to information retention.
Circuit part. Specifically, for example, with a logic circuit
LS for microcomputers with mixed memory circuits
Logic circuit 2a and memory circuit 2b
Respond. In this case, even if it is not a direct memory circuit,
Circuits that generate signals necessary for the operation of memory circuits
2b. In this embodiment, the operation state is the same as in FIG.
A change in state is detected by 100, and the result is converted to 101.
Output. With this signal, it is not particularly related to information retention
The operation of the circuit section 2a is stopped to reduce power consumption. information
Power is supplied to 2b related to the holding, and the information is held. According to this embodiment, there is no relation to information retention.
Stops the operation of the circuit section, enabling a significant reduction in power consumption
Noh. Note that 2a and 2b in this embodiment are
As described above, in the information retention state such as during a power outage,
Circuit parts not related to information retention and related circuits
The logic circuit mentioned as a specific example
(2a) It is not limited to the memory circuit (2b). example
If the same memory circuit is used,
The memory portion that does not need to store the information of
It may be included in the part. Specific example of such an LSI chip
For example, in the memory system of a large computer
BS (Buffer Storage) operating at high speed, low speed
However, as with large-capacity MS (Main Storage)
Have (or even more) types of memory, mainly
The information is stored in the MS at normal operation.
To speed up the process, a small amount of information may be
LSI chip that reads and operates from a high-speed BS
And the like. In this case, BS 2a, MS
It should be 2. Generally, high-speed memory such as BS
Is a bipolar static memory, large like a MS
The quantity memory is composed of MOS type dynamic memory
However, its components, circuit method, etc.
Various other selections are possible. For example, both 2a and 2b
Bipolar and MOS transistors, respectively
Combination of both types of transistors, and also other than Si
Components such as transistors made of GaAs type material
Static or dynamic memory
And other types of memory can be arbitrarily selected. FIG. 3 shows another specific embodiment of the present invention.
An example is shown, and the same numbers as those in FIG. 2 indicate the same contents.
ing. In the figure, the circuit section 2b is divided into 2b1 and 2b2.
They differ in that they are divided. In FIG. 2, reference numeral 2b1 denotes an information holding operation at the time of a power failure or the like.
In the operation state, it is related to the information
Consumption due to high performance during operation (for example, high-speed operation)
This is a circuit part designed to have large power.
The product of time and power consumption is almost constant.) Sand
In other words, the performance is excessive for only the information retention operation,
Therefore, the power consumption is high in the circuit section. 2b2
Is a circuit portion except for 2b1 in 2b. In this embodiment, in the information holding operation state,
Is obtained by the signal of the output 101 described in the embodiment of FIG.
Power consumption by stopping the operation of the portion 2a unnecessary for the information holding operation
At the same time as reducing the
The necessity of using the high performance 2b1 circuit for the information retention operation
To reduce the power consumption of this circuit section. According to this embodiment, the embodiment shown in FIG.
In addition, power consumption can be reduced. In this example,
In addition, low power consumption by stopping the operation of 2a and 2
The two of low power consumption by trade-off with the performance of b1
The same effects can be achieved even if implemented independently.
Needless to say, this is obtained. FIG. 4 shows an LSI chip in addition to the embodiment of FIG.
Power supply voltage conversion means 200 is provided in the
2b3 operates at its output 201. 2b1 ', 2b2
'Removes 2b3 from 2b1, 2b2 in FIG.
Circuit part that was The voltage conversion means 200 is in the information holding state.
From the operating voltage of the circuit section 2a other than 2b3
Alternatively, a boosted voltage is output. Here is the normal operating state
The output voltage of 200 at is generally equal to the voltage of 3.
However, even under normal operating condition, the voltage itself is
6-57143, Japanese Patent Application No. 56-168698, etc.
The value obtained by converting the voltage of 3 for other purposes as described
It may be. Now, in the information holding state, the voltage
The purpose of stepping down is to reduce the operating power supply voltage of 2b3 to information, for example.
Power supply voltage VBT (battery voltage)
This is to reduce power consumption by lowering the power consumption. That is,
Specific example of the method for reducing the power consumption of 2b1 in FIG.
It is also a practice. Also, the eye that boosts the voltage
Specifically, for example, in the power supply voltage VBT in the information holding state,
The operating voltage is too low, and the circuit performance deteriorates,
If it becomes unstable, operate it with the boosted voltage
This is to stabilize the crop. As described above, in the information holding state,
Step down or boost some circuits in the LSI chip compared to others
Low power consumption and operation by operating at the specified voltage
Can be stabilized. In the present embodiment,
To convert the power supply voltage for simplicity
As mentioned, in some cases the amplitude voltage of the pulse signal
It may be a conversion target. As described above, FIG. 1 to FIG.
Concept was explained. Contents described in these examples
Are implemented individually or in any combination
It is possible to obtain the effect described in each embodiment as it is.
Of course, it can be done. Further, in each embodiment,
The operation state detecting means 100 includes a normal operation state and an information holding state.
The example of detecting the two states described above has been described.
Detection of operating state, for example,_BTPrepare the value of
And V_INTOf small changes in the
φ_BCCauses more fine-grained circuit control.
It is also possible to do. Alternatively, launch in this way
Born φ_BCAnd each embodiment described with reference to FIGS.
It is also possible to operate in combination. That is, the figure
Φ at 4_BCAs φ_BC1~ Φ_BC4And φ_BC1
2a, φ_BC22b1 ', φ_BC3By
2b2 ', φ_BC4Controls the operation of 2b3
Other things are possible. In each embodiment, the description will be simplified.
100, 200, 2a, 2b, etc.
Sections are clearly separated, but in general each circuit is an LSI
Mutual input in the spatial arrangement in the chip, circuit connection, etc.
It goes without saying that they are mixed and mixed. The following is a more specific description of each embodiment described above.
Examples will be described. FIG. 5 shows a specific example of the operation state detecting means 100.
In this example, the change in voltage is detected and the
An example of detecting a change will be described. In the figure, reference numeral 110 denotes the power of the inputs 111 and 112.
Discriminates the level of the positional relationship. If 111 is higher, output 1
13 is low potential (information “0”), and 111 is lower
This is a discrimination circuit that outputs high potential (information "1").
Loose Schmitt trigger circuit or comparator circuit
Road. There are various concrete construction methods of these circuits.
However, in general, a differential amplifier or IEE
ー E Transaction on Circuits A
And Systems Vol. CAS-25, No. 7, July 1
978, pages 482-489 (IEEE Transact
ion on Circuits and Systems, Vol. CAS-25, N
o.7, July 1978, pp482-489).
Operational Amplifier
May be used. 120 is input to 121, for example, V
_INTTo the appropriate value V for the input of 110_INTConvert to ´
Circuit, and in some cases V_INT'= V_INTAs well
No. 130 is the reference voltage V described in FIG._BC(V_BC1,
V_BC2). 115 is the 113 signal
φ_BCIs inverted to 114_BCInverter that outputs ￣
Circuit. According to this embodiment, V_INT´> V_BCin the case of
Is a low potential (information “0”) at 113 and a high potential at 114
(Information "1")_INT´ <V_BCIn the case of, 113,
114 can output the opposite signal to the above.
To detect changes in operating conditions.
You. Here, V_INTAnd V_INTThe relationship of 'is 120 in advance
Therefore, after all, V_INTAnd V_BCConstant
The above detection can be performed in the relation of According to the present embodiment, the characteristics of 120 and 130
The detection level can be changed minutely by changing the
Versatility and design flexibility
Can be In this embodiment, the reference voltage VBC is set to 1
The method of generating at 30 and inputting it to the discrimination circuit 110 has been described.
Has a certain threshold value which is itself 110, and this value
And the input voltage, and according to the result,
Or a so-called threshold circuit that outputs "0"
There may be. In such a case, V
_INTTo any V_INTBy converting to ´ and inputting,
The desired characteristics can be obtained. One of the specific embodiments
Will be described later with reference to FIG. FIG. 6 shows that, as described in FIG.
_INTThe detection reference voltage at the time of drop and rise of V_BC1, V_BC2When
It is a specific example in the case of different. As shown in the drawing, in this embodiment, the reference voltage
Binary V_BC1, V_BC2With the ability to generate
Add these to S₁₃₁, S₁₃₂Switch of V_BC
And output to 112. S₁₃₁, S₁₃₂Switching
Well, here is φ_BC(In some cases, φ_BCUsing ￣
), And φ_BCWhen “0” is
That is, in the normal operation state, S₁₃₁On, S₁₃₂Off and
Then V_BC= V_BC1And φ_BCIs “1”, that is,
S in the information holding state₁₃₁Off, S₁₃₂Is turned on and V
_BC= V_BC2Then, as shown in FIG._INTAt the time of decline
V_BC1Becomes the reference voltage, and when rising, V_BC2Becomes the reference voltage
Become. According to this embodiment, V_INTWhen falling and rising
Can be independently set to arbitrary values. FIG. 7 shows V in FIG._INTTo V_INTChange to ´
This is one specific embodiment of the circuit 120 for converting and outputting. As shown in FIG._INT´
Is V_INTTo R₁₂₁, R₁₂₂By dividing the resistance by
Have been obtained. Also, V_BCIs almost the threshold of Q131
Voltage V_T131be equivalent to. In the present embodiment, V
_INT´ = R₁₂₂/ R_{one two Three}+ R₁₂₁・ V_INTAnd V_BC≒ V_T131of
Compare the relative voltages, and if the former is higher,_BC=
“0”, if the former is low, φ_BC= Output "1"
Power, but this is V_INTAnd V_T131Reorganization of relationships
Then it looks like this: That is, [0044] (Equation 1) In the case of φ_BC= “0”, [0046] (Equation 2) In the case of φ_BC= “1”. These are shown in FIG._BCIs the value of
(1 + R₁₂₁/ R₁₂₂) V_T131Is equivalent to
Therefore, R₁₂₁And R₁₂₂By choosing
The reference voltage can be easily set to any value. FIG. 8 is a circuit diagram of the operation state detection circuit 100.
This is another specific embodiment, and the basic configuration circuit is described in
No. 57-220083, the circuit presented in FIG.
DCV is used. In FIG.₁₄₁~ Q_14n, Q₁₅₁Each
Threshold is V_T141~ V_T14n, V_T151MOS transistor
It is. Where Q₁₄₁~ Q_14nIs V in FIG._INTof
The conversion circuit 120 is composed of 150 V_INT'= V
_INT− (V_T141+ ... + V_T14n) Is output. Q₁₅₁, R
₁₅₁Constitutes the discrimination circuit 110 of FIG.
Solid himself has a certain reference threshold,
Threshold for discriminating input voltage level
It is a value circuit. The threshold V of this circuit_TCIs V_T151
Threshold voltage V_T151And R₁₅₁And Q₁₅₁To the on-resistance ratio of
It is more defined and can be set arbitrarily.₁₅₁The value of₁₅₁of
If it is set sufficiently higher than the on-resistance, V_TC= V_T151
It can be. Here, for simplicity,
Will be described. The operation of this embodiment will be described with reference to FIG.
explain. V_INTGradually decreases to a voltage of 150
Is V_INT'= V_INT− (V_T141+ ... + V_T14n) ≦ V_T151You
That is, V_INT≤V_T151+ (V_T141+ ... + V_T14n) = Φ_BC
(Time t₀) Q₁₅₁Turns off and the output φ_BCIs
"0" changes to "1". By this, already mentioned
V as in the previous embodiment._INTOperation is detected
The transition to the information holding state can be detected. Also in this embodiment, the MOS transistor used is
By adjusting the threshold voltage of the transistor or the number of stages
And the equivalent V in FIG._BCCan be set to any value
You. Further, according to the present embodiment, V_INT≤V_T151+ (V_T141+
… + V_T14n) Under Q₁₅₁Is turned off and the eyes of the present invention
To reduce power consumption in the information retention state
Effective. In FIG.₁₅₀Is V_INTFrom high to low
Charge at nodes such as 150 when changing state
This is a discharge resistor for preventing the discharge from occurring. This resistance
The value is V_INTMust be selected according to the rate of change of
If the rate of change of the
It is also possible to substitute a parasitic resistor that is parasitic on
Yes, in which case R₁₅₁Is unnecessary. Where R₁₅₀, R
₁₅₁Can be replaced with the on-resistance of the MOS transistor.
It is possible. In the present embodiment described above, the same as the other embodiments
Various modifications are possible. For example, Q₁₄₁~ Q_14nHaichi
Any device that can provide a constant voltage shift can be used.
Polar transistor, FET transistor, Tio
And zener diodes can be substituted. Also, Q
₁₅₁Is used if the active device has a certain threshold
Possible, bipolar transistor, FET transistor
Etc. can be substituted. In addition, each of the implementations described above
Any combination with the examples is possible. for example
If V_INT'Is generated by using the resistance dividing circuit described in FIG.
Alternatively, or conversely, 120 in FIG.
Q of₁₄₁~ Q_14nMay be replaced by a circuit such as FIG. 9 shows the resistance R of FIG.₁₅₀, R₁₅₁Each
Re Q₁₅₂, Q₁₅₃This is an embodiment replaced with. V_G2, V_G3Is Q₁₅₂, Q₁₅₃Gate via
Voltage, connected to the drain in some cases
Then V_G2= V_INT', V_G3= V_INTIt may be. Where V
_G3= V_INT, Then φ_BCHigh voltage side of
(“1”) voltage is V_INTTo Q₁₅₃Threshold voltage V
_T153Note that it is only lower. So this
Voltage to V_INTIf you want to be equal to_G3≧ V_INT+ V
_T153It is necessary to set as follows. In this embodiment
Also has the same operation and effect as FIG._G2=
V_INT´ as Q₁₅₂Threshold voltage V_T152To V_T152≒ V
_T151So, V_INT´ <V_T151Information retention behavior
In the working state, Q₁₅₂Will also be turned off,
The power consumption can be further reduced than in the case of FIG. As described above, in the embodiment shown in FIGS.
4 to FIG. 4 show a specific embodiment of the operation state detecting means 100.
I also mentioned. Next, information is held by the output signal of 100.
A specific embodiment for reducing the power consumption in the operating state is described in MO.
S dynamic memory and address multiple
A description will be given by taking a memory of the matrix type as an example. It should be noted that the present invention
The scope of application is not limited to this, and in the following examples,
Applicable to various types of LSI chips as described above
It is. FIG. 10 is a block diagram showing an address multiplexer according to the present invention.
Example applied to a matrix-type MOS dynamic memory
It is. Now, with a MOS dynamic memory,
As is known, the storage capacity in the memory cell
Information charge disappears over time,
It is necessary to perform the rewrite operation periodically. This is it
This is a refresh operation, and the information holding operation state of the present invention.
This operation is also required in the state. Address multiplex
For example, a memory cell is a memory cell in which a row and a column are secondary.
In the originally arranged memory, the row designation address and column
Multiplex the specified address on the same signal line by dividing the time zone
Input from outside to reduce the number of input / output pins of the entire LSI
It is a method of aiming. These details are described in Japanese Patent Application No. 56-28.
No. 109, etc. In FIG. 10, 1 is a memory LSI chip,
3 is a power supply wiring,_INTIndicates the voltage.
V from outside to 3_EXTOr for battery backup
V_BTIs applied. 4 is a ground line, generally V_SS(0
V) is applied from the outside. 100 detects the voltage change of 3
Circuit for detecting the operating state of the memory LSI chip
Therefore, the various embodiments described above can be applied. 300
Is the substrate voltage generation circuit built in the memory LSI chip
It is. This substrate voltage is the operating performance (operation) of the memory LSI.
Speed, etc.).
Depending on the situation, it may be given externally or
Alternatively, the ground potential may be used. In this case, 300 is unnecessary
You. Reference numeral 700 denotes a two-dimensional array of memory cells arranged in rows and columns.
Memory array section, and is provided by a row selection decoder 800.
Row selection 80i and column selection decoder 900 selected by
By the intersection of any column selection line 90i selected by
The designated memory cell is read and the write circuit 43
0, data input buffer circuit 440, data output buffer
An external D_in, D_outAnd signal
Give and receive 400 is an external write control signal
WE generates the internal clock signal necessary for the write operation.
This is the circuit that occurs. 410 is the column selection control signal CAS
Therefore, the internal clock mainly related to the column selection operation described above is used.
This is a circuit that generates a lock signal. 420 is CAS and line
By comparing the phase of the selection control signal RAS,
Signal φ for resh_fIs a circuit that generates Normal movement
At the time of the work, RAS is input before CAS.
These signals also change from “1” to “0”).
Refresh if input before RAS
Judge as operation_r0Occurs. 500 by RAS
Generates an internal clock signal mainly related to the row selection operation.
It is a circuit that produces. Generally address multiplex
In the memory of the formula, a row selection line (generally a word line) 801
-80n sequentially (arbitrary order), address buffer 46
0 and an output signal selected by the row selection decoder.
By doing so, a refresh operation is performed. did
Therefore, 500 circuits are mainly used during the refresh operation.
Only one need be operated. Reference numerals 600, 610, and 620 denote riffs, respectively.
Resh control circuit, fixed time according to 600 instructions
signal φ every tf_fA refresh timer that generates
It is an address counter and auto refresh (Autom
atic Refresh, Self Refresh
h) Perform each refresh operation. Auto refresh is a refresh operation.
Start-up is performed according to an external instruction.
Is automatically generated by the internal address counter.
Operating mode. In contrast, self-refresh
Is the activation of the refresh operation and the refresh address
The generation is automatically performed in the memory LSI chip. this
These operations are based on the external refresh signal REF or
Is the output φ of 420 described above._r0Is controlled by That is, in the auto refresh, REF
(Generally changes from high voltage to low voltage) or φ_r0Is entered
Every time_rOccurs during the refresh operation
500 as well as an internal address counter
620 automatically refresh address A internally
i ′, and 46 instead of the external address signal Ai.
0, and 801 to 80n in order according to Ai '.
The next selection operation is performed and the refresh operation is performed. Self riff
Refresh is in addition to the internal generation of the refresh address described above.
In addition, a certain time t_fOccurs every time
Signal φ_fAutomatically refreshes internally
The work is started. Auto refresh and self-refresh
An instruction from the outside of the fresh is generally sent after the REF signal.
State (generally low voltage state)
Self-reflection when the duration exceeds a certain time.
A flash operation is performed. These details
Electronic technology, Vol. 23, No. 3, etc. Now, in the memory having the above configuration,
Therefore, in the present invention, as described in the embodiment of FIG.
A voltage change is detected by 100, and a change in the operation state is detected.
Know. This can be used, for example, in the event of an external power outage.
When it is detected that the information holding operation has started, 60
0, 610, 620, etc., and activates the previously described cell.
The memory cell operates in the same manner as the
To prevent the information in the inside from disappearing. At this time, the present invention
In the same way as described above,
Supply only the minimum necessary power to the
The power supply stops. Therefore, the refresh operation
400, 410, 430, 44 primarily unrelated
Circuits such as 0, 450, and 900 stop operating in principle
Let it. Further, the circuit required for the information holding operation
However, the power consumption is reduced as much as possible. That is, before
As mentioned, the performance of each circuit is the performance required for normal operation.
Is set according to the
Is over-performing, such as operating too fast.
ing. This performance is reduced to the minimum required for information retention operation
I do. For example, a circuit of 500 has an operation speed
Set the speed appropriate for the operation to reduce power consumption. In addition,
Stop the operation of the plate voltage generation circuit and set the substrate potential to the ground potential
(0V) or lower the starting capacity to reduce power consumption.
Reduce power consumption. Further described in Japanese Patent Application No. 58-99341.
The number of refresh operations is the same as in the normal operation.
Lower power consumption is achieved. For example, electronic
64K bits described in Technology, Vol. 23, No. 3.
In a dynamic memory or the like, the refresh time tref
2ms, refresh cycle Nref128 cycles
Although it is a general specification, this is 12 ms in 2 ms.
This means that eight refresh operations are required. did
Therefore, once every tf = tref / Nref ≒ 15 μs on average
, The signal φ from the refresh timer 610_tDepart
It is necessary to perform a refresh operation. t_fThe value of the
Is reduced as the internal temperature Tj of the LSI chip increases.
When Tj changes by 30 ° C., about one digit t_fIs small
We know experimentally what we need to do. above
Specifications are determined by considering the worst conditions under normal operating conditions
It is. That is, the ambient temperature T using the LSI chip
a is the highest (generally 70 ° C), the power consumption P of the LSI chip
d is determined under the maximum condition. Tj at this time is
If Ta = 70 ° C. and Pb = 300 mW, [0066] (Equation 3) Here, θ_jaIs the LSI chip package
Thermal resistance, θ_ja
１００100 ° C./W. As described above, under the worst conditions, Tj ≒ 100 ° C.
And based on this value, t_fIs defined. Now, in the information holding state in the present invention,
Is intended to reduce power consumption.
Can sufficiently satisfy Pd ≦ 1 mW.
For example, the value of Tj is Ta even if the external power supply fails.
Is apparent from equation (4) even at a high temperature of 70 ° C.
Thus, Tj is lower by about 30 ° C. than in the normal operating state.
And therefore t_fCan be increased by about one digit. That is,
The number of refresh operations per unit time can be reduced by about one digit.
You can. In the information holding operation state,
The entire electronic device that uses the LSI chip also stops operating
In general, there is a need to keep Ta below 70 ° C.
You can think that. Therefore, the value of tf should be longer.
May be. In the present invention, utilizing the above,
In the holding state, φ generated from the refresh timer
_fThe time interval tf is set to be longer than normal operation by one digit or more.
To reduce the number of refresh operations and reduce power consumption.
Aim. Further, in the present invention, in the information holding operation state,
In other words, a part of the operating voltage of the memory
The operation is stabilized by setting it higher than the circuit. In this embodiment, the change of the operation state is performed.
Describes how to detect
However, as mentioned earlier, it is also possible to give instructions from outside
For example, as described in the description of the refresh operation,
Φ due to the phase difference between RAS and CAS_r0How to cause
Alternatively, you can use the REF signal input method
You. In other words, the self-refresh instruction in the prior art
It is used as an instruction for operating state change in the present invention.
You. Here, φ is determined by the phase difference between RAS and CAS.
_r0And the method of inputting the REF signal are as follows.
Since the functions are almost the same, either method is generally used.
Just prepare. For example, state change detection is performed at 100
No, φ due to phase difference between RAS and CAS_r0Causes
Instruct conventional auto refresh operation and input REF
Is possible. At this time,
The information holding operation state of the present invention may be provided.
Almost corresponds to the self-refresh operation.
Is also good. According to the above-described embodiment, the information holding operation
Power consumption in the working state can be significantly reduced. Hereinafter, specific examples of each part of the present embodiment will be described in other embodiments.
This will be described in detail with an example. In the following embodiment, the memory
Assuming N-channel MOS transistor as constituent element
As described above, other P-channel MOS transistors,
Alternatively, both P and N channel types, and even bipolar type
Transistors and combinations of MOS and bipolar
It can be applied to the case where any of the constituent elements is used. FIG. 11 shows an embodiment of low power consumption.
Thus, an example is described in which the power consumption of the circuit 500 in FIG. 10 is reduced.
Clear. Generally, a circuit of 500 is as shown in FIG.
Generation of multiple dynamic pulses such as PG1 to PG3
It consists of cascaded connections of circuits. This pulse generation circuit P
An example of the circuit configuration and operation of G
Listed in the IEICE National Conference on Semiconductors and Materials No. 69
I have. V_INT1~ V_INT3Indicates the power supply voltage of each PG
Connected to a common power supply voltage VINT in the chip.
It is. Now, in the present invention, as described above,
The operation speed is too fast just for the information holding operation,
Set an appropriate speed (lower speed) for this operation state to reduce power consumption.
Strengthen. That is, in a general circuit,
Signal delay time t_PdAnd the power consumption Pd are almost constant.
That is to say that it is used. Therefore, in this embodiment,
The power supply of the circuit to be reduced in power consumption, for example, the power supply of PG2
Pressure V_INT2Lower than the power supply voltage of other circuits to reduce power consumption
Plan. As another means, in the information holding state,
For example, the circuit constant of PG2 is internally switched and t_PdThe size
To reduce Pd. Also, as another means,
As shown by the broken line in FIG.
Note that in the information holding operation state, SW502, SW
502 ', SW503 and SW503' switches.
The operating circuit is switched from PG2 to PG2 '
Reduce power consumption. According to the embodiment described above, 500 circuits
Low power consumption can be achieved. In addition, the applicable range of this embodiment
Is not limited to 500, but in other similar circuits
Applicable. In general, most of the circuits shown in FIG.
It is a dynamic circuit. Therefore, input 5
01 or 602 receives a signal and the circuit operates
It consumes power only when it does. I
However, only the PG1 circuit receives an external signal RAS #,
Can respond immediately if entered at any time
As described above, the apparatus is always in a standby state in which power is consumed. sand
That is, PG1 is a static type circuit.
2 is the low consumption of the substrate voltage generation circuit 300 described in FIG.
This is one of the specific embodiments for power generation. Generally, a substrate voltage generating circuit is
ESSC Sea Digest of Te
Clinical Papers, pp. 138-139 (197
6ISSCC DIGEST of TECHNICAL
  PAPERS, pp. 138-139).
As shown in the figure, the power supply voltage is
And generates a voltage of the opposite polarity. In the figure, reference numeral 311 denotes a ring oscillator circuit.
Oscillation circuit consisting of a charge pump signal
φ_BBOccurs. C_BBIs the charge pump capacity Q_BB1Is straight
For flow regeneration, Q_BB2Is a rectifying MOS transistor.
Also, I_BBIs a substrate generated in the entire circuit in the LSI chip
This is a schematic representation of the current, and is generally
Circuit current driving capability I_outIs I_out≧ I_BBMust be
Absent. Details of these operations are described in the above literature.
You. Now, in the information holding state in the present invention,
Most of the LSI chips are in a stopped state.
The substrate current of the LSI chip becomes extremely small and the substrate voltage
Current drive capability I of generating circuit_outLSI
There is no hindrance to the operation of the entire chip. This I_outAnd substrate voltage
Power consumption Pd of generating circuit_BBAre approximately proportional, so
This I_outAnd Pd_BBCan be reduced
You. I_outIs generally represented by the following equation. [0082] (Equation 4) Here, Vφ_BBIs φ_BBVoltage amplitude of f_BBIs
φ_BBFrequency. Therefore, in this embodiment, the information holding state
Then Vφ_BBAnd reduce the value of Pd_BBSmaller. This
Vφ of_BBThere are various ways to reduce the value of
The operating voltage V of the circuit_INTBCan be reduced (generally
V in normal operation_INTB= V_INT). This V_INTBLower
For example, Japanese Patent Application No. 56-168698
And Japanese Patent Application No. 57-220083.
The operating voltage V of the entire LSI chip is determined by the circuit._INTLower
Voltage, and V_INTAnd its low
It suffices to switch the voltage for use. Also Pd_BBThe small
F_BBMay be reduced. for that purpose,
For example, if you use the above method of lowering the operating voltage,
Good. Or f in 311_BBTime constant of the circuit that determines
May be controlled. 311 has a plurality of inverters
Consists of a ring oscillator cascaded in a ring
If it is, the load resistance of the inverter is switched so that f
_BB(Determined by the delay time of the inverter), Pd_BBControl
You may. In addition, Pd_BBAs a way to reduce
Is a multiple C_BBAnd prepare this depending on the operating state.
It is also possible to switch and use it. As described above, the power consumption of the substrate voltage generation circuit is reduced.
As mentioned above, in some cases,
The operation stops in the information holding state, and V_BB= 0V
It is also possible to completely reduce power consumption to zero. for that reason
As shown in FIG. 12, the ground line 311 (the power line
Q)_BB3And this is φ_BC￣ to turn off the power
You only need to stop paying. At this time, the output 316 is Q_BB4
It is fixed to the ground potential (0 V). Thus V_BB= 0V
Then, the diffusion layer capacitance Cj in the LSI chip increases.
(Cj is inversely proportional to the square root of the voltage between the diffusion layer and the substrate.
Problems), such as slow operation speed.
As mentioned, it operates at a particularly high speed in the information holding state
There is no problem because there is no need. Also, V_BB= 0V
Power supply via the input / output pins of the LSI chip
When noise with a polarity opposite to the voltage is input,
Remembered information may disappear, but such
In this case, as a silicon substrate for making an LSI chip,
Using a silicon substrate with a sufficiently low specific resistance,
Even if the above noise is input,
What is necessary is just to be able to absorb. Note that the specific resistance is small.
If too much, the threshold of MOS transistor formed there
This may cause characteristic problems such as too high voltage.
In such a case, the resistivity suitable for making a MOS transistor
Forming an anti-silicon layer on the low resistivity silicon substrate
Was. For example, an epi silicon substrate may be used. As described above, according to this embodiment, the information storage
The power consumption of the substrate voltage generation circuit in the holding state can be reduced.
You. The basic concept of the present invention described above with reference to FIGS.
Examples of dynamic memory
However, the scope of the present invention is limited to this.
And can be applied to various types of LSI
It is. [0088] According to the invention described above, the power supply voltage drops.
Occasionally, we provide semiconductor devices with even lower power consumption.
Can be

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an embodiment illustrating a basic concept of the present invention. FIG. 2 is an example illustrating a basic concept of the present invention. FIG. 3 is an embodiment illustrating the basic concept of the present invention. FIG. 4 is an example illustrating the basic concept of the present invention. FIG. 5 is a specific example of an operation state detection unit. FIG. 6 is a specific example of an operation state detection unit. FIG. 7 is a specific example of an operation state detection unit. FIG. 8 is a specific example of an operation state detection unit. FIG. 9 is a specific example of an operation state detection unit. FIG. 10 is a specific example for reducing power consumption of the entire chip. FIG. 11 is a specific example for reducing power consumption of the entire chip. FIG. 12 is a specific example for reducing power consumption of the entire chip. [Description of Signs] 1 ... LSI chip, 2 ... Circuit part, 3 ... Power supply wiring, 4 ... Signal input line, 5 ... Battery, 6 ... Diode.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-15991 (JP, A) JP-A-56-159892 (JP, A) JP-A-54-137246 (JP, A) 172761 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G11C 11/407

Claims (1)

(57) [Claims] A power supply line for supplying a power supply voltage, power supply voltage conversion means for stepping down and outputting the power supply voltage input from the power supply wiring, a comparison means for comparing the power supply voltage from the power supply wiring with a reference voltage, A first pulse generation circuit to which the power supply voltage is supplied from the power supply wiring; and a second pulse generation circuit to which the power supply voltage is supplied from the power supply wiring, wherein the power supply voltage from the power supply wiring is Switching the voltage supplied to the second pulse generation circuit from the power supply voltage from the power supply wiring to the output voltage of the power supply voltage conversion means according to the output of the comparison means when the voltage falls below the reference voltage. A semiconductor device characterized by the above-mentioned. 2. 2. The semiconductor device according to claim 1, wherein the second pulse generation circuit is an oscillation circuit of a substrate voltage generation circuit. 3. A control signal is supplied from outside, and the control signal
A pulse generation circuit that forms a delayed pulse signal
Wherein the pulse generation circuit comprises a first pulse generation circuit, a second pulse generation circuit, and a third pulse generation circuit having a longer signal delay time and a smaller power consumption than the second pulse generation circuit. wherein a pulse generator circuit, to become one of the second pulse generating circuit or the third pulse generating circuit and a switching means as provided for connecting to the first pulse generating circuit Semiconductor device. 4. A power supply line for supplying a power supply voltage to the first pulse generation circuit and the second pulse generation circuit; and a comparing means for comparing the power supply voltage from the power supply line with a reference voltage. In response to the output of the comparing means when the power supply voltage from the wiring falls below the reference voltage, the switching means is controlled so that the third pulse generating circuit is connected to the first pulse generating circuit. The semiconductor device according to claim 3, wherein: