JP2784764B2 - Memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a static RAM (hereinafter referred to as SRAM).
And a dynamic RAM (hereinafter referred to as DRAM).

[Summary of the Invention]

The present invention relates to a memory device suitable for application to an SRAM or a DRAM, and a gate circuit for supplying or preventing a signal obtained at one or two predetermined terminals to a memory control unit according to a signal level obtained at a chip enable terminal. And the signal level obtained at the chip enable terminal undergoes a predetermined change. While the level is maintained, the number of pulse signals obtained at one or two predetermined terminals is counted. A multi-bit test for simultaneously testing a plurality of bits by including a count circuit for performing a predetermined output when a pulse signal is counted, and a multi-bit test circuit that is set or reset by a predetermined output of the count circuit Eliminates dedicated terminals for operating the circuit, simplifying the configuration. It is obtained by allowing the control of the strike circuit.

[Conventional technology]

Conventionally, some memory devices such as SRAMs have a multi-bit state circuit (MBT circuit). This multi-bit test circuit allows simultaneous testing of a plurality of signal processing units inside the memory device, and can greatly reduce the state time as compared with the case where testing is performed separately. In this case, when the test is performed by the multi-bit test circuit, a set signal is supplied from the outside to the multi-bit test circuit to make the test possible, and a reset signal is supplied from the outside to the multi-bit test circuit after the test is completed. It was necessary to return to the normal operation mode. Conventionally, in order to supply the set signal and the reset signal, specific terminals of the memory device are set as a set signal input terminal and a reset signal input terminal, and supplied from outside via these terminals.

[Problems to be solved by the invention]

However, if a dedicated terminal for supplying the set signal and the reset signal to the multi-bit test circuit is provided in the memory device, the number of terminals is increased accordingly, and the configuration of the memory device becomes complicated.

In order to solve this inconvenience, for example, a high voltage higher than the power supply voltage is applied to predetermined terminals other than the power supply terminal Vcc and the ground terminal GND, and when this high voltage is applied, the multi-bit test circuit is set or Although it is conceivable to make a configuration for resetting, it is not easy to actually generate a high voltage exceeding the power supply voltage, and the circuit configuration becomes complicated.

In view of the above, an object of the present invention is to provide a memory device capable of operating a multi-bit test circuit with a simple configuration that does not require a dedicated terminal.

[Means for solving the problem]

The memory device according to the first aspect of the present invention, as shown in FIG. 1, for example, changes a signal obtained at a first or second terminal (1b) or (1c) according to a signal level obtained at a chip enable terminal (1a). The signal level obtained at the first or second gate circuit (2) or (3) for supplying or blocking to the memory control unit (4) and the chip enable terminal (1a) undergoes a predetermined change, and the level is maintained. During this operation, the number of pulse signals obtained at the first or second terminal (1b) or (1c) is counted, and when a predetermined plurality of pulse signals are counted, a first count output is performed. Or, it comprises a second count circuit (6) or (7) and a multi-bit test circuit (8) set or reset by a predetermined count output of the first or second count circuit. According to a second aspect of the present invention, as shown in FIG. 4, a signal obtained at a predetermined terminal (1b) is supplied to a memory control unit (4) according to a signal level obtained at a chip enable terminal (1a). Alternatively, the gate circuit (2) for blocking and the signal obtained at the chip enable terminal (1a) make a predetermined change, and while the level is maintained, the number of pulse signals obtained at the predetermined terminal (1b) is changed. A counting circuit (31) that counts and outputs a set signal or a reset signal when the first or second number of pulse signals are counted, and a multi-bit set or reset by a predetermined count output of the counting circuit (31) And a test circuit (8).

[Action]

According to the memory device of the present invention, the multi-bit test circuit (8) is set or reset by supplying a predetermined number of pulse signals to the terminal (1b) or (1c) while supplying the window pulse signal to the terminal (1a). As long as the window pulse signal is not supplied to the terminal (1a), even if the pulse signal is supplied to the terminals (1b) and (1c), the multi-bit test circuit (8) does not test the predetermined signal processing unit. , Terminals (1a) and (1) except when the multi-bit test circuit (8) is operating.
b) and (1c) can be used for different signal input / output, and the multi-bit test circuit (8) can be operated with a simple configuration that does not require a dedicated terminal.

〔Example〕

Hereinafter, an embodiment of the memory device of the present invention will be described with reference to FIGS.
This will be described with reference to the drawings.

In FIG. 1, (1) shows the entire memory device, and in this example, the memory device (1) is integrated.
SRAM. The memory device (1) has a plurality of terminals (1a), (1b), and (1c) as signal input or output units.
.. And the terminal (1a) is a chip enable terminal ▲
In ▼, the terminal (1b) and the terminal (1c) are arbitrary terminals provided in the memory device (1) other than the power supply terminal Vcc and the ground terminal GND. The terminal (1a) is connected to the memory control circuit (4), and the terminals (1b) and (1c) are connected to the memory control circuit (4) via gate circuits (2) and (3) as input buffers. Connect to Further, a terminal (1a) is connected to the respective gate circuits (2) and (3), and the respective gate circuits (2) and (3) are controlled by a signal obtained at the terminal (1a). Although not shown, another terminal of the memory device (1) is connected to a memory control circuit (4) via a predetermined gate circuit.

The memory control circuit (4) is connected to a memory cell unit (5), which is a signal storage unit, via a bus line, and outputs a signal obtained at each terminal (1a), (1b). Based on this, the memory control circuit (4) controls input / output of storage data to / from the memory cell section (5). At this time, when, for example, a high-level signal “1” is supplied to the chip enable terminal (1a), a signal obtained to another terminal such as the terminal (1b) is not supplied to the memory control circuit (4) side. is there.

In this example, the signals obtained at the terminals (1a) and (1b) are supplied to a set signal discrimination circuit (6), and the signals obtained at the terminals (1a) and (1c) are reset signal discrimination circuits (7). To supply. Each of the determination circuits (6) and (7) outputs a predetermined pulse signal from the terminals (1b) and (1c) three times while a window pulse signal described later is supplied from the chip enable terminal (1a). When supplied, the circuit outputs a set signal and a reset signal to the multi-bit test circuit (8).

The multi-bit test circuit (8) is a circuit for simultaneously testing each signal processing unit such as the memory control circuit (4) and the memory cell unit (5) of the memory device (1). Connected via When the set signal is supplied from the set signal determination circuit (6),
When the test mode is set, the multi-bit test circuit (8) performs an operation test of each circuit, and when a reset signal is supplied from the reset signal discriminating circuit (7), the test mode is reset to the normal operation mode. It is made to return to.

Next, FIG. 2 shows the details of the set signal discriminating circuit (6), the reset signal discriminating circuit (7), and peripheral circuits. First, each of the gate circuits (2) and (3) includes a NOR gate (2
a) and (3a) are connected in series with inverter gates (2b) and (3b), and a chip enable terminal (1a)
Is connected to one input of each of the NOR gates (2a) and (3a), the terminal (1b) is connected to the other input of the NOR gate (2a), and the terminal (1c) is connected to the NOR gate (3a). ) To the other input side. Then, the output side of each inverter gate (2b) and (3b) is connected to the memory control circuit (4). With this configuration, for example, in the case of the gate circuit (2), when a high-level signal “1” is supplied from the chip enable terminal (1a) to one input side of the NOR gate (2a), The output signal of the NOR gate (2a) is always low level signal "0" regardless of the signal state of the terminal (1b)
Thus, a constant signal is supplied to the memory control circuit (4), and the signal obtained at the terminal (1b) is not supplied to the memory control circuit (4).

In this example, the signals obtained at the terminals (1a) and (1b) are supplied to a set signal discrimination circuit (6), and the signals obtained at the terminals (1a) and (1c) are reset signal discrimination circuits (7). To supply. The two discriminating circuits (6) and (7)
Has a similar configuration. For example, the set signal determination circuit (6)
The terminal (1b) is connected to the first input of a three-input NOR gate (12). A delay circuit (11) in which the terminal (1a) is connected in series with a plurality of inverter gates (11a) and (11b)
Of the delay circuit (11)
Connect to the second input of NOR gate (12). Furthermore, the terminal (1a) is connected to the third input side of the three-input NOR gate (12) via the inverter gate (13). Then, the output side of the three-input NOR gate (12) is connected to the count signal input terminal CLK of the counter (15) via the inverter gate (14). Further, the terminal (1a) is directly connected to the reset signal input terminal ▲ ▼ of the counter (15).

This counter (15) has a reset signal input terminal ▲
While the signal obtained at ▼ is a high level signal “1”,
In 2-bit counter for counting the pulse signal obtained at the count signal input terminal CLK, and the output terminal Q ₁ of inverted every supply of the pulse signal is inverted for each fall of the signal obtained at the output terminal Q ₁ output and a terminal Q _2. Then, both output terminals Q ₁ and Q ₂ are connected to one and the other input sides of the NAND gate (16), and the NAND gate (16)
Is connected to the set signal input terminal of the multi-bit test circuit (8).

Similarly, the reset signal discrimination circuit (7) also includes a delay circuit (2) composed of inverter gates (21a) and (21b).
1), 3-input NOR gate (22), inverter gates (23) and (24), counter (25) and NAND gate (2
The output side of the NAND gate (26) is connected to the reset signal input terminal of the multi-bit test circuit (8).

Next, an operation when the multi-bit test circuit (8) is operated by the memory device of the present embodiment will be described. First, when a set signal is supplied, an activation device (9) that outputs a predetermined signal described later. To the terminals (1a), (1b) and (1c) of the memory device (1). When the activation device (9) is a trigger signal for the set to the trigger signal input terminal (9a) is fed, the window pulse signal W to be high level signal "1" during the period t ₀ as shown in FIG. 3 A Is supplied to the chip enable terminal (1a), and a pulse signal P as shown in FIG. 3C is supplied to the terminal (1b) three times while the window pulse signal W is obtained.

When the window pulse signal W is supplied to the chip enable terminal (1a), the window pulse signal W is inputted to the reset signal input terminal ▲ ▼ of the counter (15) of the set signal discriminating circuit (6), While the signal W is obtained, the counter (15) counts the pulse signal obtained at the count signal input terminal CLK.

Then, the pulse signal P (FIG. 3C) obtained at the terminal (1b) and the window pulse signal W obtained at the terminal (1a) are delayed by the delay circuit (11) for a predetermined period d (third signal).
The NOR gate (12) obtains the NOR of the signal obtained by inverting the window pulse signal W supplied from the terminal (1a) by the inverter gate (13) with the NOR gate (12). The signal inverted as shown in FIG. 3D by (14) is supplied to the count signal input terminal CLK of the counter (15). Here, while the window pulse signal W is obtained at the reset signal input terminal ▲ ▼,
A pulse signal P '(FIG. 3D) slightly shifted in timing from the pulse signal P is supplied to the count signal input terminal CLK three times. Therefore, the signal output from the counter (15) becomes the third such signal is shown in Figure E, which is inverted every supply of a pulse signal P 'from the output terminal Q _1, the output terminal Q ₂
From the such signal is shown in Figure 3 F is inverted every edge cut off the signal output from the output terminal Q _1. And
The signal output from the set signal determination circuit (6) is
The signals obtained at both output terminals Q ₁ and Q ₂ are connected to a NAND gate (1
As shown in FIG. 3G, the signal becomes a signal obtained by performing a logical operation, from the supply of the third pulse signal P 'to the rise of the delay signal of the window pulse signal W (FIG. 3B) as shown in FIG. The output signal is supplied to the multi-bit test circuit (8) as a set signal.

When the set signal which temporarily becomes the low level signal "0" is supplied to the multi-bit test circuit (8), the multi-bit test circuit (8) enters a test mode, and each signal of the memory device (1) is set. The operation test of the processing unit is performed at the same time.

Then, when a reset signal is supplied to return the operation mode to the normal mode after the end of the test, a trigger signal for reset is supplied to a trigger signal input terminal (9a) of the activation device (9). When this signal is supplied, FIG.
Supplies window pulse signal W to be high level signal "1" during the period t ₀ as shown in a chip enable terminal (1a), as shown during the window pulse signal W is obtained in Fig. 3 C The same pulse signal P as in the setting is supplied to the terminal (1c) three times.

When the window pulse signal W is supplied to the chip enable terminal (1a), the window pulse signal W is inputted to the reset signal input terminal ▲ ▼ of the counter (25) of the reset signal discriminating circuit (7), While the signal is obtained, the counter (25) counts the pulse signal obtained at the count signal input terminal CLK.

Since the reset signal discriminating circuit (7) has the same circuit configuration as the set signal discriminating circuit (6), the pulse signal P is supplied three times as in the case of the set signal discriminating circuit (6). 3. A signal which temporarily becomes a low level signal "0" as shown in FIG. 3G is output, and this output signal is supplied to the multi-bit test circuit (8) as a reset signal.

When the reset signal which temporarily becomes the low level signal "0" is supplied to the multi-bit test circuit (8), the multi-bit test circuit (8) returns from the test mode to the normal operation mode, and the memory cell unit The data storage operation in (5) is performed.

As described above, the memory device (1) of the present example uses the terminals (1a), (1b) and (1c) for supplying a predetermined signal to the memory control circuit (4) during normal operation, and performs a multi-bit test. The setting and resetting of the circuit (8) can be instructed. Therefore, it is not necessary to provide a dedicated terminal for signal supply in the multi-bit test circuit (8), so that the number of terminals can be reduced accordingly, and there is an advantage that the configuration of the memory device is simplified. The window pulse signal W and the pulse signal P supplied from the activation device (9) to the memory device (1) do not need to have higher voltage values than other signals, and do not require a booster circuit as the activation device (9). A simple circuit configuration using a logic circuit can be obtained.

The relationship between the window pulse signal W and the pulse signal P will be described with reference to FIG. 3. The period t ₀ during which the window pulse signal W is obtained maintains the following relationship with the period t ₁ of the pulse signal P. You can do it.

t ₀ ≧ nt ₁ where n is the number of times the pulse signal P is obtained. The number n of the pulse signals P is three in the above-described example, but may be a plurality of times. Further, it is preferable to provide a setup time ts from the start of the window pulse signal W to the time when the first pulse signal P is obtained and a hold time t _H from the third pulse signal P to the end of the window pulse signal W. . The time d for delaying the window pulse signal W by the delay circuit (11) and (21) should be a d ≧ nt _1, shorter than the period t ₀ of the delay time d the window pulse signal W As a result, the counter of the pulse signal by the counters (15) and (25) stops at the rising point of the delay signal. By setting like this,
A signal from the starting device (9) is set and a signal discrimination circuit (6)
And the reset signal discriminating circuit (7) can reliably discriminate and supply the set signal and the reset signal to the multi-bit test circuit (8).

In the above embodiment, the same number of pulse signals P are supplied to the other terminals (1b) and (1c) to distinguish between set and reset. The number of signals P may be changed and supplied to the same terminal, and the difference between the numbers of pulse signals P may be used to distinguish between set and reset. That is, as shown in FIG. 4, when set as the activation device (32), the window pulse signal W
Terminal (1b) of the memory device (30) during supply of (FIG. 5A)
To the memory device (30) during supply of the window pulse signal W at the time of reset.
The pulse signal P (FIG. 5C) is supplied twice to the terminal (1b). As the memory device (30), when the pulse signal P obtained at the terminal (1b) is twice during the supply of the window pulse signal W obtained at the terminal (1a), a set signal is output, and the terminal (1a) A determination circuit (31) for outputting a reset signal when the number of pulse signals obtained at the terminal (1b) is three while the window pulse signal W obtained is supplied is provided. The multi-bit test circuit (8) is set by the supply of the set signal from the determination circuit (31) and reset by the supply of the reset signal. The other parts of the memory device (30) are configured in the same manner as the memory device (1) of FIG. By doing so, the multi-bit test circuit (8) can be set and reset using only the chip enable terminal (1a) and the other terminal (1b). It can be easily understood that the same operation and effect as in FIG. 1 can be obtained also in the case of FIG.

Further, the present invention is not limited to the above-described embodiment, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the memory device of the present invention, there is an advantage that a multi-bit test circuit for simultaneously testing a plurality of signal processing units can be operated with a simple configuration that does not require a dedicated terminal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a memory device of the present invention,
FIG. 2 is a block diagram showing details of the discrimination circuit of the example of FIG.
FIG. 4 is a timing chart for explaining the example of FIG. 1, FIG. 4 is a block diagram showing another embodiment of the memory device of the present invention, and FIG. 5 is a timing chart for explaining the example of FIG. (1) and (30) are memory devices, (1a), (1b) and (1c) are terminals, (4) is a memory control circuit, (5) is a memory cell section, (6) is a set signal discrimination circuit, (7) is a reset signal determination circuit, (8) is a multi-bit test circuit,
(9) and (32) are activation devices, and (31) is a determination circuit.

Claims (2)

(57) [Claims] In a memory device in which data writing or reading of a memory cell unit is controlled based on control of a memory control unit, when a signal obtained at a chip enable terminal is at a first level, the signal is applied to the first terminal. A first signal for supplying the obtained signal to the memory control unit and for preventing the supply of the signal obtained at the first terminal to the memory control unit when the signal obtained at the chip enable terminal is at the second level. A gate circuit, when a signal obtained at the chip enable terminal is at a first level, a signal obtained at a second terminal is supplied to a memory control unit, and a signal obtained at the chip enable terminal is at a second level; A second gate circuit for preventing a signal obtained at the second terminal from being supplied to the memory control unit; and a signal obtained at the chip enable terminal being at a first level. When a pulse signal changing to the second level is obtained, while the second level is maintained, the number of pulse signals obtained at the first terminal is counted, and a predetermined plurality of pulse signals are obtained. A first count circuit that performs a predetermined count output when counting is performed, and a second count circuit that obtains a pulse signal that changes a signal obtained at the chip enable terminal from a first level to a second level. A second count circuit that counts the number of pulse signals obtained at the second terminal while maintaining the level of the second terminal, and outputs a predetermined count when a predetermined plurality of pulse signals are counted; A multi-bit test circuit set by a predetermined count output of the first count circuit and reset by a predetermined count output of the second count circuit. Apparatus. 2. A memory device in which data writing or reading of a memory cell unit is controlled based on control of a memory control unit, wherein a signal obtained at a chip enable terminal is at a first level and is obtained at a predetermined terminal. A gate circuit that supplies a signal obtained to the chip enable terminal to the memory control unit and supplies a signal obtained at the predetermined terminal to the memory control unit when the signal obtained at the chip enable terminal is at a second level; When a pulse signal at which the signal obtained at the chip enable terminal changes from the first level to the second level is obtained, the pulse signal obtained at the predetermined terminal is maintained while the second level is maintained. A counter for counting the number of pulses, outputting a set signal when the first number of pulse signals are counted, and outputting a reset signal when the second number of pulse signals are counted. Memory device comprising: a preparative circuit, it is set by the set signal the count circuit outputs, and a multi-bit test circuit which is reset by a reset signal the count circuit outputs.