JP2786141B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device such as a read only memory (ROM).

[0002]

2. Description of the Related Art Conventionally, as a test method for judging non-defective / defective products of a semiconductor memory device, a method of judging whether or not desired data output can be obtained in response to an address signal input to the semiconductor memory device. Was common. However, with the recent progress in miniaturization of the semiconductor manufacturing process, it is necessary to detect a very small abnormality in the memory cell portion that does not appear as a defect in the output data in order to guarantee the long-term reliability of the semiconductor memory device. Came out. For example, JP-A-3-205
As in the case of the semiconductor memory device described in Japanese Patent Application Laid-Open No. 699 (Document 1), a small leak current occurs in the output side terminal portion of the memory cell transistor and the like, so that it is not detected as defective in the judgment based on normal output data. 2. Description of the Related Art A semiconductor memory device configured to detect a defect during a short test is used.

Referring to FIG. 5, which is a circuit diagram showing a part of a conventional semiconductor memory device described in Document 1 as a block, the conventional semiconductor memory device is arranged in a matrix of i + 1 column k + 1 row. NMOS transistor Q00
A memory cell array 8 having horizontally stacked memory cells made of Qik is provided. The gates of the memory cell transistors in each row are connected to corresponding word lines WL0 to WLi of an X decoder 5 which is a row address decoder.

The transistors Q00 to Qi for each memory cell
The bit lines BL1 to B1
Lk are connected to the respective bit lines BL1 to BLk.
Is connected to a sense amplifier 1 for amplifying read data from the transistors Q00 to Qik via NMOS transistors QN1 to QNk, and output data of the sense amplifier 1 is output via an output buffer 2.

In addition, each memory cell transistor Q00
To the source of Qik, respectively, a virtual ground line VGL
0, VGL2 to VGL (k + 1) are connected, and one virtual ground line VGL0 is connected to an NMOS transistor Q
V0 to QV (k-1), and are connected to one charging circuit 3 and the other virtual ground lines VGL2 to VGL (k +
1) NMOS transistors QV2 to QV (k +
It is connected to another charging circuit 4 via 1). These charging circuits 3 and 4 are connected to corresponding virtual ground lines V
The potentials of GL0 to VGL (k + 1) are changed to bit lines BL1 to BL
This is a circuit for setting the same high level as Lk.

The gates of the transistors QV0, QN1 to QV (k + 1) inserted in the middle of the bit lines BL1 to BLk and the virtual ground lines VGL0 to VGL (k + 1) correspond to the Y decoder 6 as a column address decoder. Column lines CSEL0 to CSELj are connected. Further, corresponding virtual ground lines VGL0 to VGL are provided between the output terminals of the charging circuits 3 and 4 and the ground.
NMOS transistors QM1 and QM2 for switching and setting the potential of (k + 1) to the ground potential (0 V)
Is connected.

The transistors Q00 to Qi for each memory cell
a plurality of NMOS transistors sources are connected respectively to the source and drain of k Q C 0~ Q C (k
+1), and these NMOSs are provided.
The gate and the drain of the transistor Q C 0~Q C (k + 1 ) is connected to an input terminal TT of commonly connected test signal TE. The input terminal TT is connected to the X decoder 5
And the Y decoder 6. The input terminal TT is a terminal for inputting a test signal TE when testing the semiconductor memory device. In response to the supply of the test signal TE, the operations of the X decoder 5 and the Y decoder 6 are stopped, and each NMOS transistor of circuit 7 Q C 0~Q C (k + 1) is turned on.

Next, the operation of the conventional semiconductor memory device at the time of testing will be described with reference to FIG. 5. When a high-level potential is applied to test signal input terminal TT as test signal TE during this test, The X decoder 5 and the Y decoder 6 stop operating, and the bit line BL1
To BLk and virtual ground lines VGL0 to VGL (k +
The transistors QV0, QN1 to QV (k +
1) is turned off, and each NMOS of the test circuit 7 is turned off.
Transistor Q C 0~Q C (k + 1 ) is turned on. As a result, transistors Q00-Q of memory cell array 8
ik on the drain side and virtual ground lines VGL0-VG
The potential of L (k + 1) is at a high level.

At this time, if there is a defect in the junction between the bit lines BL1 to BLk or the gate oxide film of the transistors Q00 to Qik and a leak current flows from the defective portion to the ground, even if the leak current is very small. NMOS transistor Q C 0~Q C of the test circuit 7 from the test signal input terminal TT (k + 1) via the transistor Q00~
The current I flows into the Qik side. Therefore, by confirming the presence or absence of the current, a good or defective semiconductor memory device is determined.

As described above, in the conventional semiconductor memory device,
Since the source and drain potentials of the transistor are set to a high level and the gate potential is set to a low level in order to detect a minute leak current of the memory cell transistor,
Only the leak current flowing from the source and drain to the gate or from the source and drain to the well of the transistor can be detected, and the leak current from the gate to the well due to a defect such as a gate oxide film cannot be detected.

Recently, in this type of semiconductor memory device, the cell size of a vertically stacked memory cell comprising a plurality of memory cell transistors connected in series can be reduced by sharing the source / drain between adjacent memory cells. It has been widely adopted because it has a smaller layout area than the horizontal memory cells and is advantageous for high integration.

However, the conventional semiconductor memory device cannot be applied to a vertically stacked memory cell because the potential of the gate of the memory cell transistor is set at a low level in order to detect a leakage current of the transistor.

The reason is that a vertically stacked memory cell generally uses both enhancement and depletion type transistors connected in series as a memory cell transistor.
In the case where the n-th memory cell transistor is an enhancement transistor, this transistor is turned off because the gate potential is at a low level, and the drain potential of the (n + 1) -th memory cell transistor from the bit line is undefined. The above-described leak current from the drain to the gate and from the drain to the well of the memory cell transistor cannot be detected.

[0014]

In the conventional semiconductor memory device described above, the source and drain potentials of the transistor are set to high level and the gate potential is set to low level in order to detect a small leak current of the memory cell transistor. , Only the leak current flowing from the source and drain to the gate or from the source and drain to the well of the transistor can be detected, and the leak current from the gate to the well due to a defect such as a gate oxide film cannot be detected. There was a disadvantage.

Further, since the gate potential of the transistor for detecting the leak current of the transistor for the memory cell is set to a low level, a vertically integrated memory cell which is more highly integrated than the horizontally stacked memory cell in terms of layout area can be obtained. If this method is to be applied, the enhancement transistor constituting the vertically stacked memory cell is turned off, and the drain potential of the subsequent transistor becomes unstable.

An object of the present invention is to solve the above-mentioned drawbacks and to minimize a leakage current between electrodes of memory cells or between wells which does not appear as a defect in output data irrespective of horizontal or vertical memory cells. An object of the present invention is to provide a semiconductor memory device that can detect the above-described abnormality of a semiconductor memory device having an abnormality and determine that the semiconductor memory device is defective.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array comprising a plurality of first conductivity type MOS transistors arranged in a matrix and forming memory cells; A row address decoder for selectively setting the transistors in an arbitrary row of the memory cell array to a conductive state and a bit line corresponding to the transistors in an arbitrary column of the memory cell array to be in an output enabled state; The column address decoder to be set and the selection operation of the row address decoder and the column decoder are stopped in response to the supply of the first test signal, and the potential of each electrode of all the transistors of the memory cell array is predetermined. A test circuit for setting a test level and performing a predetermined test. A first test switch circuit for connecting each of drains and sources of all the transistors of the memory cell array to a test voltage source in response to the supply of the first test signal; A second test switch circuit for simultaneously setting the potentials of the gates of all the transistors to the first level in response to the supply of the signal; and setting the output potentials to the first and second levels in response to the level of the second test signal. And the test voltage source set to one of the second levels.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of first memory cells arranged in a matrix and forming memory cells.
A memory cell array having a memory cell block composed of a series connection of MOS transistors of the conductivity type; a row address decoder for selectively setting the transistors of an arbitrary row of the memory cell array to a non-conductive state; A column address decoder for selectively setting a bit line corresponding to the transistor for an arbitrary column of the memory cell array to an output enabled state, and the row address decoder and the column decoder in response to supply of a first test signal And a test circuit that stops a selection operation and sets a potential of each electrode of all the transistors of the memory cell array to a predetermined level and executes a predetermined test. All of the memory cell arrays in response to the supply of the first test signal. A first test switch circuit for connecting each of a drain and a source of each transistor of the memory cell block to a test voltage source, and a gate for all the transistors in response to the supply of the first test signal; A second test switch circuit for setting the output potential to one of the first and second levels in response to a level of a second test signal; It is provided with.

[0019]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, in which components common to those of FIG. Referring to
The semiconductor memory device according to the present embodiment shown in this figure is composed of horizontally stacked memory cells as in the prior art, and has a common sense amplifier 1, an output buffer 2, charging circuits 3 and 4, an X decoder 5, and a Y decoder. Decoder 6 and transistors Q00-Qi
k, a memory cell array 8 having word lines WL0-W
Li, the bit lines BL1 to BLk, and the virtual ground line V
GL0, VGL2 to VGL (k + 1) and the column line CS
EL0 to CSELj, transistors QN1 to QNk,
QV0 to QV (k-1), QV2 to QV (k + 1), Q
In addition to M1 and QM2, a test circuit 7A having a test mode switching function is provided instead of the test circuit 7.

In the test circuit 7A, similarly to the transistors Q1 to Q (k + 1) of the conventional test circuit 7, the drains are respectively connected to the sources and drains of the transistors Q00 to Qik for the memory cells, and the gates are commonly connected. NMOS transistors QC0 connected to TT
A switch circuit 71 composed of QC (k + 1), an NMOS transistor QT1 having a commonly connected gate connected to a test mode terminal TD and a drain connected to a commonly connected source of transistors QC0 to QC (k + 1), respectively.
Inverter 72 including PMOS transistor QT0
An inverter 73 that inverts the test signal TE and outputs an inverted test signal TEB, a plurality of drains each having the gates connected to the gates of the transistors Q00 to Qik of the memory cell array 8, the gate connected to the output of the inverter 73, and the source connected to the power supply, respectively. And a switch circuit 74 having PMOS transistors QW0 to QWi.

When the test signal TE is input to the test signal input terminal TT, the operation of the sense amplifier 1, the X decoder 5, the Y decoder 6, and the charging circuits 3, 4 is performed in response to the supply of the test signal TE. Is stopped and the transistors QC0 to QC (k + 1) of the test circuit 7
Turns on.

Next, the operation at the time of testing of the present embodiment will be described with reference to FIG. 1. First, a high-level potential is supplied to a test signal input terminal TT as a test signal TE. In response to the supply of the test signal TE, the sense amplifier 1, the X decoder 5, the Y decoder 6, and the charging circuits 3, 4 are in an operation stop state, and are in the middle of the bit lines BL1 to BLk and the virtual ground lines VGL0 to VGL (k + 1). Transistors QV0, QN1 to QV (k + 1) are turned off, and transistors QC0 to QC of test circuit 7A are turned off.
(K + 1) turns on. Next, when the test mode signal TM is supplied to the test mode signal input terminal TD, the inverter 72 outputs a level inversion signal TMB of the test mode signal TM, and the NMOS transistors QC0 to QC
The potentials of the sources and drains of the transistors Q00 to Qik are designated via (k + 1). The inverter 73 outputs a low-level inverted signal TEB in response to the supply of the signal TE. In response to the supply of the inverted signal TEB, the transistors QW0 to QWi of the switch circuit 74 conduct, and the transistors Q00 to Qik The gate potential is set to a high level.

Transistors Qxy and Qx for arbitrary adjacent two bits representing transistors Q00 to Qik
FIG. 2A showing the potential of each electrode during the test of (y + 1).
When the supplied test mode signal TM is at a high level, the transistors Qxy and Qx
(Y + 1), that is, the potentials of the gates of the transistors Q00 to Qik become high level, and the transistors Q00 to Qi respond to the supply of the inverted test mode signal TMB.
The source and drain potentials of k become low level.
At this time, defects are present in the junctions of the word lines WL0 to WLi and the gate oxide films of the transistors Q00 to Qik, and the gate is grounded (source, drain, well).
When the leakage currents I1, I2, and I3 flow, even if the leakage current is very small, the power supply current flows from the power supply terminal to the transistors Q00 to Qik via the switch circuit 74. Since the sense amplifiers 1 and the charging circuits 3 and 4 are in an operation stop state as described above, usually only a very small power supply current should flow. However, if there is the above defect, the value of the power supply current is easy. To two or three orders of magnitude. Therefore, the presence or absence of a leak current can be confirmed by confirming the value of the power supply current, and a good semiconductor memory device
Defective products can be determined.

When the test mode signal TM is at a low level, as shown in FIG.
The gate potentials of 0 to Qik are at a high level, and the source and drain potentials are also at a high level. At this time, when the leak current I4 or I5 flows from the source or drain to the ground (well), the presence or absence of the leak current can be similarly confirmed based on the value of the power supply current, and the semiconductor memory device can be determined to be good or defective. It can be carried out.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention in which components common to those in FIG. Referring to FIG. 7, this embodiment is different from the above-described first embodiment in that a plurality of memory cells arranged in a matrix of i + 1 columns and k + 1 rows are used instead of the memory cell array 8 composed of horizontally stacked memory cells. Memory cell block MB0 which is a vertically stacked memory cell
A memory cell array 8A comprising 0 to MBik is provided, and an X decoder 5A including a difference described later and a test circuit 7B are provided.

Memory cell blocks MB00-MBik
Are NMOS transistors Q000 to Qi stacked vertically
k3. The gates of the transistors in each row of the transistors Q000 to Qik3 are connected to corresponding word lines WL00 to WLi3 of the X decoder 5A, respectively. X decoder 5A includes transistors Q000 to Qik
3 is selectively set to a state corresponding to the off operation.

Each memory cell block MB00-MBik
Output terminals of the NMOS transistors QB00 to QB
Bit lines BL0 to BLk are connected via ik, respectively, and the bit lines BL0 to BLk are connected to the sense amplifier 1 via NMOS transistors QN0 to QNk, as in the first embodiment. Also, the transistor Q
The gates of B00 to QBik are connected to corresponding memory cell block select lines BSEL0 to BSELi of X decoder 5A, respectively. X decoder 5A sets a selected state in which output data from any one memory cell block can be output.

Each of the memory cell blocks MB00-MB
Bik input terminals are respectively virtual ground lines VGL.
0, VGL2 to VGL (i + 1) are connected, and an NMOS for setting the potential of the corresponding virtual ground lines VGL0 to VGL (i + 1) to the ground potential (0V) is connected to the virtual ground lines VGL0 to VGL (i + 1). The transistors QM0 and QM2 to QM (i + 1) are connected.
The gates of the transistors QN0 to QNK inserted in the middle of the bit lines BL0 to BLk are connected to the corresponding column lines CSEL0 to CSELk of the Y decoder 6, respectively.

The test circuit 7B has an NMOS transistor Q0 whose drain is connected to the input terminal and output terminal of each of the memory cell blocks MB00 to MBik, and whose gate is connected in common and connected to the test terminal TT.
, And a common inverter 72 in which the commonly connected gate is connected to the test mode terminal TD and the drain is connected to the commonly connected sources of the transistors Q0 to Qn, respectively. The drains are Q000 to Qi of the memory cell array 8A.
k3, a switch circuit 74A to the gate to the gate of QB00~QBik comprises a plurality of PMOS transistors Q00～Qi 3 or found whose source is connected to the power source to the output of inverter 73, the inverted test signal TEC inverts the test signal TE And a switch circuit 76 including NMOS transistors QM0 to QM (i + 1) whose gates are supplied with the inverted test signal TEC.

As in the first embodiment, when the test signal TE is input to the test signal input terminal TT, the sense amplifier 1, the X decoder 5A, the Y decoder 6, and the charging circuit respond to the supply of the test signal TE. The operations of 3 and 4 are stopped and the transistors Q0 to Q0 of the test circuit 7B are stopped.
Qn turns on. Further, the transistors QM0 to QM (i + 1) are turned off in response to the supply of the inverted test signal TEC.

A test mode signal TM for designating a test mode at the time of a test is applied to a test mode signal input terminal TD.
, The inverter 72 of the test circuit 7B outputs an inverted test mode signal TMB in response to the supply of the signal TM, and this signal TMB is supplied to the switch circuit 71A.
Of each of the memory cell blocks MB00 to MBik via the respective transistors Q0 to Qn.

Next, the operation at the time of the test of this embodiment will be described with reference to FIG. 3. First, a high-level potential is supplied to the test signal input terminal TT as the test signal TE. In response to the supply of the test signal TE, the sense amplifier 1, the X decoder 5A, and the Y decoder 6 stop operating, the transistors QM0 to QM (i + 1) are turned off, and the transistors Q0 to QM of the switch circuit 71A are turned off.
Qn turns on. Next, the test mode signal input terminal T
When the test mode signal TM is supplied to D, the inverter 7
2 is a level inversion signal TMB of the test mode signal TM.
To specify the potentials of the input and output terminals of each of the memory cell blocks MB00 to MBik via the transistors Q0 to Qn. In addition, the inverter 7
3 is a low-level inverted signal T in response to the supply of the signal TE.
EB, and in response to the supply of the inverted signal TEB, the transistors Q00 to Qi3 of the switch circuit 74A are turned on, and the transistors Q000 to Qi of the memory cell array 8A are turned on.
The gate potential of each of ik3, QB00 to QBik is set to a high level.

Referring to FIG. 4A showing the potential of each electrode at the time of testing a part of an arbitrary vertically stacked memory cell block of the memory cell array 8A, when the supplied test mode signal TM is at a high level, , These transistors Q0
The potential of each of the gates 00-Qik3, QB00-QBik attains a high level, and each memory cell block MB00 responds to the supply of the inverted test mode signal TMB.
The potential of the input side terminal and the output side terminal of MBik becomes low level. Since the gate potential is at a high level, the transistors Q000 to Qik3, QB00 to QBi
k is turned on, and these transistors Q000 to Qik
3, the potentials of the sources and drains of QB00 to QBik are all at the low level.

At this time, the junctions of the word lines WL00 to WLi3 and the transistors Q000 to Qik3, QB00 to QB00
If there is a defect in the gate oxide film of QBik and the leak currents I6, I7, I8 flow from the gate to the ground (source, drain, well), even if the leak current is small, the power supply terminal via the switch circuit 74A. Supply current flows into the transistors Q000 to Qik3 and QB00 to QBik from the power supply. Since the sense amplifier 1 is in an operation stopped state, the power supply current value is usually extremely small. On the other hand, if the defect is present, the power supply current value increases by two to three digits. Similarly, the presence / absence of a leak current can be confirmed, and a good / defective product can be determined.

When the test mode signal TM is at a low level, as shown in FIG.
The potentials of the gates of 00 to Qik3 and QB00 to QBik are at the high level, so that they are turned on, and the source and drain potentials are also at the high level. Further, the potentials of the input side terminals and the output side terminals of the memory cell blocks MB00 to MBik are at the high level. At this time, when the leak current I9 or I10 flows from the source or drain to the ground (well), the presence or absence of the leak current can be similarly confirmed by the value of the power supply current, and the non-defective / defective semiconductor memory device can be determined. It can be carried out.

[0036]

As described above, in the semiconductor memory device of the present invention, the test circuit connects each of the drain and source of the memory cell transistor to the test voltage source in response to the supply of the first test signal. A first switch circuit,
A second switch circuit for simultaneously setting a gate potential to a first level; and the test voltage source for setting an output potential to one of a high level and a low level in response to a level of a second test signal. With this arrangement, it is possible to detect a leak current between the gate and the source or the drain or between the gate and the well or between the source and the drain or the well of the transistor for a memory cell. Since it can be determined as defective, there is an effect that long-term reliability can be guaranteed.

Further, by configuring the second switch circuit so as to be adapted to the vertically stacked memory cells, it is possible to achieve a higher integration and a memory cell array composed of vertically stacked memory cells which are superior in layout area to horizontally stacked memory cells. There is an effect that it is also applicable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a part of a semiconductor memory device according to a first embodiment of the present invention in a block diagram.

FIG. 2 is an explanatory diagram showing potentials of respective electrodes when testing a transistor in the semiconductor memory device of the present embodiment.

FIG. 3 is a circuit diagram showing a part of a semiconductor memory device according to a second embodiment of the present invention by using blocks;

FIG. 4 is an explanatory diagram showing potentials of respective electrodes when testing a transistor in the semiconductor memory device of the present embodiment.

FIG. 5 is a circuit diagram showing a part of an example of a conventional semiconductor memory device in a block.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sense amplifier 2 Output buffer 3, 4 Charge circuit 5 X decoder 6 Y decoder 7, 7A, 7B Test circuit 8, 8A Memory cell array 72, 73, 75 Inverter 71, 74, 71A, 74A, 76 Switch circuit

Claims (4)

(57) [Claims] 1. A memory cell array comprising a plurality of first conductivity type MOS transistors arranged in a matrix and forming respective memory cells, and the transistors in an arbitrary row of the memory cell array are electrically connected. A row address decoder for selectively setting a state, a column address decoder for selectively setting a bit line corresponding to the transistor for an arbitrary column of the memory cell array to an output enabled state, and supply of a first test signal A test circuit for stopping a selecting operation of the row address decoder and the column decoder in response to the above, setting a potential of each electrode of all the transistors of the memory cell array to a predetermined level, and executing a predetermined test. Wherein the test circuit responds to the supply of the first test signal. A first test switch circuit that connects each of the drains and sources of all the transistors of the memory cell array to a test voltage source; and a potential of gates of all the transistors in response to the supply of the first test signal. A second test switch circuit for simultaneously setting the output voltage to a first level; and the test voltage for setting an output potential to one of a first level and a second level in response to a level of a second test signal. And a source. 2. The first test switch circuit receives a supply of the first test signal at each gate, and has a drain connected to a drain and a source of the transistor for each column of the memory cell array. A first conductivity type MOS transistor having the same number as the number of the columns connected to the test voltage source; and the second test switch circuit inverting the first test signal at each gate. A plurality of second conductivity type MOS transistors having the same number as the number of the rows in which a signal is supplied, each drain is connected to the gate of the transistor for each row of the memory cell array, and each source is connected to a power supply. 2. The semiconductor memory device according to claim 1, wherein: 3. The test voltage source comprises second and first conductivity type MOS transistors connected in series, and inverts the second test signal to generate the first and second level voltages. Characterized by comprising an inverter circuit
The semiconductor memory device according to claim 1 . 4. A memory cell array having a memory cell block comprising a series connection of a plurality of first conductivity type MOS transistors which are arranged in a matrix and form memory cells, and any one of the memory cell arrays. A row address decoder for selectively setting the transistors in a row to a non-conduction corresponding state and a column address decoder for selectively setting a bit line corresponding to the transistor in an arbitrary column of the memory cell array to an output enabled state And the first
In response to the supply of the test signal, the selection operation of the row address decoder and the column decoder is stopped, and the potential of each electrode of all the transistors of the memory cell array is set to a predetermined level to execute a predetermined test. A test circuit to execute the test circuit, wherein the test circuit responds to the supply of the first test signal by setting a drain and a source of each transistor of all the memory cell blocks of the memory cell array. A first test switch circuit connected to a test voltage source; and a second test switch for simultaneously setting the potentials of the gates of all the transistors to a first level in response to the supply of the first test signal. A circuit; and an output potential in response to a level of the second test signal, the output potential being one of a first level and a second level. The semiconductor memory device characterized by comprising a voltage source for the test set.