JP2789792B2 - Pulse output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse output circuit, and more particularly to a pulse output circuit built in a microcomputer used for a servo control circuit of a VTR (vide tape recorder) device.

[Conventional technology]

In recent years, microcomputers have been used for servo control circuits of VTR devices. This is intended to improve reliability and obtain flexibility corresponding to various television systems by replacing a servo control circuit which has conventionally been constituted by an analog circuit with a microcomputer. Since analog servos are also inexpensive, they are considered to coexist for the time being. Therefore, in order to facilitate the introduction of a servo control circuit by a microcomputer, it is desirable to make the parts other than the servo control circuit the same as in the case of the analog servo.

However, in a current VTR device, a ternary control signal is used in a signal processing circuit that is closely related to a servo to save arrangement. A servo control circuit needs to output a control signal to a signal processing system at a predetermined timing. However, a pulse output circuit built in a conventional microcomputer can output only a low level and a high level and cannot directly output a binary value. Could not connect to signal processing system. For example, a pseudo-vertical synchronization (VSYNC) signal at the time of trick play (slow, still) inputs a control signal shown in FIG. 6 (a) to a signal processing system. The signal processing system outputs a reproduced video signal when the control signal is at "L" level, outputs a synchronization signal when it is at "M" level, and outputs a pedestal level when it is at "H" level. This signal processing can be realized with an inexpensive dedicated IC. However, when servo control is performed by a microcomputer, since ternary values cannot be output, an inexpensive dedicated IC cannot be used, and the circuit of the signal processing system needs to be changed. For this reason, the cost and the mounting area have increased due to the increase in the number of components and wiring. In addition, in the current situation in which analog servos and servos by microcomputers coexist, the inability to share circuits and components of the signal processing system has led to an increase in design man-hours and manufacturing costs.

[Problems to be solved by the invention]

Conventional pulse output circuits have two levels, low level and high level.
Since only values can be output, signal processing ICs that require ternary control signals when using VTR servo control
Could not connect to.

[Means for solving the problem]

A pulse output circuit according to the present invention includes a timer circuit for generating a timing signal, a first state, a second state, and a third state.
A state generating circuit having a state and changing the state in response to the timing signal; an output terminal; a first level at the output terminal; a second level different from the first level;
A switch circuit for outputting a third level different from the first and second levels; and, when the state generating circuit is in the first state, causing the switch circuit to output the first level; A logic circuit that causes the switch circuit to output the second level when the switch circuit is in the state, and a third circuit that outputs the third level when the switch circuit is in the third state. And a control device for controlling and initializing the state generating circuit to any one of the first state, the second state, and the third state.

Thus, a low level is output in the first state, a high level is output in the second state, and a level different from both the low level and the high level is output in the third state. Since the state generating circuit changes the state according to the timing signal, it can output three values as a pulse output.

〔Example〕

 FIG. 1 is a block diagram of one embodiment of the present invention.

The timer circuit 1 is a preset timer circuit, and outputs a timing signal to the timing signal line 2 when a set time is reached.

 The timing signal line 2 transmits a timing signal.

The state generating circuit 3 includes two-bit latches 4,
It comprises a latch 5 and transfers the value stored in the latch 4 to the latch 5 in synchronization with the timing signal and outputs it as a state.

The logic circuit 6 controls the first switch element 7 and the second switch element 8 according to the logic shown in Table 1 according to the state of the state generation circuit 3.

The first switch element 7 has a higher power supply potential of 5
This is a P-channel MOS transistor that connects [V] to the output terminal 9.

The second switch element 8 has a low power supply potential of 0.
This is an n-channel MOS transistor that connects [V] to the output terminal 9.

The central processing unit 10 presets the timer circuit 1 and sets the state of the latch 4 of the state generating circuit 3.

Both the resistors 11 and 12 externally connected to the output terminal 9 are 5
This is for setting the potential of the output terminal 9 to 25 [V] when the output terminal 9 is in a high impedance state with a resistance of [KΩ].

 Next, the operation will be described with reference to FIG.

It is assumed that the state generating circuit 3 is in the state 1 as an initial state. At this time, the first switch element 7 is released and the second switch element 8 is conductive, so that the output terminal 9 is set to 0.
[V] is output.

The central processing unit 10 at time T ₁ of the state change in the timer 1 in FIG. 2 (a), respectively set the next state 01 to the latch 4. Therefore, the value of the latch 5 to the time T ₁ is 01 next second
State. At this time, the first switch element 7 becomes conductive,
Since the second switch element 8 is open, the output terminal 9 outputs 5 [V].

Figure 2 similarly (b), (c) in each time T _2, a third
The case of the state at time T ₃ shows a case where the first state. In the third state, since both the first switch element 7 and the second switch element 8 are open, the output terminal 9 is in a high impedance state, and the resistance 11 and the resistance 1
By the voltage division of 2, the potential of the output terminal 9 becomes 2.5 [V].

Accordingly, by setting the time and the state by the central processing unit 10, a pulse output which outputs one of three values of 0 [V], 2.5 [V] and 5 [V] at an arbitrary time is obtained. Therefore, by setting the time and state as shown in FIG.
A control signal for the pseudo VSYNC signal can be created.

In the present embodiment, the first switch element 7 and the second switch element 8 are both opened in the third state, and the output terminal 9 is set to 2.5 by the voltage division of the external resistors 11 and 12.
[V], but the output logic of the theoretical circuit 6 is inverted, and in the third state, the first switch element 7,
A configuration in which both the second switch elements 8 are turned on may be employed. In this case, the first switch element 7 and the second switch element 8 are designed to have the same resistance (on resistance) when conducting, so that 2.5 [V] is output without connecting the resistance 11 and the resistance 12. be able to. Therefore, the number of components can be reduced and the mounting area can be reduced.

 FIG. 4 shows a block diagram of a second embodiment of the present invention.

The theoretical circuit 69 has the control input terminal 13 connected to the theoretical circuit 6 of the mounting example 1.
The operation when the control input terminal 13 is at the low level is the same as that of the first embodiment. When the control input terminal 13 is at a high level, the first
Switch element 7 is in an open state. The second switch element 8 is not affected.

The pulse generation circuit 14 generates a high active horizontal synchronization pulse.

 Next, the operation will be described.

Since the control input terminal has only the function of opening the switch element, the operation in the first state and the operation in the third state are the same as those in the first embodiment. The second embodiment differs from the first embodiment only when the control input terminal 13 goes high in the second state. At this time, both the first switch element 7 and the second switch element 8 are open. That is, it becomes the same as the third state. Therefore, when the second state is set in this embodiment, the output terminal 9 supplies 5 [V] to the output terminal 9 during the period when the horizontal synchronization pulse is at the inactive level and 2.5 [V] during the period when the horizontal synchronization pulse is at the active level. V]. Therefore, in order to obtain the same control signal as in FIG. 3, the central processing unit 10 only needs to make the settings shown in FIG. Normally, approximately five horizontal synchronizing pulses are cut into the pseudo VSYNC signal, so in the first embodiment, 13 settings are required to obtain the waveform of FIG. 3, but in this embodiment, FIG. As can be seen, three settings are sufficient. In the first embodiment, the central processing unit 10 is required to operate at a high speed in order to cut the horizontal synchronization pulse. In the present embodiment, since the pulse is cut by the pulse generation circuit 14, the central processing unit 10
Can be slow. For example, in FIG. 3, from time T ₂ to T ₃
It is necessary to only the third state during the time of T ₃ from T ₂ are about 5 [.mu.s] only without, during the next timing (T ₃₎ the next state (second state) Must be set. In this embodiment, since this processing is not required, there is an advantage that the central processing unit 10 can be operated at low speed and at low cost.

〔The invention's effect〕

As described above, since the pulse output circuit of the present invention can output three values, it can be directly connected to the VTR signal processing IC.
Therefore, there is an effect that the servo control circuit by the microcomputer can be realized inexpensively and compactly.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is an operation timing chart of the present embodiment of the present invention, and FIG. 3 is a timing chart for generating a pseudo VSYNC signal of one embodiment of the present invention. FIG. 4, FIG. 4 is a block diagram of another embodiment of the present invention, FIG. 5 is a timing diagram for generating a pseudo VSYNC signal in this embodiment of the present invention, and FIG. 6 is for generating a pseudo VSYNC signal. FIG. 3 is a diagram illustrating control signals of FIG. DESCRIPTION OF SYMBOLS 1 ... Timer circuit, 2 ... Timing signal line, 3 ... State generation circuit, 4 ... Latch, 5 ... Latch, 6 ... Theoretical circuit, 7 ... First switch element, 8 ... Second Switch element, 9 output terminal, 10 central processing unit, 11
Resistor, 12: Resistor, 13: Control input terminal, 14: Pulse generator circuit, 60: Logic circuit.

Claims (4)

(57) [Claims] A timer circuit for generating a timing signal;
A state generating circuit having a first state, a second state, and a third state and changing the state in response to the timing signal; an output terminal; And a switch circuit for outputting a second level different from the first level and a third level different from the first and second levels, and the switch circuit outputs the second level when the state generating circuit is in the first state. A logic circuit for outputting the first level, causing the switch circuit to output the second level in the second state, and outputting the third level to the switch circuit in the third state. And a control device for setting and controlling the generation time of the timing signal, and performing processing for initializing the state generation circuit to any of the first state, the second state, and the third state. Characteristic pulse output circuit 2. A signal processing circuit connected to said output terminal, said signal processing circuit outputting a reproduced video signal when said first level is output to said output terminal, and outputting a reproduced video signal when said second level is output. 2. The pulse output circuit according to claim 1, further comprising a signal processing circuit that outputs a synchronization signal and outputs a pedestal level when the third level is output. 3. A timer circuit for generating a timing signal,
A state generating circuit having a first state, a second state, and a third state and changing a state in response to the timing signal; an output terminal; and a third circuit connecting the output terminal to a first power supply line. 1 switch element, a second switch element for connecting the output terminal to a second power supply line, and the first switch element in a non-conductive state when the state generating circuit is in the first state. At the same time, the second switch element is turned on, and in the second state, the first switch element is turned on, and the second switch element is turned off. A logic circuit that renders both the first switch element and the second switch element non-conductive; a first load element that connects the output terminal to the first power supply line; The second power line A second load element to be connected; and a control circuit for performing processing for initializing the state generating circuit to any one of the first state, the second state, and the third state. Pulse output circuit. 4. A timer circuit for generating a timing signal,
A state generating circuit having a first state, a second state, and a third state and changing a state in response to the timing signal; an output terminal; and a third circuit connecting the output terminal to a first power supply line. 1 switch element, a second switch element for connecting the output terminal to a second power supply line, and the first switch element in a non-conductive state when the state generating circuit is in the first state. At the same time, the second switch element is turned on, and in the second state, the first switch element is turned on, and the second switch element is turned off. And a logic circuit that makes both the first switch element and the second switch element conductive, and sets the state generating circuit to one of the first state, the second state, and the third state. System that initializes Pulse output circuit, characterized in that it comprises a circuit.