JP2791762B2 - Arithmetic unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit capable of high-speed arithmetic processing, and more particularly to a specific-purpose logical arithmetic unit.

[0002]

2. Description of the Related Art A general arithmetic device having a conventional CPU processes a program in a stepwise manner. At the stage of processing the program, a program stored in an external memory is used to execute instructions necessary for the arithmetic processing. Had to read. For example, when an attempt is made to accumulate in a conventional arithmetic unit, the processing results in a step situation as shown in FIG. That is, in the conventional device, the instruction access, the input 1, the instruction access, the result input 1, the instruction access, the addition 1, the instruction access, the result storage 1, the instruction access, and the result output 1 are performed in one accumulation. 10 steps were required, and an instruction access was required for each step. Therefore, in order to obtain five operation result outputs by this device, processing of 50 steps is necessary.

[0003]

In such a conventional arithmetic device, necessary instructions must be read during the processing of a program, and all arithmetic processing is performed in a stepwise serial manner. There is a problem that the processing speed becomes slow. Further, there is a case where a conventional arithmetic device is operated in parallel to increase the speed. However, each of the arithmetic units used therein must perform an operation serially in a stepwise manner and read a repetitive instruction. Therefore, the same problem as described above remains in that the processing speed is reduced. SUMMARY OF THE INVENTION It is an object of the present invention to provide an arithmetic device which does not require instruction access and can perform high-speed processing.

[0004]

An arithmetic unit according to the present invention comprises:
A rectangular ALU assembly having an LU, wiring, and input / output ports, a bus, and an arbiter connected to an end of the bus for permitting control of signal output to the bus; Placed on top of one of the ALU structures A
Connect the LU unit to the external input unit and connect the other ALU
A flow graph code is connected as a signal for connecting a knitted structure to an external output unit, connecting all the ALU knitted structures via the bus, and hardening a program for setting up the connection relationship and the sharing of individual functions from the external input unit. A logical operation circuit for a specific use is formed on the board by using the ALU organization storing the individual functions according to the flow graph code and the arbiter. The n-th side of the opposite side of the ALU knitted body
Providing an input port, providing an n-th output port on the other side,
The distance from the other side to the n-th input port is equal to the distance from the one side to the n-th output port, and the n-th input / output port is arranged.

[0005] With the above configuration, a flow graph code is input from an external input unit as a means for hardening a program for setting individual functions and connecting relations (setup) according to processing to be executed by the arithmetic unit. if,
Each ALU organization stores and holds its own arithmetic processing content according to its flow graph code. In this state, each AL
The U knitted body becomes an arithmetic element having individual functions, and this device is set, that is, set up as an arithmetic device dedicated to processing according to the flow graph code. Then, next, when predetermined data is input from the external input unit, each ALU organization executes an arithmetic process according to the set individual function without command access. In addition, since the positional relationship between the input / output ports on each side of the ALU assembly is set as described above, the ALU assembly having the same configuration is simply arranged in a matrix on the board, and the ALU assembly of the adjacent ALU assembly can be used. n input ports;
The nth output port is inevitably connected, and the input / output port directly connects the adjacent ALU organization.
Therefore, there is no need to adjust the positions of the input / output ports for connection between the ALU assemblies, and the ALU assemblies having the same configuration can be arranged at all positions, which is economical. Further, by arranging the devices in a matrix, it is easy to reduce the size of the entire device. Note that the same configuration here includes that which becomes a symmetrical figure.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is an enlarged view of an arbiter connection portion. FIG. 3 and FIG. 4 are a block diagram of the ALU knitted structure 4 of FIG. 1 and an arrangement explanatory view of input / output ports, respectively. Figure 1
In the first embodiment shown in FIG.
The ALU organization 4 having a _ij as a main element is arranged in an N × N matrix (where i and j are integers satisfying 1 ≦ i, j ≦ N). Thus, N ² ALU a _ij can be arranged on the substrate 1. The ALUa ₁₁ is connected to the external input unit 2, and the ALUa _N1 is connected to the external output unit 3. As shown in FIG. 3, a logic setting storage element b _ij is connected to each ALU a _ij of the ALU organization 4 by a channel 9.
ALUs adjacent to each other on the left, right, up and down are connected to each other via a pair of adjacent wirings 5 and 6 for input and output.

Buses x _i , y _j are provided between the ALU matrices, and each ALU a _ij is connected to the nearest bus x _i , y _j via a pair of input / output bus connection channels 7 and 8. doing. As described above, the ALU organization 4 includes ALUa _ij and
The logic setting storage element b _ij and the left and right ALU a _{i (j−1)} , a
a pair of adjacent wirings 5 for connecting to _{i (j + 1)} , a pair of adjacent wirings 6 for connecting to ALUa _{(i-1) j} , a _{(i + 1) j} located above and below, and a bus x _i , y _j , channels 7, 8 connecting ALU a _ij to these buses x _i , y _j , and logical setting storage elements b _ij are connected to the left and right adjacent logical setting storage elements bi _(j−1) , b
channel 10 connected to _{i (j + 1),} and logical setting storage element b
_ij and a channel 9 connecting ALUa _ij . In FIGS. 1-3, each bus x _i indicated by a single line, y _j
Are used as transmission paths for signals in both directions.

The input / output ports located on each side of the ALU knitted body 4 are represented by I and O. For example, the input port of the adjacent wiring 5 is 5 _I , the output port is 5 _O, and the input / output port of the bus x _i is x _IO . These input / output ports are arranged as shown in FIG. On the left side,
Input port 1 of channel 10 at a distance m ₁ from the upper side
0 _I, an output port 5 _O positions in adjacent wire 5 of the distance m _2, the distance m ₃ input ports 5 _I, the distance m _4, provided input and output ports x _IO bus x _N, the opposite side is Again, at the positions of distances m ₁ , m ₂ , m ₃ , and m ₄ from the upper side, respectively, the output port 10 _O of the channel 10, the input port 5 _I of the adjacent wiring 5, the output port 5 _O , input and output ports x _IO bus x _N is provided. On the top and bottom sides, the output and input ports 6 _O and 6 _{I of} the channel 6 are located at a distance s ₁ from the left side, and the input and output ports 6 _I and 6 _O are located at a position s ₂ , respectively. also, the position of s ₃ is provided with input and output ports y _IO bus y _n.

When the ALU assemblies 4 are arranged in a matrix, adjacent wirings and respective channels are inevitably connected as shown in FIG. In order to connect all the logic setting storage elements b _ij in series, the external wiring 1
1 and 12 are provided. With these external wirings 11 and 12, logic setting storage elements b _ij located at both ends, for example, b
_1N and b _2N , b ₂₁ and b ₃₁ can be connected. However, the orientation of the signal of the channel 10 of the logic setting storage element b ₂₁ ~b _2N, because in the opposite direction to FIG. 3, FIG. 3, used as configured symmetrically to ALU knitting 4 shown in FIG. The same applies to the case of the logic setting storage elements b _4j , b _6j . The bus x ₀ is a bath set to connect two buses in the vertical direction, ALU is not connected. ALUa
bus x _i provided between _ij matrix, and y _j, by bus x _i, y _j provided next to ALUA _ij matrix, and bus x _0, x _N, y
Also includes those provided outside the matrix, such as _N. A bus x ₀ ~x _N provided laterally to the respective end of the longitudinal direction of the bus y ₁ ~y _N, arbiter 13 and 14 to control the timing of the output permission from the ALU to the bus is connected .

As shown in FIG. 2, the arbiter 14 has a memory 18 and can store a teaching schedule input from the external input unit 2. This teaching schedule is an AL with an arbiter
This is data for giving output permission in the order determined for U. The arbiter 13 has a similar memory 17. Between the longitudinal direction of the bus y ₁ ~y _N and bus x _0, optionally switches S ₁ to S _N are connected, and to switch the connection of the horizontal and vertical buses. These switches S _{1 to} S _N
Is configured to perform switching in synchronization with the timing of the arbiter 13 _a connected to the bus x _0. For example, when transmitting signals from non-adjacent ALUa ₃₁ to ALUa ₂₃ , both ALUs must be connected via a bus. First, the output permission of the arbiter 14a connected to the bus y _1, ALUA ₃₁ outputs a signal to the bus y _1. Under the control of the arbiter 13a connected to the bus x0,
Closes switch S _1, the connected bus y ₁ and the bus x _0, closes S _3, bus x ₀ and bus y ₃ is to connect. As a result, the signal is transferred to the ALUa ₂₃ via the bus y ₁ → the bus x ₀ → the bus y _3.
Is input to

Next, the operation of the first embodiment will be described.
First, a function sharing code which is a flow graph code for sharing the individual functions of the ALU a _ij of each ALU organization 4 is input from the external input unit 2 to the logic setting storage element b _ij . At this time, the function sharing code from the external input unit 2 is:
The data is input from the channel 10 to the logic setting storage element _bij .
The logic setting storage element b _ij is connected to the logic setting storage element b ₁₁ → b ₁₂ →, by the channel 10 and the external wires 11 and ₁₂ .
..., → b _1N → wiring 11 → logic setting storage element b _2N →, ...,
→ b _N1 connected in series. Therefore,
The function sharing code input by the flow graph code from the external input unit 2 to the logic setting storage element b ₁₁ is transmitted to the logic setting storage element b ₁₂ and the logic setting storage element b by the channel 10.
₁₃ … and so on. As a result, the function sharing code is inversely input from the N ² -th logical setting storage element b _N1 and finally input to the logical setting storage element b ₁₁ .
This completes the input of the function assignment code, and the logic setting storage element b _{ij that} has received each function assignment code stores the input code content and sets an individual function in the ALU a _ij . This individual function includes not only the operation function of each ALUa _ij but also the function of switching connections with other ALUs.

A teaching schedule, which is a switching timing of the switch S, is input from the external input unit 2 to the memory 18 of the arbiters 13 and 14 separately from the function sharing code. Since the arbiter 13 and the arbiter 14 are connected in series by one wire 16, the teaching schedule is also set to the arbiter 14 directly connected to the external input unit 2.
Input can be made sequentially from a. When the setting of the individual functions of the ALU _ij and the input of the teaching module are completed in this way, the logic circuit of the arithmetic unit is formed, and the setup is completed as a logic circuit for a specific application. That is, the hardware of the flow graph code for a specific use is completed. When the purpose of the device is changed, the logical setting storage elements b _ij and
What is necessary is just to input a flow graph code corresponding to the intended use to the arbiters 13 and 14, and to perform a re-setup. In this state, if data is input to the ALUa ₁₁ set as the input unit, the data is sent to another ALUa _ij according to the set logic circuit, and is repeatedly processed.
Finally, the function of the output unit is output from the set ALUa _N1 to the external output unit 3.

[0013] Of the data input to and processed by the ALU a _ij , the data is transmitted to adjacent ALUs via the channels 5 and 6, and to the other ALUs via the buses x _i and y _j. . A plurality of ALUs are connected to each bus x _i , y _j . For example, the bus x _1, ALUA from above
₁₁ ~a _1N is connected. That is, N ALUs are connected to one bus. These ALU arbiter 13b so as not to output a signal to the bus x ₁ is adjusted at the same time. The arbiter 13b is so stored in the memory 18 of the timing for providing an output permission to the ALU connected to the bus x ₁ as teaching schedule, according to the schedule, may be given the output permission. The arbiter may not have this memory 18. However, in that case, the arbiter 13b is always so needs to monitor all of the ALU connected to the bus x _1, it is necessary arbiter to operate at very high frequencies.

If such an arithmetic device is set up by itself, it becomes a special-purpose arithmetic device for which the purpose of performing necessary arithmetic processing is specified, and the access to the memory unlike the conventional device is unnecessary. Even when obtaining the same calculation result as in the conventional example, instruction access is not required, so that the number of processing steps for obtaining one output is reduced by half. In the apparatus of the present embodiment, since each ALU _ij is set with an individual function in order to perform each processing, when obtaining a plurality of outputs, each step can be performed simultaneously. For example, FIG. 6 shows the processing status when performing accumulation. As shown in FIG. 6, according to this embodiment, input → result input → addition → result storage → result output can be performed simultaneously by shifting one step. In order to obtain five result outputs, 50 steps were required in the conventional apparatus, but 9 steps are sufficient in the present invention. Therefore, there is an effect that the operation time is greatly reduced. Then, as the processing becomes more complicated and the number of steps increases, the difference increases.

The ALU knitting body 4 constituting the logical operation circuit capable of performing such high-speed operation processing is configured as shown in FIGS. 3 and 4.
If they are simply arranged in a matrix on the board, the n-th input port and the n-th output port of the adjacent ALU are inevitably connected. With this input / output port, adjacent ALU units are directly connected, and the bus is continuous. The ALU knitted body 4 configured in the same manner can be arranged at all positions. Therefore, when developing a single ALU knitting 4, it will be developed the N ² pieces of ALU knitting 4, which is economical. Further, by arranging the devices in a matrix, it is easy to reduce the size of the entire device. In particular, one A
If the area of the LU knitted body 4 can be reduced, N ²
Since it can be reduced twice, it greatly affects the price of the device. For example, if the area of the logical operation circuit can be reduced by 20%, the price is currently reduced to less than half. In the present embodiment, the logic setting storage elements b _ij are all connected in series, and the input code is configured to be sequentially forwarded.
The code corresponding to each logic setting storage element b _ij may be directly input. However, when inputting individually, N ² input ports are required.

A second embodiment shown in FIG. 5, the first row of the logic setting the memory element b ₁₁ directly connected to the external input unit 2, logical setting storage element b ₂₁ ~b _N1 follows the second row, It is connected to the external input unit 2 via the changeover switch 17. The changeover switch 17 as described above opens and closes according to an output signal from the external input unit 2. That is, the external input unit 2 is, for example, the logic setting storage element a _{11 in} the first row.
~a to code input to _1N is completed, Maintain an open switch 17. Then, when the code input of the first row is completed, so as to close the switch 17 connected to the logic setting storage element b ₂₁ of the second row, the external input section 2 issues a command. In this way, by sequentially closing the changeover switches 17 connected to each row,
A predetermined sharing code is input to the logic setting storage element of each row.

In the case of the second embodiment, the signal flow direction of each logic setting storage element is the same. Therefore, the ALU knitted body 4 does not have to be symmetrical as in the first embodiment. In the second embodiment,
The changeover switch 17 is opened and closed by a control signal from the external input unit 2. However, if the changeover switch 17 is provided with a counting function, the control signal from the external input unit 2 becomes unnecessary. In other words, when the changeover switch 17 counts the number of logic setting storage elements in each row in the order of code input and counts the same number as the predetermined number of logic setting storage elements in that row, it outputs a signal to close the changeover switch in the next row. do it.

[0018]

According to the arithmetic unit of the present invention, during the processing of a program, there is no need to access an instruction for processing the program, so that the calculation speed is increased accordingly. In addition, when the result output can be repeated, the processing can be performed in parallel by shifting the steps, so that high-speed processing has become possible. Such a device is connected to the same pattern AL
By arranging the U knitted body, it can be realized, and the device cost and the development cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is an enlarged view of an arbiter connection portion of FIG.

FIG. 3 is a block diagram of the ALU knitted body of FIG. 1;

FIG. 4 is an explanatory diagram of an arrangement of input / output ports of the ALU knitted body of FIG. 1;

FIG. 5 is a block diagram of a second embodiment.

FIG. 6 is a diagram illustrating an accumulation processing state according to the first embodiment;

FIG. 7 is a diagram shown to explain an accumulation processing state in a conventional example.

[Explanation of symbols]

1 substrate 2 external input unit 3 external output unit 5, 6 adjacent lines 13 and 14 the arbiter x _i, y _j bus a _ij ALU b _ij logic setting storage element 5 _I, 6 _I, 10 _I input port 5 _O, 6 _O, 10 _O output port x _IO , y _IO input / output port

Claims (1)

(57) [Claims] 1. A rectangular ALU assembly comprising an ALU, wiring, and input / output ports, a bus, and an arbiter connected to an end of the bus for permitting control of signal output to the bus. The ALU knitted body is placed on the board, and one of the ALU knitted bodies is connected to the external input unit,
A signal for connecting another ALU unit to an external output unit, connecting all the ALU units via the bus, and hardening a program for setting up the sharing of the individual functions and the connection relationship from the external input unit. A logic operation circuit for a specific use is formed on the board by using the ALU assembly storing the individual functions according to the flow graph code and the arbiter. In addition, the n-th input port is provided on one side of the opposite side of the ALU knitted body, the n-th output port is provided on the other side, the distance from the other one side to the n-th input port, and the one side An n-th input / output port, wherein the distance from the first to the n-th output port is equal.