JP2793553B2 - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JP2793553B2 JP2793553B2 JP10524696A JP10524696A JP2793553B2 JP 2793553 B2 JP2793553 B2 JP 2793553B2 JP 10524696 A JP10524696 A JP 10524696A JP 10524696 A JP10524696 A JP 10524696A JP 2793553 B2 JP2793553 B2 JP 2793553B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- metal plate
- electric wiring
- multilayer ceramic
- ceramic capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/547—Dispositions of multiple bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置用パッケ
ージに関し、特に半導体素子を搭載するとともに、積層
セラミックコンデンサを備えた半導体装置用パッケージ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package for a semiconductor device, and more particularly to a package for a semiconductor device on which a semiconductor element is mounted and which has a multilayer ceramic capacitor.
【0002】[0002]
【従来の技術】従来、かかる半導体装置用パッケージ
は、積層セラミックコンデンサを搭載する電気的配線基
板と、半導体素子を搭載する金属板とを備え、この金属
板を半導体素子の放熱用に用いている。例えば、近年の
半導体素子の高速化および大消費電力化に伴い、グラン
ドバウンスノイズの低減を目的として積層セラミックコ
ンデンサを搭載したり、あるいは半導体素子の発熱を効
率よく放熱することを目的として金属板を用いたりする
パッケージが増加している。2. Description of the Related Art Conventionally, such a semiconductor device package includes an electric wiring board on which a multilayer ceramic capacitor is mounted, and a metal plate on which a semiconductor element is mounted, and this metal plate is used for heat dissipation of the semiconductor element. . For example, with the recent increase in speed and power consumption of semiconductor devices, multilayer ceramic capacitors are mounted for the purpose of reducing ground bounce noise, or metal plates are used for the purpose of efficiently dissipating heat generated by semiconductor devices. The number of packages used is increasing.
【0003】図3(a),(b)はそれぞれ従来の一例
を説明するための半導体装置用パッケージの上面図およ
びそのA−A’断面図である。図3(a),(b)に示
すように、かかるパッケージは、電気的配線基板1と、
半導体素子9を搭載するとともに電気的配線基板1に固
着される金属板4aとを備えている。この電気的配線基
板1は中央に開口部2を形成し、下面より電気的接続用
の複数の外部端子3を導出している。また、その開口部
2内に金属板4aに固着した半導体素子9が位置するよ
うに配置するとともに、上面には半導体素子9を囲む位
置(4個所)に電源端子8aおよびグランド端子8bを
有する積層セラミックコンデンサ7を搭載する。一方、
金属板4aは中央に半導体素子9を固定する素子搭載部
6を形成し、電気的配線基板1の上面に固着される。こ
のため、電気的配線基板1の開口部上面は金属板4aで
閉塞され、開口部2内に半導体素子9が配置される。FIGS. 3 (a) and 3 (b) are a top view of a semiconductor device package and an AA 'cross-sectional view thereof for explaining one example of the prior art. As shown in FIGS. 3A and 3B, such a package includes an electric wiring board 1,
A metal plate 4a on which the semiconductor element 9 is mounted and which is fixed to the electric wiring board 1; The electrical wiring board 1 has an opening 2 formed in the center, and a plurality of external terminals 3 for electrical connection are led out from the lower surface. In addition, the semiconductor element 9 fixed to the metal plate 4a is arranged so as to be located in the opening 2, and the power supply terminal 8a and the ground terminal 8b are provided at positions (four places) surrounding the semiconductor element 9 on the upper surface. The ceramic capacitor 7 is mounted. on the other hand,
The metal plate 4 a forms an element mounting portion 6 for fixing the semiconductor element 9 at the center, and is fixed to the upper surface of the electric wiring board 1. For this reason, the upper surface of the opening of the electric wiring board 1 is closed by the metal plate 4 a, and the semiconductor element 9 is arranged in the opening 2.
【0004】さらに、半導体素子9が金属細線10によ
り配線基板1のパッド(図示省略)とボンディング接続
された後、電気的配線基板1の開口部下面は金属キャッ
プ11などにより遮断し、外部より保護する。なお、こ
の半導体素子9と外部回路との電気的接続は、前述した
外部端子3により行う。また、積層セラミックコンデン
サ7は、一般に電気的配線基板1の上面の金属板4aの
取り付け部外側に設けられた電源端子8aとグランド端
子8bに電気的に接続された状態で搭載される。Further, after the semiconductor element 9 is bonded and connected to a pad (not shown) of the wiring board 1 by a thin metal wire 10, the lower surface of the opening of the electric wiring board 1 is blocked by a metal cap 11 or the like to protect it from the outside. I do. The electrical connection between the semiconductor element 9 and an external circuit is made by the external terminal 3 described above. The multilayer ceramic capacitor 7 is generally mounted in a state of being electrically connected to a power supply terminal 8a and a ground terminal 8b provided on the upper surface of the electric wiring board 1 outside the mounting portion of the metal plate 4a.
【0005】かかる構造の半導体装置用パッケージにお
いて、これら積層セラミックコンデンサ7および金属板
4aは、セラミック基板やプラスチック基板からなる電
気的配線基板1の上面に取り付けるのが一般的である。
すなわち、電源ライン・接地ライン間の電位変動である
グランドバウンスノイズを低減させるための積層セラミ
ックコンデンサ7は、その搭載位置が半導体素子9にに
りょり近いほど有効である。特に、グランドバウンスノ
イズを重視する製品については、積層セラミックコンデ
ンサ7の搭載部より内側に取り付けられる金属板4aの
寸法を可能な限り小さくなるように設計している。In a semiconductor device package having such a structure, the multilayer ceramic capacitor 7 and the metal plate 4a are generally mounted on the upper surface of an electric wiring board 1 made of a ceramic substrate or a plastic substrate.
That is, the multilayer ceramic capacitor 7 for reducing the ground bounce noise, which is a potential fluctuation between the power supply line and the ground line, is more effective as the mounting position thereof is closer to the semiconductor element 9. In particular, for products in which ground bounce noise is important, the dimensions of the metal plate 4a mounted inside the mounting portion of the multilayer ceramic capacitor 7 are designed to be as small as possible.
【0006】[0006]
【発明が解決しようとする課題】上述した従来の半導体
装置用パッケージは、電気的配線基板の上面に取り付け
られた金属板の外側に積層セラミックコンデンサを搭載
する構造になっているため、積層セラミックコンデンサ
の搭載位置を半導体素子に近づけるほど、金属板の取り
付け面積が減少する。したがって、グランドバウンスノ
イズ低減を重視すればするほど、半導体素子の動作時の
発熱に対する放熱特性を著しく阻害するという欠点があ
る。The above-described conventional package for a semiconductor device has a structure in which a multilayer ceramic capacitor is mounted outside a metal plate mounted on an upper surface of an electric wiring board. The closer the mounting position is to the semiconductor element, the smaller the mounting area of the metal plate becomes. Therefore, the more the emphasis is placed on reducing ground bounce noise, the more disadvantageously the heat dissipation characteristic of the semiconductor element against heat generation during operation is significantly impaired.
【0007】本発明の目的は、かかる積層セラミックコ
ンデンサを半導体素子の近傍に配置してグランドバウン
スノイズを低減すると同時に、放熱特性を阻害すること
のない半導体装置用パッケージを提供することにある。An object of the present invention is to provide a package for a semiconductor device in which such a multilayer ceramic capacitor is arranged near a semiconductor element to reduce ground bounce noise and at the same time does not hinder heat radiation characteristics.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置用パ
ッケージは、中央に開口部を形成し且つ下面より電気的
接続用の複数の外部端子を導出させた電気的配線基板
と、前記電気的配線基板の上面に固着するとともに前記
電気的配線基板の前記開口部の上面側を閉塞するように
素子搭載部を形成した金属板と、前記開口部内に位置す
る前記金属板の前記素子搭載部に固定された半導体素子
と、前記電気的配線基板の上面に且つ前記半導体素子を
囲む位置に搭載した積層セラミックコンデンサとを有
し、前記電気的配線基板の上面の前記金属板を前記積層
セラミックコンデンサの外側にまで延在させて構成され
る。According to the present invention, there is provided a package for a semiconductor device, wherein an opening is formed in the center and a plurality of external terminals for electrical connection are led out from a lower surface; A metal plate fixed to an upper surface of a wiring board and having an element mounting portion formed so as to close the upper surface side of the opening of the electrical wiring substrate; and an element mounting portion of the metal plate positioned in the opening. A fixed ceramic element, and a multilayer ceramic capacitor mounted on the upper surface of the electrical wiring board and at a position surrounding the semiconductor element, wherein the metal plate on the upper surface of the electrical wiring board is It is configured to extend to the outside.
【0009】また、本発明の半導体装置用パッケージに
おける前記金属板は、前記電気的配線基板上に設けた前
記積層セラミックコンデンサの周囲に開口部を形成し、
前記電気的配線基板の上面のほとんどを覆うように形成
される。In the semiconductor device package according to the present invention, the metal plate has an opening formed around the multilayer ceramic capacitor provided on the electric wiring board,
It is formed so as to cover most of the upper surface of the electric wiring board.
【0010】さらに、本発明の半導体装置用パッケージ
における前記金属板は、前記電気的配線基板上に設けた
前記積層セラミックコンデンサの近傍に凹部を形成し、
前記電気的配線基板の上面の残りの部分のほとんどを覆
うようにして形成される。Further, in the semiconductor device package according to the present invention, the metal plate has a concave portion formed in the vicinity of the multilayer ceramic capacitor provided on the electric wiring board,
It is formed so as to cover most of the remaining portion of the upper surface of the electric wiring board.
【0011】[0011]
【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【0012】図1(a),(b)はそれぞれ本発明の一
実施の形態を説明するための半導体装置用パッケージの
上面図およびそのA−A’断面図である。図1(a),
(b)に示すように、本実施の形態の半導体装置用パッ
ケージは、中央に開口部2を形成し、下面より電気的接
続用の複数の外部端子3を導出させた電気的配線基板1
と、この電気的配線基板1の上面に固着するとともに電
気的配線基板1の開口部2の上面側を閉塞するように素
子搭載部6を形成した金属板4と、開口部2内に位置す
る金属板4の素子搭載部6に固定された半導体素子9
と、電気的配線基板1の上面で、しかも半導体素子9を
囲む位置に搭載した積層セラミックコンデンサ7とを有
し、電気的配線基板1の上面の金属板4を積層セラミッ
クコンデンサ7の外側にまで延在さている。特に、この
金属板4は、電気的配線基板1上に設けた積層セラミッ
クコンデンサ7の周囲に開口部5を形成し、電気的配線
基板1の上面のほとんどを覆うようにしている。なお、
積層セラミックコンデンサ7の両端に接続する電源端子
8aおよびグランド端子8bと、半導体素子9に接続す
る金属細線10および保護用の金属キャップ11とは、
前述した図3の従来例と同様である。FIGS. 1A and 1B are a top view and a sectional view taken along the line AA 'of a semiconductor device package, respectively, for explaining an embodiment of the present invention. FIG. 1 (a),
As shown in FIG. 1B, the semiconductor device package according to the present embodiment has an electric wiring board 1 in which an opening 2 is formed in the center and a plurality of external terminals 3 for electric connection are led out from the lower surface.
A metal plate 4 on which an element mounting portion 6 is formed so as to be fixed to the upper surface of the electric wiring substrate 1 and close the upper surface side of the opening 2 of the electric wiring substrate 1, and is located in the opening 2. Semiconductor element 9 fixed to element mounting portion 6 of metal plate 4
And a multilayer ceramic capacitor 7 mounted on the upper surface of the electric wiring substrate 1 and at a position surrounding the semiconductor element 9. The metal plate 4 on the upper surface of the electric wiring substrate 1 extends outside the multilayer ceramic capacitor 7. Extending. In particular, the metal plate 4 forms an opening 5 around the multilayer ceramic capacitor 7 provided on the electric wiring board 1 so as to cover almost the upper surface of the electric wiring board 1. In addition,
A power supply terminal 8a and a ground terminal 8b connected to both ends of the multilayer ceramic capacitor 7, and a thin metal wire 10 and a protective metal cap 11 connected to the semiconductor element 9,
This is the same as the conventional example of FIG.
【0013】本実施の形態においても、中央に開口部2
を形成した電気的配線基板1の開口部上面は金属板4で
閉塞されており、その開口部2内で金属板4に半導体素
子9が搭載されている。また、電気的配線基板1の開口
部下面は金属キャップ11などで半導体素子9を遮断
し、外部から保護している。Also in the present embodiment, the opening 2 is provided at the center.
The upper surface of the opening of the electric wiring board 1 in which is formed is closed by the metal plate 4, and the semiconductor element 9 is mounted on the metal plate 4 in the opening 2. Further, the lower surface of the opening of the electric wiring board 1 is shielded from the outside by blocking the semiconductor element 9 with a metal cap 11 or the like.
【0014】本実施の形態において従来例と異なるの
は、電気的配線基板1の開口部2の上面に固着された金
属板4が積層セラミックコンデンサ7の搭載を可能にす
るための開口部5を形成し、しかも金属板4のサイズに
左右されずに半導体素子9のより近傍に積層セラミック
コンデンサ7を搭載できる構造にしたことにある。さら
に、この金属板4は積層セラミックコンデンサ7の搭載
位置より外側の電気的配線基板1上をも覆うことによ
り、半導体素子9により発生する熱量の放熱効果を高め
ている。The present embodiment is different from the conventional example in that the metal plate 4 fixed to the upper surface of the opening 2 of the electric wiring board 1 forms the opening 5 for enabling the mounting of the multilayer ceramic capacitor 7. The structure is such that the multilayer ceramic capacitor 7 can be mounted closer to the semiconductor element 9 irrespective of the size of the metal plate 4. Further, the metal plate 4 also covers the electrical wiring board 1 outside the mounting position of the multilayer ceramic capacitor 7, thereby enhancing the heat radiation effect of the heat generated by the semiconductor element 9.
【0015】上述したように、本実施の形態による半導
体装置用パッケージは、半導体素子9の動作時の発熱を
効率よく外部に放熱することを目的として取り付けられ
た金属板4に積層セラミックコンデンサ7搭載用の開口
部5を形成するとともに、積層セラミックコンデンサ7
搭載部よりも外側の電気的配線基板1をも金属板4で固
着できる構造とすることにより、積層セラミックコンデ
ンサ7の搭載位置が半導体素子9の近傍であっても金属
板4の固着面積にほとんど影響を与えることがない。As described above, the package for a semiconductor device according to the present embodiment has the multilayer ceramic capacitor 7 mounted on the metal plate 4 attached for the purpose of efficiently radiating heat generated during operation of the semiconductor element 9 to the outside. Opening 5 is formed, and the multilayer ceramic capacitor 7 is formed.
By employing a structure in which the electric wiring board 1 outside the mounting portion can be fixed by the metal plate 4, even when the mounting position of the multilayer ceramic capacitor 7 is near the semiconductor element 9, the mounting area of the metal plate 4 is almost zero. Has no effect.
【0016】図2は本発明の他の実施の形態を説明する
ための半導体装置用パッケージの上面図である。図2に
示すように、本実施の形態による半導体装置用パッケー
ジは、前述した実施の形態と比べ、金属板4の形状を変
更したものである。すなわち、この金属板4は電気的配
線基板1上に設けた積層セラミックコンデンサ7の近傍
に凹部12を形成し、電気的配線基板1の上面の残りの
部分のほとんどを覆うようにしている。この場合も、中
央に開口部2を形成した電気的配線基板1の開口部上面
は金属板4で閉塞され、その開口部2内で金属板4に半
導体素子9が固着される。また、電気的配線基板1の開
口部下面は、金属キャップ等で外部から遮断するととも
に保護している。FIG. 2 is a top view of a semiconductor device package for explaining another embodiment of the present invention. As shown in FIG. 2, the semiconductor device package according to the present embodiment is different from the above-described embodiment in that the shape of the metal plate 4 is changed. That is, the metal plate 4 forms the recess 12 in the vicinity of the multilayer ceramic capacitor 7 provided on the electric wiring board 1 so as to cover most of the remaining portion of the upper surface of the electric wiring board 1. Also in this case, the upper surface of the opening of the electric wiring board 1 having the opening 2 formed in the center is closed by the metal plate 4, and the semiconductor element 9 is fixed to the metal plate 4 in the opening 2. The lower surface of the opening of the electric wiring board 1 is shielded and protected from the outside by a metal cap or the like.
【0017】要するに、本実施の形態における電気的配
線基板1の開口部上面に固着された金属板4は、凹部1
2を形成することにより、積層セラミックコンデンサ7
の搭載部を避け、積層セラミックコンデンサ7の搭載位
置より外側の電気的配線基板1の4つのコーナ部(隅
部)にまで延在する構造にしたことにある。In short, the metal plate 4 fixed to the upper surface of the opening of the electric wiring board 1 in this embodiment
2 to form a multilayer ceramic capacitor 7
The structure extends to the four corners (corners) of the electric wiring board 1 outside the mounting position of the multilayer ceramic capacitor 7 while avoiding the mounting portion of the multilayer ceramic capacitor 7.
【0018】[0018]
【発明の効果】以上説明したように、本発明の半導体装
置用パッケージは、開口部を形成した電気的配線基板に
搭載する金属板に対し、前記半導体素子の上面を覆うだ
けでなく、前記半導体素子の周囲に配置する積層セラミ
ックコンデンサの搭載部を避け且つ前記積層セラミック
コンデンサの搭載位置よりも外側の電気的配線基板上ま
で延在することにより、金属板のサイズに左右されず、
積層セラミックコンデンサを前記半導体素子の近傍に搭
載することができるので、素子に対する放熱特性を阻害
することなく、効率的にグランドバウンスノイズを低減
することができるという効果がある。As described above, the semiconductor device package of the present invention not only covers the upper surface of the semiconductor element but also covers the semiconductor plate with respect to the metal plate mounted on the electric wiring board having the opening. By avoiding the mounting portion of the multilayer ceramic capacitor arranged around the element and extending to the outside of the mounting position of the multilayer ceramic capacitor on the electric wiring board, regardless of the size of the metal plate,
Since the multilayer ceramic capacitor can be mounted in the vicinity of the semiconductor element, there is an effect that the ground bounce noise can be efficiently reduced without obstructing the heat radiation characteristics to the element.
【図1】本発明の一実施の形態を説明するための半導体
装置用パッケージの上面および断面を表わす図である。FIG. 1 is a diagram illustrating a top surface and a cross section of a semiconductor device package for describing an embodiment of the present invention;
【図2】本発明の他の実施の形態を説明するための半導
体装置用パッケージの上面図である。FIG. 2 is a top view of a semiconductor device package for explaining another embodiment of the present invention.
【図3】従来の一例を説明するための半導体装置用パッ
ケージの上面および断面を表わす図である。FIG. 3 is a diagram illustrating a top surface and a cross section of a semiconductor device package for explaining an example of the related art.
1 電気的配線基板 2 開口部 3 外部端子 4 金属板 5 開口部 6 素子搭載部 7 積層セラミックコンデンサ 8a 電源端子 8b グランド端子 9 半導体素子 10 金属細線 11 金属キャップ 12 凹部 DESCRIPTION OF SYMBOLS 1 Electrical wiring board 2 Opening 3 External terminal 4 Metal plate 5 Opening 6 Element mounting part 7 Multilayer ceramic capacitor 8a Power supply terminal 8b Ground terminal 9 Semiconductor element 10 Fine metal wire 11 Metal cap 12 Concave part
Claims (3)
的接続用の複数の外部端子を導出させた電気的配線基板
と、前記電気的配線基板の上面に固着するとともに前記
電気的配線基板の前記開口部の上面側を閉塞するように
素子搭載部を形成した金属板と、前記開口部内に位置す
る前記金属板の前記素子搭載部に固定された半導体素子
と、前記電気的配線基板の上面に且つ前記半導体素子を
囲む位置に搭載した積層セラミックコンデンサとを有
し、前記電気的配線基板の上面の前記金属板を前記積層
セラミックコンデンサの外側にまで延在させたことを特
徴とする半導体装置用パッケージ。An electric wiring board having an opening formed in the center and a plurality of external terminals for electrical connection leading out from a lower surface, and an electric wiring board fixed to an upper surface of the electric wiring board. A metal plate on which an element mounting portion is formed so as to close an upper surface side of the opening, a semiconductor element fixed to the element mounting portion of the metal plate located in the opening, and an electric wiring board. A multilayer ceramic capacitor mounted on the upper surface and at a position surrounding the semiconductor element, wherein the metal plate on the upper surface of the electrical wiring board extends to the outside of the multilayer ceramic capacitor. Equipment package.
設けた前記積層セラミックコンデンサの周囲に開口部を
形成し、前記電気的配線基板の上面のほとんどを覆うよ
うにした請求項1記載の半導体装置用パッケージ。2. The electric circuit board according to claim 1, wherein the metal plate has an opening formed around the multilayer ceramic capacitor provided on the electric wiring board, and covers most of the upper surface of the electric wiring board. Package for semiconductor devices.
設けた前記積層セラミックコンデンサの近傍に凹部を形
成し、前記電気的配線基板の上面の残りの部分のほとん
どを覆うようにした請求項1記載の半導体装置用パッケ
ージ。3. A method according to claim 1, wherein the metal plate has a recess formed near the multilayer ceramic capacitor provided on the electrical wiring board, and covers most of a remaining portion of the upper surface of the electrical wiring board. Item 2. A package for a semiconductor device according to Item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10524696A JP2793553B2 (en) | 1996-04-25 | 1996-04-25 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10524696A JP2793553B2 (en) | 1996-04-25 | 1996-04-25 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09293825A JPH09293825A (en) | 1997-11-11 |
| JP2793553B2 true JP2793553B2 (en) | 1998-09-03 |
Family
ID=14402300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10524696A Expired - Fee Related JP2793553B2 (en) | 1996-04-25 | 1996-04-25 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2793553B2 (en) |
-
1996
- 1996-04-25 JP JP10524696A patent/JP2793553B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09293825A (en) | 1997-11-11 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980602 |
|
| LAPS | Cancellation because of no payment of annual fees |