JP2796401B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor having a structure having a solder joint for hermetic sealing and a solder joint for heat radiation. The present invention relates to a technology that is effective when applied to an integrated circuit device.

[Conventional technology]

As an example of a sealing mode in response to a request for improvement of the mounting density of a semiconductor integrated circuit device, for example, a sealing structure as shown in FIG.

That is, a preform material made of solder E is sandwiched between the base C on which the semiconductor integrated circuit element B is mounted and the cap D and between the cap D and the semiconductor integrated circuit element B via the solder bump A, The base C and the cap D, and the semiconductor integrated circuit B
And the formation of a heat radiation bonding structure by the solder E between the metal and the cap D.

Then, the base C of the semiconductor integrated circuit device having such a sealing structure is further mounted on a desired mounting substrate or the like via a solder bump or the like (not shown), and a wiring structure and a solder bump A (not shown) formed inside the base C. Through which electric signals are exchanged between the semiconductor integrated circuit element B and the outside.

By the way, in the case of the sealing structure shown in FIG. 3 described above, from the viewpoint of reducing the thermal stress acting on the semiconductor integrated circuit element B and the solder bump A, etc., in the height direction of the entire sealing structure. The balance of thermal expansion becomes important,
In accordance with the diameter of the semiconductor integrated circuit element B and the solder bump A determined by the type, measures are taken such as appropriately setting the thickness of the solder E at the sealing portion between the pace C and the cap D.

On the other hand, when the thickness of the solder E at the sealing portion between the base C and the cap D is large, the airtightness of the sealing portion is impaired due to shrinkage holes generated in the width direction at the time of solidification. As a countermeasure, it is conceivable to reduce the thickness of the solder E at the sealing portion to prevent the occurrence of shrinkage holes.

[Problems to be solved by the invention]

For this reason, if the same solder E is used for the heat radiation bonding structure and the sealing portion, and the thickness of the solder E in the sealing portion is simply reduced as a measure against the decrease in the airtightness of the sealing portion, the thickness is increased. In the cooling process at the time of solder reflow, the solder of the sealing portion and the heat radiation bonding structure portion are simultaneously cured in a state where the balance of thermal expansion in the directions is lost, and the semiconductor integrated circuit element B is placed between the cap D and the base C. Is strongly restrained.

Therefore, due to the difference in the coefficient of thermal expansion between the cap D and the semiconductor integrated circuit element B, for example, as shown in FIG. 3, a tensile thermal stress is applied to the solder bump A located at the peripheral portion of the semiconductor integrated circuit element B. Occurs, the solder bump A peels off from the semiconductor integrated circuit element B, and the electrical connection between the semiconductor integrated circuit element B and the outside becomes unstable, and the reliability of the operation of the semiconductor integrated circuit device increases. Is reduced.

As a countermeasure against thermal stress in a similar sealing structure, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 60-34813.

That is, at the time of solder reflow, the chip is lifted from the substrate by the surface tension of the solder layer on the back surface of the chip, and the melting shape of the connection bumps electrically connected to the substrate and the chip is controlled in a columnar shape. It is intended to reduce the stress concentration at the joint interface between the connection bump and the substrate, which is generated at the time of shape, and to improve the thermal fatigue characteristic of the joint. There is no mention of measures to reduce airtightness in the department.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit device in which thermal stress acting on solder bumps interposed between a base and a semiconductor integrated circuit element is reduced to improve operation reliability.

Another object of the present invention is to provide a semiconductor integrated circuit device capable of achieving both improvement of airtightness in a sealing portion and reduction of thermal stress acting on solder bumps interposed between a base and a semiconductor integrated circuit element. Is to provide.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application is briefly described as follows.

That is, the semiconductor integrated circuit device according to the present invention seals the semiconductor integrated circuit device by sealing the cap via the first solder to the base on which the semiconductor integrated circuit device is mounted via the solder bumps, A semiconductor integrated circuit device in which a back surface of a semiconductor integrated circuit element and a cap are connected by a second solder, wherein a melting point of the second solder is lower than a melting point of the first solder.

[Action]

According to the semiconductor integrated circuit device of the present invention described above, for example, in the cooling process in the solder reflow at the time of sealing, the first solder having a higher melting point interposed in the sealing portion between the base and the cap is formed by the semiconductor integrated circuit. Since the solidification is performed before the second solder having a lower melting point interposed between the element and the cap, the semiconductor integrated circuit element and the solder bumps are not strongly restrained between the base and the cap. When the first solder is solidified, the second solder still in a molten or semi-molten state absorbs thermal deformation and the like of the cap and the semiconductor integrated circuit element.

In addition, since the melting point of the second solder is lower and closer to room temperature, the thermal stress generated by solidification of the second solder is smaller.

Therefore, the thermal stress acting on the semiconductor integrated circuit element and the solder bump due to the difference in the coefficient of thermal expansion between the cap and the semiconductor integrated circuit element and the like is alleviated. The occurrence of peeling of the semiconductor integrated circuit device is reliably avoided, the electrical connection between the semiconductor integrated circuit element and the outside via the solder bumps is stabilized, and the reliability of the operation of the semiconductor integrated circuit device is improved.

Also, without concern about the occurrence of thermal stress in the semiconductor integrated circuit element and the solder bumps, for example, the thickness of the first solder interposed at the sealing portion between the base and the cap can be reduced to reduce the airtightness of the sealing portion. Thus, it is possible to achieve both improvement in airtightness in the sealing portion and reduction in thermal stress acting on solder bumps interposed between the base and the semiconductor integrated circuit element.

〔Example〕

Hereinafter, an example of a semiconductor integrated circuit device according to an embodiment of the present invention will be described in detail with reference to the drawings.

1 and 2 show an example of a configuration in an assembling process of the semiconductor integrated circuit device of the present embodiment in the order of processes.

First, the configuration of the semiconductor integrated circuit device according to the present embodiment will be described.

For example, a semiconductor integrated circuit structure having a desired function is formed on a base 1 made of ceramics or the like via a plurality of solder bumps 2 having a composition of, for example, Pb-3.6% by weight Sn (melting point: 310 to 320 ° C.). The integrated circuit element 3 is mounted.

Although not particularly shown, a wiring structure is formed inside the base 1 and on both the front and back sides, and via the wiring structure and the solder bumps 2, an operation signal and drive power between the semiconductor integrated circuit element 3 and the outside are formed. It is configured to exchange information.

A cap 5 having a concave cross section is provided on a base 1 on which the semiconductor integrated circuit element 3 is mounted via a solder layer 4 (first solder) formed by a solder reflow operation as described later.
Is sealed, so that the semiconductor integrated circuit element 3 is sealed in a sealed space formed by the base 1 and the cap 5.

In the case of the present embodiment, for example, the solder layer 4 has a composition of Pb
A solder of -10% by weight Sn (melting point: 275 to 300 ° C.) is used.

Further, although not particularly limited, a desired metallized layer may be formed in the sealing portion between the base 1 and the cap 5 for the purpose of improving the wettability with respect to the solder layer 4 if necessary. .

In this case, the back surface of the semiconductor integrated circuit element 3 and the cap 5
For example, the composition is In-48% by weight of Sn
A solder layer 6 (second solder) having a melting point lower than that of the solder layer 4 and having a temperature closer to room temperature (second solder) is formed so as to be filled as described later. The heat generated during the operation of the circuit element 3 is radiated to the outside via the solder layer 6 and the cap 5.

An example of the solder reflow process in assembling the semiconductor integrated circuit device having such a structure will be described below.

First, a semiconductor integrated circuit element 3 is mounted on a base 1 via a plurality of solder bumps 2.

Next, as shown in FIG. 1, between the base 1 on which the semiconductor integrated circuit element 3 is mounted and the cap 5, a solder preform material 4a for forming a solder layer 4 is sandwiched. The solder preform material 6a constituting the solder layer 6 is stacked between the back surface of the cap 3 and the cap 5.

Then, while being squeezed with a desired load by a desired jig (not shown) or the like, it is charged into a heating furnace (not shown) and heated to a temperature about the melting point of the solder preform material 4a (solder layer 4). The solder preform material 4a and the solder preform material 6a having a low melting point are brought into a molten state, whereby the sealing portion between the base 1 and the cap 5 and the back surface of the semiconductor integrated circuit device 3 and the cap 5 are formed. As shown in FIG. 2, the molten solder layer 4 and the solder layer 6 are filled between the inner wall surface and the inner wall surface.

Thereafter, the solder layer is taken out of the heating furnace and cooled, and the solder layer 4 and the solder layer 6 are solidified.

At the time of this cooling, in the case of the semiconductor integrated circuit device of the present embodiment, the melting point of the solder layer 4 interposed in the sealing portion between the base 1 and the cap 5 changes the melting point of the back surface of the semiconductor integrated circuit element 3 and the cap Therefore, even when the solder layer 4 of the sealing portion is completely solidified, the solder layer 6 is still in a molten state or a semi-molten state.

That is, as in the conventional case, when the solder layers 4 and 6 are made of solder having the same composition and both solidify simultaneously during the cooling process, the internal semiconductor integrated circuit element 3 and the solder bumps 2 1 and the cap 5 are strongly restrained. For example, due to a difference in the coefficient of thermal expansion between the cap 5 and the semiconductor integrated circuit element 3, for example, a tensile heat is applied between the semiconductor integrated circuit element 3 and the solder bump 2. Stress will act.

However, in the case of this embodiment, since one of the solder layers 6 is in a molten or semi-molten state, thermal deformation of the cap 5 or the semiconductor integrated circuit element 3 is absorbed by the solder layer 6 in the molten or semi-molten state. This prevents harmful thermal stress from acting between the semiconductor integrated circuit element 3 and the plurality of solder bumps 2.

Further, since the melting point of the solder layer 6 is low and close to room temperature, the temperature difference in cooling from the solidification of the solder layer 6 to room temperature is small, so that the thermal stress caused by this temperature difference is further reduced.

As a result, in the heating / cooling process such as solder reflow, the semiconductor integrated circuit element 3 and the solder bump 2 are separated due to thermal stress or the like, and the electrical connection between them becomes unstable. Is avoided, and the reliability of the operation of the semiconductor integrated circuit device is reliably improved.

Also, without worrying about the occurrence of such thermal stress,
By making the thickness of the solder layer 4 sufficiently small, it is possible to prevent a decrease in the hermeticity of the sealing portion due to the occurrence of shrinkage holes, etc., thereby reducing thermal stress and improving hermeticity in the semiconductor integrated circuit device. Can be compatible.

In addition, substances with low melting points generally have low rigidity,
The thermal stress acting between the solder bump 2 and the base 1 due to a thermal cycle during use of the semiconductor integrated circuit device after sealing is also reduced, and the fatigue life at the joint between the solder bump 2 and the base 1 is reduced. As a result of being extended,
The reliability of the operation of the semiconductor integrated circuit device is improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor.

For example, the composition of the first and second solders is as follows:
The combination is not limited to those exemplified in the above embodiment, and may be a combination of other substances as long as the melting point of the second solder is lower than the melting point of the first solder.

Further, the structure of the semiconductor integrated circuit device is not limited to the above embodiment.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, according to the semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit device is sealed by sealing the cap via the first solder to the base on which the semiconductor integrated circuit device is mounted via the solder bumps. ,
A second space is provided between the back surface of the semiconductor integrated circuit device and the cap.
A semiconductor integrated circuit device connected by solder of
Since the melting point of the second solder is lower than the melting point of the first solder, for example, in the cooling process in the solder reflow at the time of sealing, the second solder having a higher melting point interposed in the sealing portion between the base and the cap is used. Since the first solder solidifies before the second solder having a lower melting point interposed between the semiconductor integrated circuit device and the cap, the semiconductor integrated circuit device and the solder bumps are strongly solidified between the base and the cap. When the first solder is solidified without being restrained, the second solder still in a molten or semi-molten state absorbs thermal deformation of the cap and the semiconductor integrated circuit element.

In addition, since the melting point of the second solder is lower and closer to room temperature, the thermal stress generated by solidification of the second solder is smaller.

Therefore, the thermal stress acting on the semiconductor integrated circuit element and the solder bump due to the difference in the coefficient of thermal expansion between the cap and the semiconductor integrated circuit element and the like is alleviated. The occurrence of peeling of the semiconductor integrated circuit device is reliably avoided, the electrical connection between the semiconductor integrated circuit element and the outside via the solder bumps is stabilized, and the reliability of the operation of the semiconductor integrated circuit device is improved.

Further, the thickness of the first solder interposed in the sealing portion between the base and the cap is reduced without concern about the occurrence of thermal stress in the semiconductor integrated circuit element and the solder bumps, and the airtightness of the sealing portion is reduced. Thus, it is possible to achieve both improvement in airtightness in the sealing portion and reduction in thermal stress acting on solder bumps interposed between the base and the semiconductor integrated circuit element.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor integrated circuit device in an assembled state before solder reflow, FIG. 2 is a cross-sectional view showing an example of a semiconductor integrated circuit device after solder reflow, and FIG. 1 is a schematic sectional view showing an example of the configuration of a semiconductor integrated circuit device of FIG. DESCRIPTION OF SYMBOLS 1 ... Base, 2 ... Solder bump, 3 ... Semiconductor integrated circuit element, 4 ... Solder layer (1st solder), 4a ... Solder preform material (1st solder), 5 ... Cap, 6 ... Solder layer (second solder), 6a... Solder preform material (second solder).

Claims (2)

(57) [Claims] 1. A semiconductor device having a semiconductor integrated circuit device mounted thereon via a first solder, wherein the cap is sealed to a base on which the semiconductor integrated circuit device is mounted via solder bumps. And a cap connected by a second solder, wherein the melting point of the second solder is lower than the melting point of the first solder. 2. A first and second solder preform material comprising said first and second solders, respectively, between said base and said cap and between said semiconductor integrated circuit device and said cap. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is assembled by heating and cooling the first solder to a temperature of about the melting point of the first solder.