JP2798485B2 - Writable nonvolatile memory - Google Patents

Description

The present invention relates to a writable nonvolatile memory (hereinafter, referred to as a PROM), and more particularly to an improvement in a data writing speed thereof.

[Prior Art] A conventional circuit for writing data in a PROM is as shown in FIG. The data input from the data terminal 201 is sent to the data holding circuit 205 through a selector circuit 204 for selecting where to write the data in the data holding circuit 205 by the following signal 203 on the address bus 202. The transmitted data is held in the data holding circuit 205 in synchronization with the data input request signal 207 from the data input request terminal 206.
Such an operation is repeatedly performed, and the data holding circuit 205
When all the data has been written into the memory cell 210, the write circuit 211 simultaneously writes all the data in the data holding circuit 205 into the memory cell 210 in response to the memory cell write request signal 209 from the memory cell write terminal 208.

FIG. 4 is a timing chart of the operation. In the conventional write operation, the data input period 240 operates at a very high speed, whereas the data input period 240
Requires a much longer time than the data input period 240 due to the characteristics of the PROM.

[Problem to be Solved by the Invention] The above-described conventional writing circuit is different from a system in which writing is performed for each set of inputs from the previous data bus.
By temporarily holding a plurality of data in the data holding circuit and writing these data at the same time, in the case of a memory having the same capacity, the number of times of the data writing period 241 in FIG. The result is a fraction.
Further, since the data input period 240 can be almost ignored, the total writing time can be greatly reduced as a result.

However, as the capacity of the PROM further increases, the amount of data to be input in one data input period 240 must be increased, and the data input period 240 cannot be ignored.

[Differences of the Invention from the Prior Art] The present invention employs a second writing circuit between the data holding circuit 205 and the memory cell 210 without changing the input terminals of the writing circuit at all.
Is different in that the data input period 240 and the data write period 241 can be simultaneously executed in parallel.

[Means for Solving the Problems] A writable nonvolatile memory according to the present invention includes a memory cell composed of a nonvolatile memory and a first data line for sequentially holding a write data string of the memory cell in synchronization with a data input request signal.
And a second data holding circuit to which a data string is inputted when the write request signal to the memory cell is inactive, and the data string of the second data holding circuit is changed when the write request signal is activated. This is to simultaneously write data into the memory cells and sequentially hold the next data string in the first data holding circuit.

Embodiment Next, an embodiment of the present invention will be described with reference to FIG. 1 and FIG.

The same parts as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals, and duplicate description will be omitted. The difference between this embodiment and the conventional example is that the second data holding circuit 100
And a memory cell write request signal 209 is input as a hold request signal.
And the same capacity. In the present embodiment, the second data holding circuit 100 holds data from the data holding circuit 205 when the write request signal 209 is in the requested state, and the held data appears on its output. On the other hand, when the state is not the request state, the data from the data holding circuit 205 does not hold and appears on the output as it is. That is, during the period when the write request signal 209 is in the request state, the second
The data held in the data holding circuit 100 is unchanged, and during the period when the write request signal 209 is not in the request state, the data appearing at the output of the second data holding circuit 100 becomes the output data of the data holding circuit 205. It can be changed.

The operation of this embodiment will be described by dividing into a first writing period 301 and a next writing period 302 in FIG. First, in the first write period 301, data input from the data input terminal 201 in FIG. 1 is sent through the selector circuit 204 for selecting where to write in the data holding circuit 205 by the lower signal 203 of the address bus 202. The transmitted data is held in the data holding circuit 205 in synchronization with the data input request signal 207 from the data input request signal 206. In this first write period, the memory cell write terminal 208
Since the memory cell write request signal 209 is not in the request state, the data of the data holding circuit 205 is directly input to the second data holding circuit 100 and appears at its output. When the writing of a series of data is completed, all the data is held in the data holding circuit 205, and the same data appearing at the output thereof also appears at the output of the second data holding circuit 100.
After that, when the memory cell write request signal 209 is changed from the memory cell write terminal 208 to the request state, the data in the second data holding circuit 100 is held and written to the memory cell 210 as it is. The time of the first writing period 301 needs to be the same as that of the conventional technique.

Next, the next data writing period 302 will be described. This period can be started during the data writing period 241 of the first writing period 301. The memory cell write request signal 209 for the first data remains in the request state and the data input request signal
07 is input to the data holding circuit 205, and even if the next data is held, the operation of writing the first data to the memory cell 210 is guaranteed by the second data holding circuit 100. Next, when the input of all the next data is completed, the data writing period 241 of the next data can be started immediately after waiting for the writing period of the first data to be completed. In this manner, the subsequent operations can also proceed simultaneously without waiting for the completion of the immediately preceding period.

[Effects of the Invention] As described above, in the present invention, since the second data holding circuit is provided between the memory cell and the data holding circuit, writing of data to the memory cell and input of the next data are performed in parallel. This has the effect of substantially reducing the PROM write time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PROM according to one embodiment of the present invention, FIG. 2 is a timing chart for explaining its operation,
FIG. 3 is a block diagram showing a conventional PROM, and FIG. 4 is a timing chart for explaining its operation. 100: second data holding circuit 201: data terminal 202: address bus 203: lower signal of address bus 204: selector circuit 205: data holding circuit 206: data input request 207: Data input request signal (request state at high level), 208: Memory cell write terminal, 209: Memory cell write request signal, 210: Memory cell, 211: Write circuit, 240: Data Input period, 241: Data writing period, 301: First writing period, 302: Next writing period.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 16/00

Claims (1)

(57) [Claims] 1. A memory cell comprising a nonvolatile memory, a first data holding circuit for sequentially holding a write data string of the memory cell in synchronization with a data input request signal, and a write request signal to the memory cell is provided. A second data holding circuit to which the data string is input when inactive, and simultaneously writing the data string of the second data holding circuit to the memory cells when the write request signal is active;
A writable non-volatile memory, wherein the first data holding circuit sequentially holds a next data string.