JP2798933B2 - Recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a recording apparatus for recording information on a recording sheet by energizing and heating, for example, in a digital copying machine or a facsimile.

(Prior art) In general, a digital copying machine or a facsimile
It comprises an image reading device or image data receiving device as image information input means, and an image recording device as image information recording means input from the image information input means. As such an image recording apparatus, an apparatus employing a thermal recording method or a thermal transfer recording method is used.

An image reading apparatus such as a digital copying machine or a facsimile reads an image of a document using a charge accumulation type image sensor (hereinafter, referred to as a “CCD sensor”) or a thin film deposition type image sensor for each scanning line. The read image is converted into binary or multi-valued image data, and this is sent to an image recording device to perform image recording.

Such an image recording apparatus has a recording head configured by arranging a number of heating elements corresponding to the number of images to be recorded in a line. Then, the image data for one scanning line is supplied to the recording head and energization is performed in accordance with the pixels, so that the heating elements are selectively heated, thereby performing recording.

However, since the recording head of the image recording apparatus as described above has a limitation on the current to be applied simultaneously, the heating elements arranged in a row are divided into a plurality of groups (groups), and the plurality of groups are sequentially driven ( The instantaneous maximum current consumption is suppressed by performing a time difference drive. Since the plurality of groups are sequentially driven, it takes a long time to print one line, and high-speed printing cannot be performed.

(Problems to be Solved by the Invention) According to the present invention, the heating elements arranged in a line are divided into a plurality of groups, and the maximum current consumption at the moment is suppressed by performing time difference driving. An object of the present invention is to provide a printing apparatus capable of performing high-speed printing in accordance with the pixel density, in order to solve the disadvantage that it takes time to print one line and cannot perform high-speed printing.

[Structure of the Invention] (Means for Solving the Problems) The recording apparatus of the present invention is composed of a plurality of heating elements arranged in a line, and the plurality of heating elements are divided into a plurality of groups to be group-by-group. A recording head for recording print data on a recording medium, output means for outputting a transfer start signal for print data to be recorded by the recording head, and transfer of the print data in accordance with a transfer start signal output from the output means A clock counter that counts a clock signal up to a count value corresponding to the number of heating elements constituting the group and outputs a carry signal; and a black pixel data of the transferred print data based on the number of heating elements constituting the group. A first counter that counts up to the number of heating elements that can be driven simultaneously and outputs a carry signal; and a black pixel of the transferred print data. A second counter for counting the number of heating elements larger than the number of heating elements forming the group and simultaneously driving the number of heating elements and outputting a carry signal; a transfer start signal output from the output means; Control means for selectively starting the first counter and the second counter in response to a carry signal from a clock counter; a carry signal output from the clock counter; Generating means for generating a signal indicating a group that can be simultaneously driven in response to the carry signals output from the first and second counters whose start is controlled, and in accordance with the signal generated by the generating means Drive control means for controlling the drive of the recording heads in groups.

(Function) The present invention outputs a print data transfer start signal for transferring a plurality of heating elements arranged in one line to a printhead which divides the print elements into a plurality of groups and records print data on a print medium in group units. In response to the output transfer start signal, a clock signal for transferring the print data is counted up to a count value corresponding to the number of heating elements constituting the group, and a carry signal is output. The black pixel data is counted by the first counter to the number of heating elements constituting the group and the number of heating elements that can be simultaneously driven, a carry signal is output, and the black pixel data of the transferred print data is output. The second counter counts up to the number of heating elements that can be driven simultaneously, which is larger than the number of heating elements forming the group, and outputs a carry signal.
In response to the output transfer start signal and the carry signal from the clock counter, the first counter and the second counter are selectively started to count, and the carry signal output from the clock counter and Generating a signal indicating a group that can be simultaneously driven in response to the carry signal output from the first and second counters whose count start is controlled, and controlling the recording head in accordance with the generated signal. Drive control is performed on a group basis.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an electric circuit of a recording apparatus according to the present invention. In the figure, a timing clock generation circuit 10 generates a timing signal that defines the operation of each unit of the device. The CCD drive circuit 11 drives the CCD sensor 12 in synchronization with the clock signal from the timing clock generation circuit 10. In addition, the CCD drive circuit 11 outputs the light irradiation time of the CCD sensor 12,
Optical signal accumulation time signal SH that defines the scanning time of the scanning line
Is output.

The CCD sensor 12 converts reflected light (not shown) from a document irradiated with light from a light source into a charge amount corresponding to the light amount, and outputs the charge amount as an analog voltage. This CC
The output voltage of the D sensor 12 reflects the read image, and is supplied to the image processing circuit 13 as an image signal Sa.

The image processing circuit 13 includes a low-frequency distortion caused by the use of the reduction optical system, which is included in the image signal Sa output from the CCD sensor 12, and
After performing correction of high-frequency distortion or the like inherent in the CCD sensor 12, so-called shading correction, the signal is converted into a binary signal. The binarized image signal VDATA output from the image processing circuit 13 is supplied to the thermal head 14 and the division determination circuit 1.
5 is output.

The thermal head 14 is a recording head including a total of 1728 heating elements, and is divided into four groups (groups) G1 to G4 each including 432 heating elements. These four groups G1 to G4 are individually energized and driven by enable signals ENA1 to ENA4 from the PTC 23 described later. The thermal head 14 operates in synchronization with the clock signal CK from the timing clock generator 10.
Of the image signal VDATA binarized by the image processing circuit 13, a portion corresponding to the heating element group to which the enable signals ENA1 to ENA4 are supplied is driven to be energized, and the heat is generated to record an image on a recording sheet. It has become. The maximum number of elements allowed for simultaneous energization of the thermal head 14 is 44
It is assumed that the number is limited to eight.

The division determination circuit 15 is a timing clock generation circuit
Clock signal CK from 10 and start signal STA from CPU24
The drive is controlled by RT, and based on the distribution of black pixel data in one scanning line, it is determined whether the groups G1 to G4 constituting the thermal head 14 are to be energized simultaneously or staggered energized. This is to generate division determination data Ln for instructing a combination of groups in the case of energization drive or time difference energization drive. Details of the division determination circuit 15 will be described later.

The first pulse motor 16 is a drive motor for moving a document in the sub-scanning direction in order to perform scanning by the CCD sensor 12. The second pulse motor 17 is a thermal head
A drive motor for transporting the recording paper to be recorded by 14. The motor driver 18 is a drive circuit for controlling the drive power of the first pulse motor 16 and the second pulse motor 17.

The rechargeable battery voltage detection circuit 19 detects the voltage of a rechargeable secondary battery that is a main power supply of the present apparatus. The thermal head thermistor temperature detection circuit 20 detects the temperature of the thermal head 14 using a thermistor built in the thermal head 14. The sub-scanning pixel density detecting circuit 21 detects the pixel density of the document in the sub-scanning direction. Details of these will be described later.

The PIO 22 is a parallel I / O controlled by a CPU (Central Processing Unit) 24, and includes detection signals of a rechargeable battery voltage detection circuit 19, a thermal head thermistor temperature detection circuit 20, and a sub-scanning pixel density detection circuit 21. Input port, an input port for inputting division determination data Ln from the division determination circuit 15, an output port for outputting a gate signal for controlling an enable signal to the thermal head 14, a first pulse motor 16 and a second An output port for outputting a control signal Sb to a motor driver 18 for driving the pulse motor 17 is provided. The control signal Sb comprises control commands such as forward rotation, reverse rotation, stop, and speed control of the first pulse motor 16 and the second pulse motor 17.

The AND circuit 25 is connected to the thermal head 14 output from the PIO 22.
Are controlled in accordance with the optical signal accumulation time SH, and the output signals GATE1 to GATE4 are supplied to the PTC 23. Further, the above-mentioned optical signal accumulation time SH is equal to CP
The signal is supplied to the interrupt terminal INT of U24.

PTC23 is a programmable timer counter controlled by the CPU 24, and the output signal GATE1 of the AND circuit 25 is provided.
To GATE4, and generates and sends out enable signals ENA1 to ENA4 having predetermined pulse widths for driving the groups G1 to G4 of the thermal head 14 based on these signals.

FIG. 2 shows the configuration of the division determination circuit 15 in detail. In the figure, a print data transfer clock counter 30 counts a clock signal CK generated by the timing clock generation circuit 10, and starts counting by a start signal START output from the CPU 24, and counts 432 clock signals CK. Then, the carry pulse S1 is output to return to the initial state, and the same counting operation is continuously repeated. That is, when the number corresponding to the number of 432 heating elements constituting each group of the thermal head 14 is counted, the carry pulse S1 indicating that fact is output.

The black pixel data first counter 32 counts the number of black pixel data included in the image signal VDATA binarized by the image processing circuit 13 at the timing of the clock signal CK. This black pixel data first counter 32 has three inputs.
The counting is started by the output signal of the AND circuit 31, and when 448 black pixel data are counted, the carry pulse S2 is output and the counting is stopped. That is, the thermal head 14
When the maximum simultaneous energization allowable element number 448 is counted, a carry pulse S2 indicating this is output. the above
To the AND circuit 31, a START signal output from the CPU 24, an output signal S11 of a NAND circuit 39 described later, and an output signal S14 of the NAND circuit 42 are input. Is driven, a significant signal is output and the counting of the first black pixel data counter 32 is started.

The second counter 34 calculates the number of black image data included in the image signal VDATA binarized in the image processing circuit 13 by the timing of the clock signal CK in the same manner as the first counter 32 of the black pixel data. , But the conditions for starting the counting are different. That is, the black pixel data second counter 34 starts counting based on the output signal of the 2-input AND circuit 33, and outputs a carry pulse S3 when 448 black pixel data are counted, and stops counting. Things. That is, as described above, the thermal head
When 14 maximum simultaneous energization allowable elements 448 are counted, a carry pulse S3 indicating this is output. The AND circuit 33 includes an output signal S12 of a NAND circuit 40 described later,
And the output signal S13 of the NAND circuit 41 is input. When any one of the signals is driven, a significant signal is output and the counting of the black pixel data second counter 34 is started. ing.

The flip-flop circuit 35 outputs the output signal S16 of the AND circuit 48.
Is reset to the initial state, and is set when the carry pulse S2 output from the first black pixel data counter 32 is output. In the above reset state,
The non-inverted output signal S7 is at a low level (hereinafter, referred to as "L level"), the inverted output signal S8 is at a high level (hereinafter, referred to as "H level"), and the carry pulse S2 is supplied. At this time, the non-inverted output signal S7 changes to H level, and the inverted output signal S8 changes to L level.

The flip-flop circuit 36 outputs the output signal S17 of the AND circuit 49.
Is reset to the initial state, and is set when the carry pulse S3 output from the black pixel data second counter 34 is output. In the above reset state,
The non-inverted output signal S9 is at L level and the inverted output signal S10 is at H level. When the carry pulse S3 is supplied, the non-inverted output signal S9 is at H level and the inverted output signal S10 is
Changes to the L level.

The OR circuit 37 receives the non-inverted output signals S7 and S9 of the flip-flop circuits 35 and 36, and performs a logical OR operation on the output. The output signal S4 of the OR circuit 37 is supplied to the shift register 38.

The shift register 38 has, for example, a 4-bit shift capacity, and outputs its parallel output (division determination data).
When Ln is described and each bit is described as “L1, L2, L3, L4”, in the shift operation, the shift-in data is input to “L1” and the data of “L4” is shifted out Things. That is, the shift register 38 performs a shift operation using the output signal S4 of the OR circuit 37 as shift-in data and the carry pulse S1 of the print data transfer clock counter 30 as a shift pulse. In addition,
The data shifted out of the bit “L4” is lost.

That is, the shift register 38
The shift operation is performed by using the output signal S4 of the OR circuit 37 as shift-in data when the clock signal CK corresponding to the number 432 of the heating elements 432 in one group is counted and stored. The parallel output of the shift register 38 is supplied to the PIO 22 as division determination data Ln. Then, it is read into the CPU 24 every cycle of the optical signal accumulation time SH of the CCD sensor 12, and the distribution of black pixel data for each main scanning line is recognized.

The NAND circuit 39 receives the non-inverted output signal S7 of the flip-flop circuit 35 and the output signal S5 of the AND circuit 46, and supplies the output signal S11 to the three-input AND circuit 31 and the AND circuits 43 and 48. It has become. Also, NAND circuit 40
Inputs the inverted output signal S8 of the flip-flop circuit 35 and the output signal S5 of the AND circuit 46, and supplies the output signal S12 to the AND circuit 33 and the AND circuit 48.

The NAND circuit 41 receives the non-inverted output signal S9 of the flip-flop circuit 36 and the output signal S6 of the AND circuit 47, and outputs the output signal S13 to the AND circuit 33 and the AND circuits 43 and 4.
9 to supply. Also, the NAND circuit 42
Inverted output signal S10 of flip-flop circuit 36 and AND circuit 47
And the output signal S14 of the above-mentioned 3
The signals are supplied to the input AND circuits 31 and 49.

The AND circuit 43 receives the output signal S11 of the NAND circuit 39 and the output signal S13 of the NAND circuit 41, performs an OR operation at the I level, and outputs the output signal S15 to the flip-flop circuits 44 and 45. Is to be supplied to The AND circuit 48 is connected to the output signal S11 of the NAND circuit 39 and the NAND circuit 4
An output signal S12 of 0 is input, an OR operation is performed at the L level, the output signal S16 is supplied to a reset terminal of the flip-flop circuit 35, and the flip-flop circuit 35 is returned to a reset state. Further, the AND circuit 49 receives the output signal S13 of the NAND circuit 41 and the output signal S14 of the NAND circuit 42, performs an OR operation on the L level, and resets the output signal S17 of the flip-flop circuit 36. This is supplied to the terminal to return the flip-flop circuit 36 to a reset state.

The flip-flop circuit 44 performs a toggle operation based on the output signal S15 of the AND circuit 43, and the output signal is supplied to the AND circuit 46. The flip-flop circuit 44 is set to an H level as an initial state. Similarly, the flip-flop circuit 45 performs a toggle operation according to the output signal S15 of the AND circuit 43, and the output signal is supplied to the AND circuit 47. This flip-flop circuit 45
Is set to L level as an initial state. Therefore, the flip-flops 44 and 45 always output signals of opposite level.

The AND circuit 46 is provided with the carry pulse S1 of the print data transfer clock counter 30 and the flip-flop circuit.
The output signal of S44 is input to generate an output signal S5 obtained by AND operation. This signal S5 is supplied to the NAND circuits 39 and 40. Also, AND circuit 4
Numeral 7 is for inputting the carry pulse S1 of the print data transfer clock counter 30 and the output signal of the flip-flop circuit 45, and generating an output signal S6 obtained by taking a logical product. This signal S6 is supplied to the NAND circuits 41 and 42.

 Next, the operation in the above configuration will be described.

First, when reading scanning of a document is started in an image reading device (not shown), reflected light from the light-irradiated document is formed on the CCD sensor 12 by an optical system (not shown). In such a state, the CCD sensor 12 outputs the amount of charge accumulated according to the amount of reflected light as an analog voltage. This analog voltage is, as shown in FIG.
The data is converted into time-series data by a control signal from the CCD drive circuit 11 that operates in synchronization with the timing signal supplied from the timing generation circuit 10, and is supplied to the image processing circuit 13 as an image signal Sa.

The image processing circuit 13 converts the received image signal Sa into binary data of white pixels and black pixels by performing image correction such as shading correction and then slicing the image signal Sa at a predetermined slice level voltage. The binarized image signal VDATA is supplied to the division determination circuit 15 and the thermal head 14 in synchronization with the clock signal CK supplied from the timing clock generation circuit 10.

Next, the division determination circuit 1 to which the image signal VDATA is supplied.
The operation of No. 5 will be described with reference to the timing charts of FIGS. FIG. 3 is a timing chart showing an operation when the CCD sensor 12 reads all black data, and FIG. 4 is a timing chart showing an operation when the black data is concentrated at the center of the document. is there.

First, the operation when reading all the black data shown in FIG. 3 will be described. As shown in FIG. 3A, a START signal is output from the CPU 24 and supplied to the print data transfer clock counter 30, so that the print data transfer clock counter 30 receives the clock signal CK (see FIG. 3B). ) To start counting the number of pulses. At the same time, START
When the signal is supplied to the first black pixel data counter 32 via the three-input AND circuit 31, the first black pixel data counter 32 outputs the image signal VDATA (the first image signal VDATA) supplied in synchronization with the clock signal CK. The counting of black pixel data in FIG. 3 (c) is started. By the way, in the example shown in FIG. 3, the input image signal VDATA is all black pixel data (shown by oblique lines).
The same count as 30 will be performed. FIG. 3 (e) shows a time zone during which the first counter 32 of the black pixel data is performing the counting operation by an H level signal.

As described above, when the 432 clock signals CK are counted, the print data transfer clock counter 30 outputs a carry pulse S1 and sets the count value to an initial value, as shown in FIG. Then, the same counting operation as above is started again. That is, the operation of generating a pulse is repeated each time 432 clock signals CK are counted. Since the number of pixels in one scan line is 1,728, the print data transfer clock counter 30 generates four pulses while transferring the image signal VDATA in one scan line.

Here, the operation at the point A in FIG. 3, that is, when the first carry pulse S1 is generated will be described. As described above, the printed transfer clock counter 30 outputs the clock signal.
The carry pulse S1 is output by counting 432 CKs. At this time, the carry pulse S2 from the black pixel data first counter 32 and the carry pulse S3 from the black pixel data second counter 34 are either Has not yet been output, and both flip-flop circuits 35 and 36 are in the reset state. Therefore, the non-inverted output signals S7 and S9 of the flip-flop circuits 35 and 36 are both at the L level, and the output signal S4 of the OR circuit 37 is also at the L level. Therefore, the shift register 38 performs a 1-bit shift operation using the L-level output signal S4 from the OR circuit 37 as shift-in data and the carry pulse S1 as a shift clock. Data Ln
And outputs 4-bit data of “Ln = L, *, *, *”. Here, the symbol “*” indicates that an indefinite value is output.

On the other hand, the carry pulse S1 is supplied to one input terminal of each of the AND circuits 46 and 47. At this time, since the flip-flop circuit 44 maintaining the initial state is set at the H level and the flip-flop circuit 45 is set at the L level, AND
The circuit 46 outputs the signal S5 by passing the carry pulse S1, but the AND circuit 47 prevents the carry pulse S1 from passing, so that the signal S6 remains at the L level.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, as described above, the count value of the black pixel data first counter 32 is the same count value as that of the print data transfer clock counter 30, and 448 have not been counted yet, and therefore, the carry pulse S2 Is not output, and the flip-flop circuit 35
Since the reset signal is also in the reset state, the non-inverted output signal S7 maintains the L level and the inverted output signal S8 maintains the H level.
Therefore, the output signal S11 of the NAND circuit 39 remains at the H level, has no effect on the operation of the subsequent circuits, and sets the flip-flop circuits 44 and 45 and the black pixel data first signal. The operation state of the counter 32 does not change. On the other hand, as the output signal S12 of the NAND circuit 40, a pulse signal S12 having substantially the same phase as the carry pulse S1 is output. This signal S12 is supplied to the black pixel data
By being supplied to the counter 34, the black pixel data second
After the counter 34 is reset to the initial value, the clock signal
The counting of black pixel data in the image signal VDATA supplied in synchronization with CK is started. That is, the counting of the black pixel data is started from the head of the area corresponding to the heating element group of the group G2 of the thermal head 14. FIG. 3 (g) shows the time period during which the second counter 34 for black pixel data performs the counting operation as H.
This is indicated by a level signal.

The signal S12 is supplied to the AND circuit 48, so that a pulse signal having substantially the same phase as the carry pulse S1 is output as the output signal S16. And this signal S16
Is supplied to the flip-flop circuit 35, whereby the flip-flop circuit 35 is reset to the initial state. Note that the reset operation at this point is based on the flip-flop circuit.
Since 35 is already in the reset state, it has no particular meaning.

Further, as described above, the output signal S6 of the AND circuit 47 is
Since the output signals S13 and S14 of the NAND circuits 41 and 42 are maintained at the H level because they are maintained at the L level, they do not affect the operation of the circuits at the subsequent stages at all.
The set state of each flip-flop circuit 35, 36, 44, 45 and the operation state of each counter 30, 32, 34 do not change.

Next, point B in FIG. 3, that is, the first counter of black pixel data
The operation when the carry signal S2 from 32 is generated will be described. The first counter 32 outputs the black pixel data, which has started counting simultaneously with the print data transfer clock counter 30, to the first counter 32.
By counting 448 black pixel data in the input image signal VDATA, a carry pulse S2 is generated as shown in FIG. 3 (f). Then, as shown in FIG. 3 (e), the counting operation is stopped.

Then, the first carry pulse S2 is supplied to the flip-flop circuit 35, so that the flip-flop circuit 35
Is set, and an H level signal is output as the non-inverted output signal S7 and an L level signal is output as the inverted output signal S8.
This set state is maintained until the output signal S16 from the AND circuit 48 is driven.

When the flip-flop circuit 35 is set, the black pixel data second counter 34 is in a counting state,
The 448 black pixel data has not yet been counted, and the output signal S3 remains at the L level. Therefore, the flip-flop circuit 36 maintains the initial state, that is, the reset state. The non-inverted output signal S9 is kept at L level and the inverted output signal S10 is kept at H level.

Therefore, one input signal S7 of the OR circuit 37 changes to the H level and the other input signal S9 maintains the L level, so that the output signal S4 becomes as shown in FIG. 3 (i). , H level signals. At this time, carry signal
Since S1 maintains the L level, the signals S5 and S6
Also remains at the L level, and the output signals S11, S12, S13, and S14 of the NAND circuits 39, 40, 41, and 42 all maintain the H level, and have no effect on the operation of the subsequent circuits. Do not give. Therefore, the set state of each flip-flop 35, 36, 44, 45 does not change, and each counter 30, 30
32 and 34 do not return to the initial state.

Next, a description will be given of the operation when the above state is reached and the point C in FIG. 3 is reached, that is, when the second carry pulse S1 is generated. When the print data transfer clock counter 30 counts 864 clock signals CK, the second carry pulse S1 is output. At this time, the flip-flop circuit 35 is in the set state, and the flip-flop circuit 36 is in the reset state. It is in. Therefore, since the non-inverted output signal S7 of the flip-flop circuit 35 is at the H level and the non-inverted output signal S9 of the flip-flop circuit 36 is at the L level, the output signal S4 of the OR circuit 37 is at the H level. The shift register 38 uses the H-level output signal S4 from the OR circuit 37 as shift-in data,
A 1-bit shift operation is performed using S1 as a shift clock, and 4-bit data of “Ln = H, L, *, *” is output as a parallel output, that is, division determination data Ln. Here, the information output as an H level signal to the bit L1 is a black pixel in the range corresponding to the heating elements of the groups G1 and G2 of the thermal head 14 until the carry pulse S1 is output twice. This means that 448 or more data have appeared, which means that the heating element group of the group G1 and the heating element group of the group G2 cannot be simultaneously energized and driven.

On the other hand, the carry pulse S1 is supplied to one input terminal of each of the AND circuits 46 and 47. At this time, since the flip-flop circuit 44 remains at the H level and the flip-flop circuit 45 remains at the L level, the AND circuit 46 remains in the initial state.
Outputs the signal S5 by passing the carry pulse S1, but the AND circuit 47 prevents the carry pulse S1 from passing, so that the signal S6 remains at the L level.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, since the flip-flop circuit 35 is in the set state and the signal S7 is output at the H level, the signal S5 is inverted through the NAND circuit 39 and output as the signal S11. This signal S11 is supplied to the first counter 3 for the black image data via the 3-input AND circuit 31.
2, the black pixel data first counter 3
2, after the set state is returned to the initial value, the counting of black pixel data in the image signal VDATA supplied in synchronization with the clock signal CK is restarted. That is, the thermal head
The counting of the black pixel data is started from the head of the area corresponding to the heating element group of the 14th group G3. The signal S11 is A
By being supplied to the flip-flop circuits 44 and 45 via the ND circuit 43, the flip-flop circuits 44 and 45
Are inverted, the flip-flop circuit 44 outputs an L-level signal, and the flip-flop circuit 45 outputs an H-level signal. Further, when the signal S11 is supplied to the flip-flop circuit 35 via the AND circuit 48, the flip-flop circuit 35 is reset.

On the other hand, the output of the NAND circuit 40 is
Since the inverted output signal S8 is at the L level, it remains at the H level, and does not affect the operation of the circuits at the subsequent stages.

Further, as described above, since the output signal S6 of the AND circuit 47 is maintained at the level, the NAND circuits 41 and 42
Output signals S13 and S14 remain at the H level, and do not affect the operation of the circuits in the subsequent stages at all.

Next, the operation when the carry signal S3 from the point D in FIG. 3, that is, the black pixel data second counter 34 is generated will be described. The black pixel data second counter 34, which has started counting by the first carry pulse S1, counts 448 black pixels in the input image signal VDATA,
As shown in FIG. 3 (h), a carry pulse S3 is generated. Then, as shown in FIG. 3 (g), the counting operation is stopped.

When the first carry pulse S3 is supplied to the flip-flop circuit 36, the flip-flop circuit 36
Is set, and an H level signal is output as the non-inverted output signal S9 and an L level signal is output as the inverted output signal S10. This set state is maintained until the output signal S17 from the AND circuit 49 is driven.

When the flip-flop circuit 36 is set, the first black pixel data counter 32 is in a counting state,
The 448 black pixel data has not yet been counted, and the output signal S2 remains at the L level. Therefore, the flip-flop circuit 35 maintains the reset state, the non-inverted output signal S7 is kept at L level, and the inverted output signal S8 is kept at H level.

Accordingly, one input signal S7 of the OR circuit 37 is maintained at the L level, and the other input signal S9 is changed to the H level. As a result, the output signal S4 of the OR circuit 37 becomes as shown in FIG. It changes to an H level signal. At this time, the carry signal S1
Maintain the L level, the signals S5 and S6 also remain at the L level, and the output signals S11, S12, S13, and S14 of the NAND circuits 39, 40, 41, and 42 all maintain the H level. This has no effect on the operation of the circuits in the next and subsequent stages.
Therefore, the set state of each flip-flop 35, 36, 44, 45 does not change, and each counter 30, 32,
34 does not return to the initial state.

Next, a description will be given of the operation when the state changes as described above and the point E in FIG. 3 is reached, that is, when the third carry pulse S1 is generated. When the print data transfer clock counter 30 counts 1296 clock signals CK, the third carry pulse S1 is output. At this time, the flip-flop circuit 35 is in the reset state, and the flip-flop circuit 36 is in the set state. It is in. Accordingly, since the non-inverted output signal S7 of the flip-flop circuit 35 is at the L level and the non-inverted output signal S9 of the flip-flop circuit 36 is at the H level, the output signal S4 of the OR circuit 37 is at the H level. The shift register 38 uses the H-level output signal S4 from the OR circuit 37 as shift-in data,
A 1-bit shift operation is performed using S1 as a shift clock, and 4-bit data of “Ln = H, H, L, *” is output as a parallel output, that is, division determination data Ln.
Here, the information output as an H level signal to the bit L1 is from the output of the first carry pulse S1 to the output of the third carry pulse S1, that is, the group G2
Means that 448 or more black pixel data appeared in the range corresponding to the heating elements of group G3, which means that the heating element group of group G2 and the heating element group of group G3 were simultaneously energized and driven. Means you can't.

On the other hand, the carry pulse S1 is supplied to one input terminal of each of the AND circuits 46 and 47. At this time, since the flip-flop circuit 44 is set at the L level and the flip-flop circuit 45 is set at the H level, the AND circuit 47 outputs the signal S6 by passing the carry pulse S1, but the AND circuit 46 outputs the signal S6. Since the carry pulse S1 is prevented from passing, the signal S5 remains at the L level.

The output signal S6 from the AND circuit 47 is supplied to one input terminal of each of the NAND circuits 41 and. At this time, since the flip-flop circuit 36 is in the set state and the signal S9 is output at the H level, the signal S6 is inverted and passed through the NAND circuit 41 and output as the signal S13. This signal S13
By being supplied to the black pixel data second counter 34 via the AND circuit 33, the black pixel data second counter 34 returns its set state to the initial value, and then outputs the clock signal CK.
Restarts the counting of black pixel data in the image signal VDATA supplied in synchronization with. That is, the counting of the black pixel data is started from the head of the area corresponding to the heating element group of the group 4 of the thermal head 14. Further, the signal S13 is supplied to the flip-flop circuits 44 and 45 via the AND circuit 43, thereby being inverted respectively, and
Outputs an H level signal, and the flip-flop circuit 45 outputs an L level signal. Further, when the signal S13 is supplied to the flip-flop circuit 36 via the AND circuit 49, the flip-flop circuit 36 is reset.

On the other hand, the output of the NAND circuit 42 is
Since the inverted output signal S10 is at the L level, it remains at the H level, and does not affect the operation of the subsequent circuits.

As described above, the output signal S5 of the AND circuit 46 is L
Since the level is maintained, the outputs of the NAND circuits 39 and 40 remain at the H level, and do not affect the operation of the circuits in the subsequent stages.

Next, in the same manner as described above, the carry pulse S2 from the black pixel data first counter 32, which has started the counting operation with the second carry pulse S1, is output, and the state changes with the flip-flop circuit 35 set. The operation when the point F is reached, that is, when the fourth carry pulse S1 is generated will be described. When the print data transfer clock counter 30 counts 1728 clock signals CK, the fourth carry pulse S1 is output. At this time, the flip-flop circuit 35
Is in a set state, and the flip-flop circuit 36 is in a reset state. Therefore, since the non-inverted output signal S7 of the flip-flop circuit 35 is at the H level and the non-inverted output signal S9 of the flip-flop circuit 36 is at the L level, the output signal S4 of the OR circuit 37 is at the H level. Shift register 38
Performs a 1-bit shift operation using the H-level output signal S4 from the OR circuit 37 as shift-in data and the carry pulse S1 as a shift clock, and performs a parallel output, that is, “Ln = H, H, H, L "
Is output. Here, bit L1 is set to H
The information output as the level signal includes the fourth carry pulse S1 after the output of the second carry pulse S1.
Is output, that is, the group of thermal heads 14
It means that 448 or more black pixel data appeared in the range corresponding to the heating elements of G3 and group G4, which means that
This means that the heating element group of the group G3 and the heating element group of the group G4 cannot be energized and driven at the same time.

On the other hand, the carry pulse S1 is supplied to one input terminal of each of the AND circuits 46 and 47. At this time, since the flip-flop circuit 44 is set to the H level and the flip-flop circuit 45 is set to the L level, the AND circuit 46 outputs the signal S5 by passing the carry pulse S1.
7 prevents the carry pulse S1 from passing, so that the level of the signal S6 is maintained.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, since the flip-flop circuit 35 is in the set state and the signal S7 is output at the H level, the signal S5 is inverted and passes through the NAND circuit 39 and is output as the signal S11. This signal S11
Is supplied to the first black pixel data counter 32 via the three-input AND circuit 31, and the first black pixel data counter 32 returns its set state to the initial value, and then synchronizes with the clock signal CK. The counting of black pixel data in the supplied image signal VDATA is restarted. The signal S11 is AND
The signals are supplied to the flip-flop circuits 44 and 45 via the circuit 43 so that they are inverted. The flip-flop circuit 44 outputs an L-level signal and the flip-flop circuit 44 outputs an H-level signal. Further, the signal S11 is supplied to the AND circuit 48
The flip-flop circuit 35 is supplied to the flip-flop circuit 35 via the, so that the flip-flop circuit 35 is reset.

On the other hand, the output of the NAND circuit 40 is
Since the inverted output signal S8 is at the L level, it remains at the H level, and does not affect the operation of the subsequent circuits.

As described above, the output signal S6 of the AND circuit 47 is L
Since the level is maintained, the outputs of the NAND circuits 41 and 42 remain at the H level, and do not affect the operation of the circuits in the subsequent stages.

By the above operation, the division determination circuit 15 performs the division determination data “Ln = H, H, H, L” for the pixels of one scan line.
Is obtained. The bit L4 of the division determination data Ln is always an L level value, and has no meaning as information.

Next, FIG. 4 is a timing chart showing an operation when black data is concentrated at the center of the document. The operation of each circuit is as described above, except that the timings at which the carry pulses S2 and S3 from the black pixel data first counter 32 and the black pixel data second counter 34 occur are later than in the case of the all black data. The description is omitted because it is the same as the case of FIG. As shown in the figure, “Ln = L, H, L, L” is obtained as the division determination data Ln in this case. Similarly, the division determination data Ln for an all-white original is “Ln = L, L, L, L”
Is obtained.

The division determination data Ln obtained from the division determination circuit 15 in this manner is a group of heating elements that can be simultaneously energized and driven.
G1 ~ G4 represents the information of the combination, for example, while being divided and driven in the form shown in the table below, the interval of conveying the original and recording paper in the sub-scanning direction according to the number of divisions,
That is, the first pulse motor 16 and the second pulse motor
The interval for driving 17 is determined.

First, the operation for recording all white data will be described. When an all-white original is read, the division determination data Ln output from the division determination circuit 15 is “Ln = L, L, L, L”. This division determination data Ln is supplied to the CPU 24 via the PIO 22. As shown in Table 1, the CPU 24 determines that the division determination data Ln is in the division mode shown in FIG. 5, and determines that the transport interval of the recording paper in the sub-scanning direction is “T” time. .

Next, the CPU 24 corresponds to the division determination data Ln,
All the H level conduction division control signals are simultaneously output to the PIO 22 via the data bus, and further supplied from the PIO 22 to one input of the AND circuit 25. The optical signal accumulation time signal SH is input to the other input of the AND circuit 25, and the output signals GATE1 to GATE4 have the same phase as the optical signal accumulation time signal SH as shown in FIG. Appears as it is. When these signals GATE1 to GATE4 are supplied to the gate terminal of the PTC 23, the PTC 23 outputs four enable signals ENA1 having the predetermined pulse width and the same phase as shown in FIG.
~ ENA4 is output. These enable signals ENA1 to ENA4 are
The heating elements of the thermal head 14 are simultaneously energized and driven by being supplied to the respective groups G1 to G4 of the thermal head 14.

Further, the CPU 24, which has determined that the conveyance interval of the recording paper in the sub-scanning direction is “T” time, sends a drive signal to the motor via the PIO 22 for each pulse of the signal SH as shown in FIG. By supplying the excitation to the driver 18, the excitation switching control of the first pulse motor 16 and the second pulse motor 17 is performed, thereby performing the rotation drive.

Next, an operation for recording an image in which black pixel data is concentrated at the center of a document will be described. In this case, as described above, the division determination data Ln output from the division determination circuit 15 is “Ln = L, H, L, L”. This division determination data Ln is supplied to the CPU 24 via the PIO 22. CP
U24 determines, as shown in Table 1, that the division determination data Ln has the division form shown in FIG. 6, and the transport interval of the recording paper in the sub-scanning direction is twice that in the case of the all white data. Is determined to be “2T” time.

Next, the CPU 24 outputs an energization division control signal corresponding to the division determination data Ln to the PIO 22 via the data bus,
Further, the signal is supplied from the PIO 22 to one input of the AND circuit 25. At this time, since the bit L1 is at the L level, the signal GATE
Since 1 and GATE2 are at the same time, the bit L2 is at the H level, the signals GATE2 and GATE3 are shifted in time, and since the bit L3 is at the L level, the output timing is controlled so that the signals GATE3 and GATE4 are at the same time. The other input of the AND circuit 25 includes:
When the signal SH is input and the first signal SH is output as shown in FIG. 10, the signals are output to GATE1 and GATE2.
When a signal having the same phase as SH is output and the second signal SH is output, a signal having the same phase as the signal SH is output to GATE3 and GATE4. By supplying these signals GATE1 to GATE4 to the gate terminal of the PTC 23, the PTC 23, as shown in FIG. 10, has two enable signals ENA1 and ENA2 having a predetermined pulse width and the same phase, and the phases thereof are different from each other. Two enable signals ENA3 and ENA4 having a predetermined pulse width and having the same phase
Are successively output. These enable signals ENA1 to ENA
A4 is supplied to each of the groups G1 to G4 of the thermal head 14, so that the heat generating elements of the groups G1 and G2 of the thermal head 14 simultaneously, and after a signal SH time, the G4 of the group G3 of the thermal head 14 And the heating elements are simultaneously driven with a time difference.

Further, the CPU 24, which has determined that the transport interval of the recording paper in the sub-scanning direction is “2T” time, sends a drive signal via the PIO 22 every two pulses of the signal SH as shown in FIG. By supplying the excitation to the driver 18, the excitation switching control of the first pulse motor 16 and the second pulse motor 17 is performed, thereby performing the rotation drive. This means that it takes twice as long to print one line as compared to the case of all white data.

Next, an operation when the division determination data Ln is “Ln = H, H, L, L” will be described. The division determination data Ln output from the division determination circuit 15 is supplied to the CPU 24 via the PIO 22. As shown in Table 1, the CPU 24 performs the above-described division determination data L
n is determined to be the division mode shown in FIG.
It is determined that the transport interval of the recording paper in the sub-scanning direction is "3T" which is three times as long as that of the all white data.

Next, the CPU 24 outputs an energization division control signal corresponding to the division determination data Ln to the PIO 22 via the data bus,
Further, the signal is supplied from the PIO 22 to one input of the AND circuit 25. At this time, since the bit L1 is at the H level, the signal GATE
1 and GATE2 are shifted in time and the bit L2 is at the H level, so the signals GATE2 and GATE3 are also shifted in time and the bit
Since L3 is at the L level, the output timing is controlled so that the signals GATE3 and GATE4 are at the same time. The signal SH is input to the other input of the AND circuit 25. As shown in FIG. 11, when the first signal SH is output, only the GATE1 signal is output, and the second signal SH is output. When the signal SH is output
When only the GATE2 signal is output and the third signal SH is output, signals of the same phase are output to GATE3 and GATE4. By supplying these signals GATE1 to GATE4 to the gate terminal of the PTC 23, the PTC 23, as shown in FIG.
An enable signal ENA1 having a predetermined pulse width, an ENA2 having a predetermined pulse width different in phase from the enable signal ENA1, and an enable signal ENA2 having a predetermined pulse width different in phase from the enable signal ENA1
Two enable signals ENA3 and ENA4 are sequentially output. By supplying these enable signals ENA1 to ENA4 to the groups G1 to G4 of the thermal head 14, respectively,
The heating elements of the group G1 of the thermal head 14 are simultaneously, after a signal SH time, the heating elements of the group G2 are simultaneously, and after the signal SH time, the heating elements of the groups G3 and G4 of the thermal head 14 are simultaneously driven with a time difference. You.

Further, the CPU 24, which has determined that the conveyance interval of the recording paper in the sub-scanning direction is “3T” time, sends a drive signal via the PIO 22 every three pulses of the signal SH as shown in FIG. By supplying the excitation to the driver 18, the excitation switching control of the first pulse motor 16 and the second pulse motor 17 is performed, thereby performing the rotation drive. This means that it takes three times as long to print one line as compared to the case of all white data.

Next, the operation for recording all black data will be described. In this case, as described above, the division determination data Ln output from the division determination circuit 15 is “Ln = H, H, H, L”. The division determination data Ln output from the division determination circuit 15 is supplied to the CPU 24 via the PIO 22. CPU24
As shown in Table 1, the division determination data Ln is determined to be in the division mode shown in FIG. 8, and the transport interval of the recording paper in the sub-scanning direction is "4T" which is four times that in the case of the all white data. It is determined that it is time.

Next, the CPU 24 outputs an energization division control signal corresponding to the division determination data Ln to the PIO 22 via the data bus,
Further, the signal is supplied from the PIO 22 to one input of the AND circuit 25. At this time, since the bit L1 is at the H level, the signal GATE
1 and GATE2 are shifted in time and the bit L2 is at the H level, so the signals GATE2 and GATE3 are also shifted in time and the bit
Since L3 is at the H level, the timing is controlled so that the signals GATE3 and GATE4 are also output with a time lag. AND circuit 2
The other input of 5 receives the signal SH, and
As shown in FIG. 2, when the first signal SH is output,
When only the ATE1 signal is output, when the second signal SH is output, only the GATE2 signal is output, and when the third signal SH is output, only the GATE3 signal is output, and the fourth signal SH is output. When the signal SH is output, only the GATE4 signal is output. By supplying these signals GATE1 to GATE4 to the gate terminal of the PTC 23, the PTC 23, as shown in FIG.
An enable signal ENA1 having a predetermined pulse width and this EN
ENA2 having a predetermined pulse width different in phase from A1 and ENA3 having a predetermined pulse width different in phase from ENA2
Further, the enable signals ENA4 having a predetermined pulse width different in phase are sequentially output.These enable signals ENA1 to ENA4 are supplied to the groups G1 to G4 of the thermal head 14, respectively. The heating elements of the groups G1, G2, G3, and G4 of the thermal head 14 are driven by time difference conduction with the signal SH time shifted.

Further, the CPU 24, which has determined that the transport interval of the recording paper in the sub-scanning direction is “4T” time, outputs a drive signal via the PIO 22 every four pulses of the signal SH as shown in FIG. By supplying the excitation to the driver 18, the excitation switching control of the first pulse motor 16 and the second pulse motor 17 is performed, thereby performing the rotation drive. This means that it takes four times as long to print one line as compared to the case of the all white data.

As described above, when the thermal head 14 is energized and driven, it is possible to drive the thermal head 14 by dividing it into four groups, while detecting the distribution of black pixel data in one scan line, According to this detection result, the above group is simultaneously driven within a range not exceeding the maximum allowable number of simultaneous energizing elements, and when the maximum allowable number of simultaneous energizing elements is exceeded, the staggered energizing drive is performed with a time lag. Drive power supply can be reduced in size and capacity, and the recording speed (corresponding to the printing speed of all black data in the above embodiment) cannot be improved by simple staggered energization as in the prior art. Thus, high-speed printing can be performed according to the appearing pixel data. Also,
Since the generation of the division determination data is performed by hardware and the intervention of software is reduced as much as possible, the time required for recording can be reduced.

In the above-described embodiment, the case where the thermal head 14 is divided into four groups and the time difference energizing drive is described, but the number of divisions is not limited to four. Has the same effect.

Next, details of the rechargeable battery voltage detection circuit 19 will be described. In FIG. 13, a rechargeable secondary battery 40 is a main power supply of the present apparatus and generates electric power to be supplied to each section of the apparatus. The output of this rechargeable secondary battery 40 is
It is supplied to. The stabilization circuit 41 removes unstable voltage fluctuations inherent in the rechargeable secondary battery 40 and enables stable supply of voltage.

The voltage detection circuit 42 includes an operational amplifier OP1 and resistors R1 and R1.
And 2. The output of the operational amplifier OP1 of the voltage detection circuit 42 is supplied to the A / D converter 43. The A / D converter 43 converts an analog signal output from the operational amplifier OP1 into a digital signal and supplies the digital signal to the PIO 22.

Rechargeable battery voltage detection circuit 19 configured as described above
Works as follows. That is, the rechargeable secondary battery 40
Is supplied to the stabilizing circuit 41, while being divided by the resistors R1 and R2 and supplied to the non-inverting input terminal of the operational amplifier OP1. This operational amplifier OP1 constitutes a voltage follower, and supplies the A / D conversion circuit 43 with the voltage divided by the resistors R1 and R2 by removing the influence from the preceding stage. A / D conversion circuit
43 converts the voltage into a digital signal and outputs it to the PIO 22. Then, the signal from the PIO 22 is supplied to the CPU 24 via the data bus. For example, when the CPU 24 detects that the voltage of the rechargeable secondary battery 40 has dropped, the CPU 24 increases the energizing time to the heating element of the thermal head 14, that is, the pulse width of the enable signal, according to the voltage drop value. Thus, the print density determined by the product of the applied voltage and the energization time is controlled to be kept constant.

Next, details of the thermistor temperature detection circuit 20 will be described. In FIG. 13, a thermistor 50 is built in the thermal head 14 and indirectly detects the temperature of the heating element. The output of this thermistor 50 is
Are supplied to the non-inverting input terminal of The operational amplifier OP2 converts the amount of change in the resistance value of the thermistor 50 with respect to the temperature into a voltage, and outputs the voltage to the A / D converter 51. The A / D converter 51 converts an analog signal output from the operational amplifier OP2 into a digital signal and supplies the digital signal to the PIO 22. The signal from the PIO 22 is supplied to the CPU 24 via a data bus, and is monitored by the CPU 24. The CPU 24 calculates the optimum energizing time, that is, the pulse width of the enable signal, corresponding to the detected temperature of the heating element in the thermal head 14, and thereby controls the moving speed of the recording paper in the sub-scanning direction. Has become. That is, if the heating element is already at a certain temperature or higher, a sufficient temperature for recording can be obtained with a short energization time. Conversely, if the temperature is below a certain level,
It is necessary to increase the energizing time to obtain a temperature sufficient for recording.

As described above, by controlling the energizing time according to the temperature of the heating element of the thermal head 14, that is, controlling the pulse width of the enable signal, it is possible to prevent printing unevenness, and to shorten the energizing time when the heating element is in a high temperature state. Is capable of high-speed recording.

Further, details of the sub-scanning pixel density detection circuit 21 will be described. In FIG. 13, the black pixel data counter 60
The image signal VDATA for one scanning line output from the image processing circuit 13 is counted in synchronization with the clock signal CK. The memory 61 is composed of, for example, a dual port RAM, and stores the value counted by the black pixel data counter 60 and outputs the stored number of black pixel data one line before to the comparator 62 at the same time. Things.

The comparator 62 inputs the number of black pixel data counted by the black pixel data counter 60 to one input terminal A, and outputs the number of black pixel data one line before output from the memory 61 to the other input terminal b.
In this case, three signals output from the terminals A> B, A = B and A <B are supplied to the PIO 22.

Next, the operation of the sub-scanning pixel density detecting circuit 21 will be described. First, the START signal is sent from the CPU 24 to start recording for one scanning line.
The black pixel data counter 60 starts counting black pixel data included in the image signal VDATA sent from the image processing circuit 13 in synchronization with the clock signal CK. When the counting for one scan line is completed, the data is sent to the memory 61 and stored, and at the same time, is supplied to the A input terminal of the comparator 62. On the other hand, the memory 61 outputs the number of black pixel data of the previous line. And supplied to the B input terminal of the comparator 62.

From the output terminal of the comparator 62, the comparison result is A> B, A =
B, output as three signals of A <B and output via PIO22 to C
Supplied to PU24.

When the CPU 24 detects that the comparison result is A> B, that is, the number of black pixel data of the current line is larger than the number of black pixel data of the previous line, the CPU 24 determines that the number of black pixel data in the image signal VDATA is increasing. In addition, the energizing time to the thermal head 14 is shortened. That is, the pulse width of the enable signals ENA1 to ENA4 for driving the thermal head 14 is reduced.

If the comparison result indicates that A <B, that is, the number of black pixel data of the current line is smaller than the number of black pixel data of the previous line, it is determined that the number of black pixel data in the image signal VDATA has decreased. The energization time to the thermal head 14 is extended. That is, the pulse width of the enable signals ENA1 to ENA4 for driving the thermal head 14 is increased.

When the comparison result detects that A = B, that is, the number of black pixel data of the current line is equal to the number of black pixel data of the previous line, it is determined that the black pixel data in the image signal VDATA has not changed. Then, the energizing time to the thermal head 14 maintains the previous state. That is, the pulse widths of the enable signals ENA1 to ENA4 for driving the thermal head 14 are not changed.

As described above, by changing the energization time of the heating element of the thermal head 14 in accordance with the change of the pixel density in the sub-scanning direction, the energization time corresponding to the image density can be given, and the density unevenness of the image can be prevented. At the same time, power is not efficiently supplied, so that efficient power control can be performed. In addition, when the energization time is short, high-speed recording can be performed.

[Effects of the Invention] As described above in detail, according to the present invention, the thermal element group is driven in a staggered manner according to the pixel density, so that a thermal recording apparatus capable of performing high-speed recording can be provided. .

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is a block diagram schematically showing a configuration of an electric circuit, FIG. 2 is a diagram showing a detailed circuit configuration of a division determination circuit, and FIGS. 4 is a timing chart for explaining the operation of the division determining circuit, FIGS. 5 to 8 are explanatory diagrams for explaining the divisional driving of the thermal head, and FIGS. 9 to 12 are divisional drivings of the thermal head. FIG. 13 is a diagram showing a detailed configuration of a rechargeable battery voltage detection circuit, a thermal head thermistor temperature detection circuit, and a sub-scanning pixel density detection circuit. 10 timing clock generation circuit, 12 CCD sensor, 13 image processing circuit, 14 thermal head (recording head), 15 division determination circuit (detection means, determination means), 16, 17 ... Pulse motor, 18 Motor driver, 22 PIO, 23 PTC, 24 CPU (time difference driving means).

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-56-148681 (JP, A) JP-A-62-122368 (JP, A) JP-A-52-56544 (JP, A) JP-A-60-1985 187175 (JP, A) JP-A-63-224972 (JP, A) JP-A-57-84865 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) B41J 2/35 -2 / 38 B41J 2/30

Claims (1)

(57) [Claims] 1. A recording head comprising a plurality of heating elements arranged in a line, wherein the plurality of heating elements are divided into a plurality of groups and print data is recorded on a recording medium in group units. Output means for outputting a transfer start signal of print data to be recorded; and a clock signal for transferring the print data in accordance with the transfer start signal output from the output means, a count value corresponding to the number of heating elements constituting the group. A clock counter that outputs a carry signal by counting up to the above, and a carry signal that counts black pixel data of the transferred print data to a number of heating elements that are greater than the number of heating elements constituting the group and can be simultaneously driven. A first counter for outputting the black pixel data of the transferred print data, the number of which is larger than the number of the heating elements constituting the group, and A second counter that counts up to the number of heat-generating elements that can be simultaneously driven and outputs a carry signal; and a transfer start signal output from the output means and a carry signal from the clock counter. Control means for selectively starting the counter and the second counter; carry signal output from the clock counter; and the first and second controlled start counts by the control means.
Generating means for generating a signal indicating a group that can be simultaneously driven in accordance with a carry signal output from the counter of the above, and driving for driving and controlling the printhead in group units in accordance with the signal generated by the generating means A recording device, comprising: control means;