JP2799008B2 - Solid-state imaging device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an improvement of a solid-state imaging device. Charge Coupled Device
s, hereinafter abbreviated as “CCD”), and relates to a CCD solid-state imaging device for extracting image signals.

(Prior Art) A conventional CCD type solid-state imaging device 30 of this type was configured as shown in FIG. That is, the element portion A of the drive circuit
-1 connects a plurality of vertical transfer registers V-1,..., Vn constituted by CCDs to two horizontal transfer registers H-1 and H-2 each constituted by CCDs. A plurality of photodiodes PD ₁₁ , PD ₁₂ , PD _1n ;... _N ,...; PD _n1 , PD _{n2 ,.}
Are connected so as to be arranged in a matrix (Matrix), so that a plurality of pixels corresponding to an image (not shown) can be photoelectrically converted. 24, a signal pulse φHG having the waveform shown in FIG.
-2, alternately every other pixel.

Also, the horizontal transfer registers H-1 and H-2 are provided with transfer electrodes H1, H2,... Sequentially from the right side to the left side in the figure, and the horizontal transfer registers H-1 and H-2 are provided on the output side. a final electrode H2 ₀ connected to, terminating electrode H1 ₀ to the horizontal transfer register H2 end on the left side of the final electrode H2 ₀ are disposed, one pixel signal charges transferred by the horizontal transfer register H2 It is configured to delay by minutes.

Further, on the left side of the final electrode H2 ₀ and the terminal electrodes H1 ₀ provided reset unit A-2 of the drive circuit A (general configuration, in FIG. 22 in relation to the horizontal transfer register H1, H2 ), An adder circuit 20a (second
The horizontal transfer registers H-1 and H-1 are provided.
-2 outputs out1 and 2 are added and output as one time-series signal output.

When a predetermined image is read by the solid-state imaging device 30 having the above-described configuration, first, before the signal image is started by the horizontal transfer registers H-1 and H-2, the transfer electrode H1 is first set at H-2.
The signal charges distributed to the lower side are transferred to the lower side of the transfer electrode H2, and then, as shown in FIG. 24, the signal charges are sequentially and alternately output to the output side (left side) with the pulses φH1 and φH2 which are 180 ° out of phase.
To be transferred to

In this way, the signal charges are transferred to the final electrode H2 _0. Horizontal transfer pulse to the last electrode H2 ₀ .phi.H2 (24
Aside from this, the output waveform is prevented from deteriorating by performing short-wave drive.

Transferred signal charges to the final electrode H2 ₀ and H1 ₀ below, the final electrode H2 _0, through the reset unit A-2 of the driver circuit 10 provided on the terminating electrode H1 ₀ left as the output out1. The signal charges transferred by the horizontal transfer register H2 likewise simultaneously reach the final electrode H2 _0. However, the signal charges transferred by the horizontal transfer register H-2 are H-1
Compared to the transferred becoming the signal charge by, is not necessary to output delays one pixel must not, to carry out the delay of this one pixel is the end electrodes H1 _0.

Terminating electrode H1 ₀ also, the final electrode H2 ₀ Similarly, by driving at square wave, as shown in FIG. 24, can suppress waveform degradation of an output out2 of H2. Terminating electrode H1 ₀ after passing through the output out
Take exactly the same path as 1.

In this way, the two outputs (out1, out2) obtained from the horizontal transfer registers H-1, H-2 are input to the adder circuit 20a, as shown in FIG. A resolution corresponding to the number of pixels can be obtained. FIG.
As an example of the addition, there is an example in which a signal of out1 is gated by a pulse SP1, a signal of out2 is gated by a pulse SP2, and two signal outputs are added.

Conventionally, the above-described CCD type solid-state imaging device 30 is driven as described above. However, in such a drive, when outputting a CCD, one pixel is output between two output signals (that is, 180 pixels).
24), the reset operation of the outputs obtained from the horizontal transfer registers H-1 and H-2 is performed by a phase shift of 180 degrees, as shown in the timing chart of FIG. This must be done with two different types of pulses. The phase relationship between the reset pulse and the output waveform is such that during the output period of out1, the reset pulse φRS2 of out2
During the output period of 2, a reset pulse φRS1 of out1 is applied.

A schematic configuration of a reset section A-2 is constructed as FIG. 22, the signal charges transferred by the horizontal transfer register H-1 and H2 final electrode H2 ₀ and the final electrode H
Via 1 _0, is output as a voltage signal via the sense capacitance _{C 1, C 2 (out1,} cut2). In this case, after detecting the output of each one pixel, and MOSFET Q _1, a reset pulse having a waveform shown in FIG. 24 to the gate of Q ₂ φRS1, the MOSFET Q _1, Q ₂ in addition to φRS2 in the "on" state, the sense capacitance C _1, C ₂ signal charges accumulated in and discharged to the reset drain RD, and to perform the reset operation.

(Problems to be Solved by the Invention) However, the two output paths out1 and out2 described above are provided on the same chip, and it is difficult to completely eliminate the interference between the channels. There is a troublesome problem that each output waveform is significantly deteriorated due to interference between channels due to the above.

In a CCD type solid-state imaging device having a structure having two horizontal transfer registers, the number of pixels in the horizontal direction is large, and the driving frequency of horizontal transfer is often high. For this reason, as the number of pixels is increased in order to increase the resolution, there is also an inconvenience problem that the deterioration of the output waveform due to interference between channels has a greater effect. In a CCD having at least two horizontal transfer registers, such a waveform deterioration is caused by a 180 degree phase difference in order to output the output signals of two channels shifted by one pixel at the time of output from the CCD. Two types of reset pulses are required. On the other hand, considering that the phenomenon of output waveform degradation due to inter-channel interference caused by two types of reset pulses is an essential problem that cannot be avoided, at the time of output from the CCD,
An object of the present invention is to provide a solid-state imaging device capable of reading out channel signals in phase, thereby suppressing deterioration of an output waveform due to interference between two channels, and reading out high-quality images.

[Configuration of the invention]

(Means for Solving the Problems) One of the basic configurations of the solid-state imaging device of the present invention for achieving the above-mentioned problems (claim (1)) is configured by CCDs as shown in FIG. A plurality of vertical transfer registers V-1,..., Vn arranged in parallel and a horizontal transfer register H
,..., H-2, and photoelectrically converts the received image into each of the plurality of vertical transfer registers V-1,. element
In the solid-state imaging device provided with a plurality of PDa, the plurality of horizontal transfer registers H-1 and H-2 are formed so that outputs between the respective horizontal transfer registers H-1 and H-2 can be read in phase. Charge-coupled devices H-1 and H-2, delay means 11 for adjusting the phase relationship between the outputs of the respective horizontal transfer registers, and respective outputs of the horizontal transfer registers after adjusting the phase relation by the delay means 11. Are added to form one time-series signal.

1. Element part A-1 of the drive circuit 10 of the solid-state imaging device of FIG.
Are a plurality of vertical transfer registers V-1, V
−2,..., Vn; and the horizontal transfer registers H−1 and H−2.
The horizontal transfer registers H-1 and H-2 are formed in the same number of stages so that the output between the horizontal transfer registers H-1 and H-2 can be read in the same phase as shown in FIG. the final electrode H ₀ is provided parts. The signal charges transferred in the vertical transfer registers V-1, V-2,..., Vn are respectively transferred to the horizontal transfer registers H-1,
H-2 is assigned to each pixel.

A reset unit A-2 shown in FIG. 3 is provided on the output side of the horizontal transfer registers H-1 and H-2, and is configured to be reset or output by the output amplifiers FDA1 and FDA2 and the reset RS. ing.

Another basic configuration of the solid-state imaging device according to the present invention (claim (2)) is that, as shown in FIG. 4, a plurality of vertical transfer registers, which are constituted by CCDs, are arranged vertically, and are horizontally transferred. A solid-state imaging device comprising: a plurality of vertical transfer registers; and a plurality of vertical transfer registers, each including a plurality of photoelectric conversion elements that photoelectrically convert a received image and transmit signal charges to the vertical transfer registers. The horizontal transfer registers are configured to hold and delay the phase relationship between the output signals of the respective horizontal transfer registers, and charge-coupled devices H-1 and H-2a are provided. Driving means for reading the force of each horizontal transfer register in phase, delay means 11 for adjusting the phase relationship between the outputs of each horizontal transfer register, and phase correlation by the delay means 11 The present invention is characterized in that there is provided an adding means 20 for adding the outputs of the respective horizontal transfer registers after the engagement adjustment to form one time-series signal.

However, the element section A-2 and the reset section A-2 of the drive circuit 10 of the solid-state imaging device according to claim (2) have the same configurations as those shown in FIGS. 22 and 23.

(Operation) As described above, in the solid-state imaging device 30-I of claim (1), a plurality of channel signals output in the same phase from the CCD end of the horizontal transfer register are output from the CCD end, and thereafter, one signal output After the phase adjustment between a plurality of channels is performed through the delay means 11, the plurality of outputs after the phase adjustment are made into a single time-series signal output by the addition means 20, so that waveform deterioration due to interference between the channels is greatly suppressed. You.

The solid-state imaging device 30-II according to claim (2) includes:
By using a CCD with a conventional configuration, the delay operation provided in the CCD is stopped by the bias setting means, and the CCD is driven by the in-phase driving means, so that the output from the horizontal transfer register can be read out in phase. it can. And
Thereafter, similar to the solid-state imaging device 30-I of claim (1),
One output signal is subjected to phase adjustment between a plurality of channel signals through the delay means 11 and each output is converted into one time-series signal through the addition means 20, so that waveform deterioration due to interference between channels is significantly suppressed.

(Embodiment) Next, an embodiment of a solid-state imaging device according to the present invention will be described with reference to the drawings.

Embodiment 1 FIGS. 5 and 13 are a block diagram showing a schematic configuration of a first embodiment of a solid-state imaging device 30-I according to claim (1) of the present invention, and a drive pulse waveform of a drive circuit 10. It is a timing chart figure.

In FIG. 5, H-1 and H-2 are CCDs formed so that the output between the horizontal transfer registers can be read in the same phase, and 11a is output from the transfer registers H-1 and H-2 in the same phase. An analog delay line (hereinafter abbreviated as "DLY") for adjusting the phase by passing one of the two CCD outputs, and 11b is a gate circuit.

When the pulse φHG having the waveform shown in FIG. 13 is applied to the horizontal separation gate HG to turn on the "on" state, the signal charges transferred by the vertical transfer registers V-1,. 1 and H-2, and when the horizontal transfer pulses φH1 and φH2 having the waveforms shown in FIG. 13 are applied to the transfer electrodes H1 and H2 on the horizontal transfer registers H-1 and H-2, the transfer electrodes H1 and H2 are applied. signal charges under H2 is transferred to the final electrodes H _0.

When driven at this timing, before the horizontal transfer is started, the signal charges distributed to the horizontal transfer registers H-1 and H-2 are aligned on the same column, and then the horizontal transfer is performed. In both 1 and H-2, the number of transfer electrodes up to the final electrode is equal, and they are output in the same phase.

Further, the output of the horizontal transfer register H-1 and H-2 via a final electrode H _0, a schematic configuration of a solid-state imaging device 30a of the reset unit A-2 (reset section A-2 of the present embodiment in FIG. 3 Output amplifiers FDA1, FDA2 and reset RS
When a reset pulse φRS is applied to the gate as shown in FIG. 13 (see FIG. 3), the MOSFEF is turned on and the signal charges stored in the reset capacitors C ₁ and C ₂ are reset by the reset drain RD. And a reset operation is performed.

In the driving in the present embodiment, unlike the conventional example, since the phase of the other reset pulse does not exist in the signal period of the other channel, the waveform deterioration due to the interference between the channels due to the reset pulse is significantly improved compared to the conventional example. Is done. Hereinafter, out of the CCD outputs OUT1 and OUT2 output in the same phase, OUT adjusts the phase by passing through DLY11a, and then adds two signals by gate pulses SP1 and SP2 in each signal period. For example, a resolution corresponding to the number of horizontal pixels can be obtained. In this method, high-quality images can be obtained because the waveform deterioration during the signal period can be greatly suppressed.

Embodiment 2 FIGS. 6 and 15 are a block diagram showing a schematic configuration of a second embodiment of the solid-state imaging device 30-I according to the first aspect of the present invention, and FIG. FIG. 4 is a timing chart of the driving pulse waveform of FIG. H-1 and H-2 in FIG. 6 are transfer register CCDs.
11c is a horizontal transfer register that can read the outputs of the two CCDs in phase with the horizontal transfer registers H-1 and H-2.
Reference numeral 11d denotes a circuit for performing a sample-and-hold process (hereinafter abbreviated as "S / H").

As the structure of the CCD element structure A-1 and the reset unit A-2 used in the present embodiment, the structures shown in FIGS. 2 and 3 are used.

In this embodiment, the clamp and sample hold processes are performed after the CCD output. FIG. 25 shows a CCD output waveform for explaining the process. In FIG. 25, T ₁ is reset period, T ₂ is feed through period, T ₃ is the signal period.

In the present embodiment, 2
The channel signal is clamped by the common clamp pulse P _CLP during the feed-through period of the CCD output, 1 / f noise included in the CCD output is suppressed, and then the signal period is sampled and held using the pulse P _{S / H} Perform This makes it possible to suppress the reset noise generated during the feedthrough period and the signal period.

These clamps and sample hold are performed in the same phase on two channels, and the delay and addition thereafter are the same as those described in the first embodiment. The drive pulse is applied according to the timing chart shown in FIG.

The feedthrough period shown in the present embodiment is clamped,
The method of suppressing the noise by sampling and holding the signal period has been used in the past, but in the conventional case, the phase of the reset pulse is shifted by 180 ° between channels, and the waveform is deteriorated at the time of CCD output. The feedthrough period to be clamped and the signal period to be sampled and held are not clear. Also, clamp pulse,
Sample hold pulse has a phase of 180 between two channels.
波形 The waveforms deviate from each other, and the waveform deterioration due to this is not negligible. For this reason, there is a problem that the noise suppression effect is not clear.

According to the present embodiment, the CCD output is read out in phase with two channels to suppress waveform deterioration at the CCD output end, and the clamp pulse and the sample and hold pulse used in the subsequent noise suppression processing are made common, so that the channel is output. It is possible to obtain a high-quality image by clarifying the noise suppression effect by minimizing mutual interference between them.

Embodiment 3 FIG. 7 shows a solid-state imaging device 30 according to claim (1) of the present invention.
FIG. 16 is a block diagram showing a schematic configuration of a third embodiment -I, and FIG. 16 shows a time chart of driving waveforms. Also in this embodiment, the CCDs of the same phase readout structure are driven by using the horizontal transfer registers H-1 and H-2, and the two channels are output in the same phase at the time of CCD output of these two horizontal transfer registers. However, the difference from the first and second embodiments is apparent with reference to the timing chart of FIG.
A reset pulse φRS and .phi.H2 ₀ has in common, the duty of the reset period of the output signal is the point that 50%.

By narrowing the pulse width of φRS than the pulse width of the first and second embodiments in .phi.H2 _0, but always in the presence of a feed-through period between the reset period and the signal period, the number of pixels CCD is increased, the driving As the frequency increases, it becomes difficult to perform reset with a narrow pulse, and to secure a feedthrough period before a signal period. Also, it becomes difficult to perform the reset operation reliably in a short time even in the reset operation.

For this reason, the reset pulse is set to 50% duty to ensure the reset operation, and the widened reset part is clamped to suppress visually noticeable 1 / f noise and improve image quality. This is the purpose of this embodiment.

The means of delay and addition after 1 / f noise suppression is the same as in the previous embodiment, but the process of adding the two-channel signal after delaying OUT2 with the delay line increases the drive frequency,
When gate addition is difficult due to SP1 and SP2, a resolution substantially corresponding to the number of pixels can be obtained even by simple resistance diffusion.

Also in this embodiment, it is possible to obtain a high-quality image in which visually noticeable 1 / f noise is suppressed.

The effect described above has been described in connection with the case where the number of horizontal transfer registers is two, but can also be applied to the case where there are two or more.

Embodiment 4: FIGS. 8 and 14 are a block diagram and a timing chart of driving pulse waveforms, respectively, showing a schematic configuration of a fourth embodiment of the solid-state imaging device 30-I according to claim (1) of the present invention. It is.

In this embodiment, as in the first embodiment, a CCD having an in-phase readout structure is driven. At the time of CCD output, both channels are output in the same phase. In this embodiment, the delay operation of OUT2 after the CCD output and the addition operation of OUT1 are performed by the sample hold circuit and the gate circuit. Sampling and holding are performed simultaneously with the pulse of P _{S / H} while the CCD outputs are output in the same phase. The result is a waveform of OUT1S / H and OUT2S / H in FIG. In this state, a signal output is obtained by gating the OUT1S / H signal at SP1 that gates the first half of the sample and hold period and OUT2S / H at SP2 that gates the second half of the hold period. In this method, waveform deterioration due to mutual interference between channels as in the related art is greatly improved, and a high-quality image can be obtained.

Embodiment 5: Claims (2) of the present invention are shown in FIGS. 9 and 17, respectively.
1 is a block diagram showing a schematic configuration of a first embodiment of the solid-state imaging device 30-II, and a timing chart of driving pulse waveforms. However, the element structure A-1 and the reset unit A-2 of the drive circuit of the solid-state imaging device according to the present embodiment are the same as those described in the 22nd embodiment.
The same structure as that shown in FIG. 23 and FIG. 23 was used.

.., Vn are vertical transfer registers, PD is a photodiode, FDA1 and FDA2 are output amplifiers, H-1 and H-2 are horizontal transfer registers, and DLY is an analog delay line. In the embodiment, similarly to the conventional example, a CCD having two horizontal transfer registers
Will be described.

Here horizontal isolation gate HG, transfer electrodes H1, a horizontal transfer pulse applied to H2 (φH1, φH2), pulse .phi.H2 ₀ to be applied to the final electrode H2 ₀ horizontal register H1 is exactly the same timing as the conventional example. When driven in this timing, after being aligned on transfer register H-1 and the signal charges distributed to the H2 is the same column before starting the horizontal transfer, until H2 ₀ for the horizontal transfer is performed the transfer phase is carried out, is the same as the conventional example, in the prior art final electrode H1 _0,
H2 only one pixel signal charges of H2 is delayed for applying pulses whose phases are inverted from ₀ to add pulse .phi.H1 ₀ and .phi.H2 ₀ and also the phase is inverted reset pulse, the output is also the phase is inverted that become. The final electrode H1 ₀ in this example H-2
Always under the final electrode H1 ₀ potential wells are formed by applying a fixed bias voltage of V in. When the final electrode H2 ₀ changes from Hi level to Lo level in this state, the signal charges transferred from the transfer electrode H2 ₀ is passed without it delays under H2 ₀ electrode. Therefore, the signal charges transferred by the transfer registers H-1 and H-2 are transferred in the same phase to the reset portion.

Therefore, the signal charges of the two channels can be reset at the same time, so that a common reset pulse can be used. As a result, the two-channel signal is output at the CCD output terminal in the same phase.

In the conventional example, since the two-channel signals are already output from the CCD output terminal in a 180 ° shifted relationship, a resolution equivalent to the number of horizontal pixels can be obtained by simply adding the two signals thereafter. Since the phase of the reset pulse of the other channel exists in the signal period of each output signal, it is inevitable that the waveform of the signal period deteriorates due to mutual interference. Since this deterioration has already occurred at the output of the CCD, it cannot be improved by subsequent signal processing or the like, and is a main cause of image quality deterioration.

In this embodiment, the CCD output terminal has the same phase, but since the reset pulse is common, the phase of the reset pulse does not exist in the signal period of the output signal. You. After the CCD output, the signal of OUT2 passes through a delay line corresponding to one pixel, and then the signal period of each output signal is alternately gated by gate pulses SP1 and SP2 to add the signals to return to the original phase relationship. For example, a resolution corresponding to the original number of horizontal pixels can be obtained. In this method, high-quality images can be obtained because waveform deterioration during the signal period can be suppressed.

Each of the solid-state imaging devices according to the fifth to eighth embodiments is an embodiment of the solid-state imaging device 30-II according to claim (2), and includes an element unit A-2 and a reset unit A- of a drive circuit.
The element structure of No. 2 is the same as the conventional one (FIGS. 22 and 23)
It is.

Embodiment 6: FIGS. 10 and 18 are a block diagram and a timing chart of driving pulse waveforms, respectively, showing a schematic configuration of a second embodiment of the solid-state imaging device 30-II according to claim (2) of the present invention. It is.

In this embodiment, the driving of the CCD is the same as in the first embodiment,
The output is output in the same phase for both channels. Here, the delay and the addition of the two-channel signal are performed by a sample-and-hold circuit and a gate circuit. The sample and hold function simultaneously outputs P _{S / H} with CCD output in the same phase.
As a result, OUT1S / H, OU in Fig. 18
The waveform becomes T2S / H. In this state, if OUT1S / H is gated by SP1 that gates the first half of the sample and hold period and OUT2S / H is gated by SP2 that gates the second half, the output signal OUT
Can be obtained.

Also in this embodiment, since the signals are read out in the same phase at the time of CCD output, deterioration of the signal period is suppressed, and a high-quality image can be obtained.

Embodiment 7: FIGS. 11 and 19 are a block diagram and a timing chart of driving pulse waveforms, respectively, showing a schematic configuration of a third embodiment of the solid-state imaging device according to claim (2) of the present invention. .

FIG. 25 is used to explain each part of the CCD output waveform. In FIG. 25, T _{1 is a} reset period, T _{2 is a} feed-through period, and T ₃ is a signal period.

Also in this embodiment, the two-channel signals at the CCD output terminal are driven so as to have the same phase, and thereafter, the feed-through period of the CCD output is clamped by the common clamp pulse _PCLP to be included in the CCD output. The / f noise is suppressed, and the signal period is sampled and held using the pulse P _{S / H} , so that the reset noise generated in the feedthrough period and the signal period can be suppressed. Subsequent phase adjustment and addition methods between the two channels are exactly the same as the methods described in the second embodiment.

The method of clamping the feedthrough period and sampling and holding the signal period to suppress noise as described in this embodiment has been conventionally performed. Due to the large mutual interference with the waveform of the two-channel signal due to the phase difference of the reset pulse and the like, the waveform is deteriorated, the feedthrough period and the signal period are not clear, and the noise suppression effect cannot be clearly confirmed.

In this embodiment, by reading out the CCD output in the same phase on two channels, the waveform deterioration during the signal period is small.

In addition, the phase of the clamp pulse is common to the two channels,
Since it does not take a signal period, the signal deterioration is small, and the noise suppression effect is clearer than that of the conventional solid-state imaging device, and it has been confirmed that a high-quality image can be obtained.

Embodiment 8: FIGS. 12 and 20 are a block diagram and a timing chart of driving pulse waveforms, respectively, showing a schematic configuration of a fourth embodiment of the solid-state imaging device 30-II according to claim (2) of the present invention. It is.

In this embodiment, as in the previous embodiment, the two-channel signals are driven so as to have the same phase at the CCD output terminal. However, other examples differs in that has a reset period of the output signal since the common and .phi.H2 ₀ to φRS As seen with reference to the timing chart of FIG. 20 to 50% duty. By narrowing the pulse width of φRS than the pulse width of .phi.H2 ₀ in the above embodiment, feed-through period was always present between the reset period and the signal period, the number of pixels CCD is increased, the driving frequency is also When the height is increased, it becomes difficult to reset with a narrow pulse and secure a feedthrough period before a signal period. Also, it becomes difficult to perform the reset operation reliably in a short time even in the reset operation.

For this reason, in order to perform the reset operation reliably, the reset pulse is set to 50% duty and the widened reset part is clamped to suppress the visually noticeable 1 / f noise and improve the image quality. Is the purpose of this example.

The means for delay and addition after 1 / f noise suppression is the same as in the previous embodiment, but the processing for adding the two-channel signal after delaying OUT2 with the delay line increases the driving frequency,
When gate addition is difficult due to SP1 and SP2, a resolution substantially corresponding to the number of pixels can be obtained even by simple resistance addition.

Also in this embodiment, it is possible to obtain a high quality image in which visually noticeable 1 / f noise is suppressed.

Although the effects described above have been described for a case where the number of horizontal transfer registers is two, the effects can be applied to a plurality of horizontal transfer registers.

In each of the above embodiments, an example in which only two horizontal transfer registers are used has been described. However, a structure having three horizontal transfer registers in a CCD may be used. Even in the case of using such a three-transfer horizontal transfer register, similarly to the above-described embodiment, the signal charges transferred by the plurality of vertical transfer registers are sequentially transferred to different horizontal transfer registers by the horizontal separation gate. Alternatively, a drive pulse may be applied to the transfer electrode via the transfer electrode on the horizontal transfer register, and the signal charge may be sequentially moved to the output end.

〔The invention's effect〕

As is apparent from the above description, the present invention relates to a solid-state imaging device in which a vertical transfer register and a horizontal transfer register are configured by CCDs, and when outputs from transfer registers such as a plurality of horizontal transfer registers are also output, the same phase is obtained. , And the phase adjustment and addition after the output in the same phase are performed to produce a single time-series signal output, so that waveform deterioration due to interference between channels is greatly suppressed, and a high-quality image can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a solid-state imaging device according to claim 1 of the present invention. FIGS. 2 and 3 are element configuration diagrams of a driving circuit of the solid-state imaging device having the configuration shown in FIG. FIG. 4 is a block diagram of the reset unit, and FIG.
5 is a block diagram showing a basic configuration of the solid-state imaging device, FIG. 5 is a schematic block diagram of a first embodiment of the solid-state imaging device according to claim (1), and FIG. 6 is a solid-state imaging device according to claim (1). FIG. 7 is a schematic block diagram of a second embodiment, FIG. 7 is a schematic block diagram of a third embodiment of the solid-state imaging device of claim (1), and FIG. 8 is a fourth block of claim (1). FIG. 9 is a schematic block diagram of a solid-state image pickup device according to a first embodiment of the present invention, and FIG. 10 is a block diagram of a solid-state image pickup device according to a second embodiment of the present invention. FIG. 11 is a schematic configuration block diagram of a third embodiment of the solid-state imaging device according to claim (2), and FIG. 12 is a fourth configuration of the solid-state imaging device according to claim (2). Schematic configuration block diagram of embodiment, thirteenth
FIG. 16 to FIG. 16 show the first and second embodiments of the solid-state imaging device according to claim (1).
Timing charts of drive pulse waveforms applied to the driving of the drive circuits of the third and fourth embodiments. FIGS. 17 to 20 are first to fourth embodiments of the solid-state imaging device according to claim (2). FIG. 21 is a schematic block diagram of a conventional CCD solid-state imaging device, and FIG. 22 is an element section of a driving circuit of the CCD solid-state imaging device of FIG. 21. 23 is a schematic block diagram of the reset unit of the drive circuit of FIG. 22, FIG. 23 is a block diagram of FIG. 21, and FIG.
FIG. 25 is a timing chart of a drive pulse waveform applied to a drive circuit of the CCD solid-state imaging device. FIG. 25 is an output waveform diagram of the CCD solid-state imaging device shown in FIG. H-1, H-2 ...... horizontal transfer register (CCD) V-1, V -2, ... V-n ...... vertical transfer registers _{(CCD) PD 11, PD 12} , ..., PD n1, PD nn ...... Photodiodes H1, H2 Transfer electrodes H1 ₀ , H2 ₀ Final electrodes HG Horizontal separation gate 10 Drive circuit 11 Delay means 20 Addition means 11a DLY 11b Gate circuit 11c CLP 11d: sample-and-hold circuit 30: conventional solid-state imaging device 30-I: solid-state imaging device according to claim (1) 30-II: solid-state imaging device according to claim (2)

Claims (2)

(57) [Claims] A plurality of vertical transfer registers arranged in parallel with each other and comprising a plurality of vertical transfer registers, wherein each of the plurality of vertical transfer registers performs photoelectric conversion on a received image. In a fixed image pickup apparatus provided with a plurality of photoelectric conversion elements for transferring signal charges to a vertical transfer register, the plurality of horizontal transfer registers are formed so that outputs between respective horizontal transfer registers can be read in phase. An element, delay means for adjusting the phase relationship between the outputs of the horizontal transfer registers, and the outputs of the horizontal transfer registers after the phase relationship adjustment by the delay means are added to one time-series signal A solid-state imaging device, comprising: 2. A vertical transfer register comprising a plurality of vertical transfer registers and a horizontal transfer register which are composed of charge-coupled devices and which are vertically arranged with respect to each other. In a solid-state imaging device provided with a plurality of photoelectric conversion elements for transferring to a vertical transfer register, the plurality of horizontal transfer registers are formed so as to hold and delay the phase relationship between output signals of the respective horizontal transfer registers. An element, a delay operation stop bias setting unit for this horizontal transfer register, a driving unit for reading the output of each horizontal transfer register in phase, and a delay unit for adjusting the phase relationship between the outputs of each horizontal transfer register. Addition means is provided for adding the outputs of the respective horizontal transfer registers after adjusting the phase relationship by the delay means to form one time-series signal. And a solid-state imaging device.