JP2800753B2 - Method for manufacturing junction field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a junction field effect transistor (JFET).

[0002]

N-channel type JFET consisting Related Art For example planar initially, for example, 10 ¹⁹ cm ^-3 units n of the p ⁺ -type silicon impurity concentration of ^-3 eg 10 ¹⁶ cm on the surface of the substrate impurity concentration of Was formed on a silicon substrate having an n-on p ⁺ structure provided with a silicon epitaxial layer. A p-type guard ring diffusion region extending from the surface of the n-type silicon epitaxial layer to the p ⁺ -type silicon substrate is provided in a region excluding the element formation region on the surface of the n-type silicon epitaxial layer. P ⁺ provided in the element formation region on the surface of the silicon epitaxial layer
The gate diffusion region was connected to the p-type guard ring diffusion region (and the p ⁺ -type silicon substrate) in such a manner as to divide the element formation region. p ⁺ -type gate in the element formation region of the surface of the n-type silicon epitaxial layer separated by the diffusion region, n ⁺ -type source diffusion in the areas away from the p-type guard ring diffusion region and the p ⁺ -type gate diffusion region, respectively A region and an n ⁺ -type drain diffusion region were provided. In the JFET having this structure (the p ⁺ -type gate diffusion region does not reach the p ⁺ -type silicon substrate), the distance between the bottom surface of the p ⁺ -type gate diffusion region and the surface of the p ⁺ -type silicon substrate is determined by the channel thickness ( = D).

A JF formed on a silicon substrate having the above structure
In ET, for example, when the p ⁺ -type silicon substrate is formed of a wafer of about 4 inches, the variation of the channel thickness d calculated from the variation of the electrical characteristics is about ± 10%. The present applicant has proposed a method for reducing this variation to about ± 5%.
It was previously filed as Japanese Unexamined Patent Publication No. 63-51677 (198
August 20, 2006). Referring to FIG. 6 which is a schematic cross-sectional view of the manufacturing process of the JFET and FIG. 7 which is a diagram schematically showing the impurity profile of the manufacturing process, the JFET presented in this patent publication is formed by the following manufacturing process. You.

First, an impurity concentration N _1,3 (for example, 10 ¹⁹ c
m ⁻³ ) p ⁺ type silicon substrates 31 [FIG.
(A), FIG. 7 (a)]. An impurity concentration N _2,3 (for example, 1 × 10 ¹⁵ cm ⁻³⁾ is formed on the surface of the p ⁺ type silicon substrate 31.
) P-type silicon layer 32 is provided. The thickness of the p-type silicon layer 32 is _X1,3 [FIG. 6 (b), FIG.
(B)]. Note that the method of forming the p-type silicon layer 32 is not specified in the above patent publication.

[0005] Next, by ion implantation of an n-type impurity,
An n-type diffusion region 33 having an impurity concentration of N _3,3 (for example, about 5 × 10 ¹⁵ cm ⁻³ ) is formed in an element formation region on the surface of the type silicon layer 32. The junction depth of the n-type diffusion region 33 is X
_2,3 (<X _1,3 ). With the formation of the n-type diffusion region 33, the p-type silicon layer 32 becomes a p-type silicon layer 32aa sandwiched between the n-type diffusion region 33 and the p ⁺ -type silicon substrate 31, and a p-type guard ring (diffusion). The p-type silicon layer 32ab functions as a region [FIG. 6 (c),
FIG. 7 (c)].

After forming an insulating film 35 covering the surfaces of the p-type silicon layer 32ab and the n-type diffusion region 33, the impurity concentration is set to N _4,3 (for example, by a known photolithography technique and a known impurity introduction technique). 10 ¹⁹ cm ^-3 units), the junction depth is the p ⁺ -type gate diffusion region 36 of the X _3,3 (<X _2,3) are formed in a predetermined region of the surface of the n-type diffusion region 33. both end portions of the p ⁺ -type gate diffusion region 36 surface is connected to the p-type silicon layer 32ab surface, p ⁺ -type gate diffusion region 36 is connected to the p ⁺ -type silicon substrate 31 through the p-type silicon layer 32ab. The thickness of the channel is d = X
The _2,3 -X _3,3. Further, by the known photolithography technology and the known impurity introduction technology, the n ⁺ -type source diffusion region 37A and the n ⁺ -type drain diffusion region 37B are formed.
It is formed in a predetermined region on the surface of the n-type diffusion region 33 (each separated from the surface of the p-type silicon layer 32ab and the surface of the p ⁺ -type gate diffusion region 36). By these series of ion implantation, the n-type diffusion region 33 becomes the n-type diffusion region 33a. Subsequently, the n ⁺ type source diffusion region 37A
And an opening reaching the n ⁺ -type drain diffusion region 37B is formed in the insulating film 35, and a metal wiring connected to the n ⁺ -type source diffusion region 37A and the n ⁺ -type drain diffusion region 37B via these openings, respectively. 38A and the metal wiring 38B are formed [FIG. 6 (d), FIG.
(D)].

[0007]

According to the above-mentioned patent publication, an initial n-channel silicon substrate having an n-on p ⁺ structure in which an n-type silicon epitaxial layer is provided on the surface of a p ⁺ -type silicon substrate, for example, has an n-channel structure. On the assumption that the variation in the thickness d of the channel of the JFET is attributed to the variation in the thickness of the n-type silicon epitaxial layer, p ⁺
An n-type diffusion region 33 is formed by ion implantation on the surface of a p-type silicon layer 32 covering the surface of the type silicon substrate 31 to reduce variations in channel thickness d. Apart from the validity of the above premise (described later), J
FETs have achieved their goals as a result.

[0008] However, the JFET disclosed in the above patent publication
Then, taking an n-channel type JFET as an example, JFET
Is formed by ion implantation into the surface of the p-type silicon layer 32, the impurity concentration N _3,3 of the n-type diffusion region 33 is
(P-type silicon layer 32aa, p-type silicon layer 32ab)
Becomes higher than the impurity concentration N _2,3 of, p which is electrically connected to the p ⁺ -type silicon substrate 31 through the p-type silicon layer 32ab that functions as a p-type guard ring diffusion region
The effective gate resistance of the ⁺ type gate diffusion region 36 becomes relatively high. Therefore, a delay is likely to occur in the extension of the depletion layer from the p ⁺ -type gate diffusion region 36 side to the n-type diffusion region 33. Further, the impurity concentration N _2,3 of the p-type silicon layer 32aa (which becomes the lower gate) is extremely lower than the impurity concentration N _4,3 of the p ⁺ -type gate diffusion region 36 (which becomes the upper gate). Since the impurity concentration of the region 33 is lower than the impurity concentration N _3,3, the extension of the depletion layer from the p-type silicon layer 32aa to the n-type diffusion region 33 increases from the p ⁺ -type gate diffusion region 36 to the n-type diffusion region 33. would be suppressed as compared to the extension of the depletion layer, the result is secure design accuracy of the pinch-off voltage V _P is not easy. Furthermore, it is not easy to manufacture a JFET having a small absolute value | V _P | of the pinch-off voltage, and the degree of freedom in design is suppressed.

Accordingly, it is an object of the present invention to provide a method of manufacturing a JFET having less variation in electrical characteristics . Further object of the present invention is to ensure the flexibility and accuracy of design related to the pinch-off voltage V _P, while suppressing an increase in the gate resistance, to provide a method of manufacturing a JFET capable of reducing variations in the thickness of the channel It is in.

[0010]

[0011]

[0012]

According to a first aspect of a method of manufacturing a JFET of the present invention, a first conductive type silicon substrate having a first impurity concentration is formed on a surface of a silicon substrate having a first impurity concentration. Forming a first silicon epitaxial layer of one conductivity type having an impurity concentration of 2; and forming a third impurity concentration lower than the second impurity concentration on the surface of the first silicon epitaxial layer. Forming a second silicon epitaxial layer of the opposite conductivity type by a low-temperature epitaxial growth method; and forming the first silicon epitaxial layer in a region excluding an element formation region on the surface of the second silicon epitaxial layer. Forming a guard ring diffusion region of one conductivity type connected to the layer; and forming the first silicon epitaxial layer in a predetermined region of the element formation region. Forming a one-conductivity-type gate diffusion region having a required distance from the surface of the layer and connected to the guard ring diffusion region; and forming a gate diffusion region in the element formation region excluding the gate diffusion region. Forming source and drain diffusion regions of the opposite conductivity type.

Further, the second aspect of the method for manufacturing a JFET of the present invention is as follows.
According to an aspect of the present invention, a one-conductivity-type diffusion layer having a second impurity concentration lower than the first impurity concentration is formed on a surface of a one-conductivity-type silicon substrate having a first impurity concentration by introducing an opposite-conductivity-type impurity. Forming a reverse conductivity type silicon epitaxial layer having a third impurity concentration lower than the second impurity concentration on the surface of the one conductivity type diffusion layer;
A step of forming by a low-temperature epitaxial growth method, and a step of forming a one-conductivity-type guard ring diffusion region connected to the one-conductivity-type diffusion layer in a region excluding an element formation region on the surface of the silicon epitaxial layer. Forming a one-conductivity-type gate diffusion region in a predetermined region of the element-forming region, which has a predetermined distance from the surface of the one-conductivity-type diffusion layer and is connected to the guard ring diffusion region; Forming a source diffusion region and a drain diffusion region of the opposite conductivity type in a predetermined region of the element formation region excluding the gate diffusion region.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of embodiments of the present invention, the progress of technical studies leading to the present invention will be described. The cause of the problem of the JFET disclosed in JP-A-63-51677 is that the impurity concentration of the opposite conductivity type diffusion region is higher than the impurity concentration of the one conductivity type silicon layer.
It is difficult to form a reverse conductivity type diffusion region having an impurity concentration lower than this impurity concentration on the surface of the one conductivity type silicon layer by thermal diffusion or ion implantation. Next, the reason why the variation in the thickness of the channel can be solved in the above-mentioned patent publication (the advantage of the above-mentioned patent publication) will be considered.

At the time of filing of the above-mentioned patent publication (August 20, 1986), the silicon epitaxial layer was formed by a high-temperature epitaxial growth method (at a temperature of 1000 ° C. or more) which is presently known. Specifically, dichlorosilane (SiH ₂ Cl ₂ ), trichlorosilane (SiHC
l ₃ ) or tetrachlorosilane (SiCl ₄ )
Using hydrogen (H ₂ ) gas as the reaction and carrier
Had gas. In these high-temperature epitaxial growth methods, the growth rate of the silicon epitaxial layer is limited by the flow rate of the raw material gas, and thus the film thickness distribution within the same wafer is certainly large. for that reason,
The thickness of the reverse conductivity type silicon epitaxial layer of the silicon substrate in which the low concentration reverse conductivity type silicon epitaxial layer is provided on the surface of the original high concentration one conductivity type silicon substrate, and the high concentration one conductivity type silicon The low-concentration (higher than the one-conductivity-type silicon layer and the one-conductivity-type silicon substrate) according to the above-mentioned patent publication formed as an element formation region (by ion implantation) on the surface of the low-concentration one-conductivity-type silicon layer covering the substrate Comparing with the junction depth of the lower conductivity type diffusion region, the variation of the junction depth of the opposite conductivity type diffusion region is smaller than the variation of the thickness of the opposite conductivity type silicon epitaxial layer. Become.

According to the inventor's idea, the reduction in the variation in the channel thickness in the JFET according to the above-mentioned patent publication is not merely the superiority of the variation in the junction depth of the opposite conductivity type diffusion region during formation. In the original JFET, only the low-concentration opposite-conductivity-type silicon epitaxial layer exists between the high-concentration one-conductivity-type gate diffusion region and the high-concentration one-conductivity-type silicon substrate. On the other hand, the JFET disclosed in the above patent publication has a low-concentration reverse-conductivity-type diffusion region and a low-concentration one-conductivity-type diffusion region between a high-concentration one-conductivity-type gate diffusion region and a high-concentration one-conductivity-type silicon substrate. Mold silicon layer. Due to this structural difference, the low-concentration reverse-conductivity-type silicon epitaxial layer and the low-concentration reverse-conductivity-type diffusion region from the high-concentration one-conductivity-type silicon substrate in the heat treatment accompanying the formation of the JFET are formed. Focusing on the auto-doping of one conductivity type impurity, the auto-doping of the low-concentration reverse conductivity type diffusion region is smaller. That is, even in the heat treatment accompanying the formation of the JFET, the JFET of the above-mentioned patent publication is more advantageous with respect to the variation in the thickness of the channel.

Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1A, which is a schematic cross-sectional view of a JFET, and FIG. 1B, which schematically shows an impurity profile in the depth direction of the JFET, a first embodiment of the present invention will be described.
The JFET according to the embodiment is an n-channel type JFET.
And has the following structure.

The silicon substrate according to the first embodiment has p
⁺ -Type silicon substrate, and the p ⁺ -type silicon covering the surface of the substrate (p ⁺ -type silicon substrate than the low concentration) p-type first silicon epitaxial layer, silicon the first
An n-type second silicon epitaxial layer (having a lower concentration than the first silicon epitaxial layer) covering the surface of the epitaxial layer. Impurity concentration N
_1,1 (for example, 10 ¹⁹ cm ^-3 units) p ⁺ type silicon substrate 1
The surface of No. 1 has an impurity concentration N _2,1 (for example, on the order of 10 ¹⁷ cm ⁻³ ) which is the remaining first silicon epitaxial layer.
Is covered with the p-type silicon epitaxial layer 12a. The thickness (= X _{1a, 1} −X _2,1 ) of the p-type silicon epitaxial layer 12a is about 1 μm. The surface of the p-type silicon epitaxial layer 12a is the remaining second silicon epitaxial layer, and the impurity concentration N _3,1 (for example, 10 ¹⁶ cm ⁻³ units) serving as an element formation region.
Is covered with the n-type silicon epitaxial layer 13a. Although the details of the method of forming the n-type silicon epitaxial layer 13a will be described later, a low-temperature epitaxial growth method is preferable. Although it is related to the manufacturing method, the n-type silicon epitaxial layer 13
The thickness of a (= X _2,1 ) is about 5 μm and is formed by low-temperature epitaxial growth, so that the variation of X _2,1 at the time of completion of the JFET can be, for example, about ± 5%. It is.

The periphery of the n-type silicon epitaxial layer 13a is surrounded by a p-type guard ring diffusion region 14 having an impurity concentration of, for example, about 10 ¹⁷ cm ⁻³ . The height of the surface of the p-type guard ring diffusion region 14 and the n-type silicon
The height of the surface of the epitaxial layer 13a substantially coincides with the height of the surface. The bottom surface of the p-type guard ring diffusion region 14 reaches the p-type silicon epitaxial layer 12a, but is not limited to this, and may directly reach the surface of the p ⁺ -type silicon substrate 11. n-type silicon epitaxial layer 13a and p-type guard ring diffusion region 1
4 is covered with an insulating film 15 made of, for example, a silicon oxide film formed by thermal oxidation. On the surface of the n-type silicon epitaxial layer 13a, ap ⁺ -type gate diffusion region 16 having an impurity concentration of N _4,1 (for example, about 10 ¹⁹ cm ⁻³ ) is provided.
An n ⁺ -type source diffusion region 17A and an n ⁺ -type drain diffusion region 17B are provided. p ⁺ type gate diffusion region 1
The junction depth of 6 (= X _3,1 ) is, for example, about 2 μm, and the channel thickness d (= X _2,1 ) of the first embodiment.
−X _3,1 ) is, for example, about 3 μm. The thickness (not shown) of the insulating film 15 immediately above the p ⁺ -type gate diffusion region 16 and the like is about 1 μm, and the thickness of the insulating film 15 in other parts is about 1.5 μm. N ⁺ type source diffusion region 17
An opening reaching A and the n ⁺ type drain diffusion region 17B is provided in the insulating film 15, and the metal wiring 18A and the metal wiring 18 are formed.
B are connected to the n ⁺ -type source diffusion region 17A and the n ⁺ -type drain diffusion region 17B via these openings.

In the JFET of the first embodiment, the n-type silicon epitaxial layer 13a serving as an element formation region
The setting of the impurity concentration of p-type silicon
Since it can be performed without being restricted by the impurity concentration of the epitaxial layer 12a, it is easy to _satisfy N _3,1 <N _2,1 . It is also easy to provide the p-type guard ring diffusion region 14 having an impurity concentration higher than N _3,1 (which can be independently set for N _2,1 ). From these facts, JFET according the first embodiment, to ensure the flexibility and accuracy of design related to the pinch-off voltage V _P,
It becomes easy to suppress an increase in gate resistance. In addition,
Since the suppression of the variation in channel thickness is related to the manufacturing method, it will be described in the section of the manufacturing method described below.

FIG. 2 is a schematic cross-sectional view of a main manufacturing process of a JFET, FIG. 3 is a diagram showing an outline of an impurity profile in a depth direction in the main manufacturing process of the JFET, and FIG.
When the JFE of the first embodiment is referred to,
T is formed as follows.

First, the impurity concentration N _1,1 (for example, 10 ¹⁹ c
m ⁻³ ) p ⁺ type silicon substrates 11 are prepared [FIG.
(A), FIG. 3 (a)]. An impurity concentration of N _2,1 (for example, 10 ¹⁷ cm) is formed on the surface of the p ⁺ type silicon substrate 11.
^-3), thickness p type silicon epitaxial layer 12 of the X _{1, 1} (for example, about 1 [mu] m) is formed. The p-type silicon epitaxial layer 12 relaxes and suppresses auto-doping of p-type impurities from the p ⁺ -type silicon substrate 11 into the n-type silicon epitaxial layer formed on the surface of the p-type silicon epitaxial layer 12. Therefore, the impurity concentration and the film thickness of the p-type silicon epitaxial layer 12 are set based on the required intervals and concentration gradients required for the above. Further, since a part of the p-type silicon epitaxial layer 12 functions as a lower gate, the p-type silicon epitaxial layer 12 is formed so that the depletion layer extends toward the n-type silicon epitaxial layer without any trouble. The setting of the impurity concentration is performed. This p-type silicon epitaxial layer 12
The method of forming the p-type silicon epitaxial layer 1
Since the accuracy of the film thickness is not strict for 2, the high-temperature epitaxial growth method or the low-temperature epitaxial growth method may be used. Also, taking into account the subsequent heat treatment step in the first embodiment, the thickness of the p-type silicon epitaxial layer 12 for relaxing and suppressing the auto doping from the p ⁺ -type silicon substrate 11 is reduced. For example, about 1 μm is sufficient [FIGS. 2 (b) and 3 (b)].

Next, the p-type silicon epitaxial layer 1
On the surface of No. 2, the impurity concentration is N _3,1 (for example, on the order of 10 ¹⁶ cm ⁻³ ) and the film thickness is X by low-temperature epitaxial growth.
_2,1 (eg, about 5 μm) n-type silicon epitaxial layers 13 are formed. Here, X _1,1 = X _{1a, 1} −X
_2,1 [FIGS. 2 (c) and 3 (c)].

The low temperature epitaxial growth method uses disilane (Si ₂ H ₆ ) as a source gas and phosphine (PH ₃ ).
Is a single-wafer-type LPCVD using helium (He) gas or argon (Ar) gas as a carrier gas, and the growth temperature is about 700 ° C. suitable for mass production. Then, for example, when the p ⁺ -type silicon substrate 11 is formed of a 4-inch wafer, the thickness variation of the n-type silicon epitaxial layer 13 in the wafer is about ± 2%. At this time, if the film formation rate is lowered while ignoring mass productivity of the n-type silicon epitaxial layer 13 and the film is formed at about 650 ° C., the thickness of the n-type silicon epitaxial layer 13 in the wafer is reduced. The variation is about ± 1%. In addition, monosilane (SiH
_{When 4} ) is used as a source gas, the growth temperature is about 50 ° C. higher, but a low-temperature epitaxial growth method is possible.
The low variation in the thickness of the silicon epitaxial film in the wafer by the low-temperature epitaxial growth method is because the growth rate in this growth method is such that Si ₂ H on the wafer surface (near)
_This is because the rate is determined by the release of hydrogen from ₆ , and uniformity of the temperature distribution in the wafer during film formation becomes important.

Formation of a silicon oxide film (not shown in the figure) of a required thickness on the surface of n-type silicon epitaxial layer 13 by thermal oxidation, n-type silicon epitaxial layer 1
Etching of this silicon oxide film using a photoresist film covering a region where an element is to be formed in No. 3 at 1060 ° C.
Thermal diffusion of boron at a temperature of about 1,100 ° C., etc. are performed, and a p-type guard ring diffusion region 1 is formed.
4 are formed. At this time, the impurity concentration of the p-type guard ring diffusion region 14 is on the order of 10 ¹⁷ cm ⁻³ . The formation of the p-type guard ring diffusion region 14 leaves an n-type silicon epitaxial layer 13a to be an element formation region, and the bottom surface of the p-type guard ring diffusion region 14 leaves the remaining p-type silicon epitaxial layer. 12a.

Again, thermal oxidation or the like is performed to
An insulating film 15 made of a silicon oxide film having a thickness of about 30 nm is formed, and this silicon oxide film is etched using a photoresist film having an opening at a portion where a p ⁺ -type gate diffusion region is formed as a mask. After the resist film is removed and a silicon oxide film having a thickness of about 20 to 30 nm is formed in this opening by thermal oxidation, 50 keV, 7.
The boron ion implantation under the condition of 0 × 10 ¹⁴ cm ^{−2 and} the implantation of boron at about 1000 ° C. are performed.
For example a 10 ¹⁹ c m ^-3 units impurity concentration N _{4, 1} of, for example 2
A p ⁺ -type gate diffusion region 16 having a junction depth (X _3,1 ) of about μm is formed. Thermal oxidation is performed again,
The thickness of the insulating film 15 is 1 just above the p ⁺ -type gate diffusion region 16.
μm, and about 1.5 μm in other parts. By the same method, an n ⁺ -type source diffusion region 17A and an n ⁺ -type drain diffusion region 17B are formed, an opening reaching the insulating film is formed, and these n ⁺ -type source diffusion regions 17A and 17B are formed.
A metal wiring 18A and a metal wiring 18B connected to the A and n ⁺ type drain diffusion regions 17B, respectively, are formed (FIGS. 1A and 1B).

In the first embodiment, n-type silicon
When the variation in the thickness of the epitaxial layer 13 is about ± 2%, the channel thickness d (= X _2,1 −X
The variation in ( _3,1 ) is suppressed to about ± 5%.

In the first embodiment, N _1,1 >
If the relationship of N _2,1 > N _3,1 is satisfied, the numerical values described above are not limited. Although the first embodiment has been described using an n-channel JFET as an example, the first embodiment can be applied to a p-channel JFET.

Referring to FIG. 4 which is a schematic cross-sectional view of the manufacturing process of the JFET, and FIG. 5 which is a diagram schematically showing the impurity profile in the depth direction in the manufacturing process of the JFET.
The JFET according to the second embodiment of the present invention is also an n-channel type JFET.
The main difference between the JFET of the first embodiment and the JFET of the first embodiment lies in the structure of the silicon substrate on which the JFET is formed. The JFET according to the present embodiment is formed as follows.

First, the impurity concentration N _1,2 (for example, 10 ¹⁹ c
m ⁻³ ) p ⁺ type silicon substrates 21 are prepared [FIG.
(A), FIG. 5 (a)]. Phosphorus ion implantation or the like is performed on the surface of the p ⁺ -type silicon substrate 21 under the conditions of 50 keV and 1 × 10 ¹² cm ⁻² , and the impurity concentration is N _2,2 (for example, 10 ¹⁷ cm ⁻³ ). The junction depth is X _1,2 (for example, 1 μm
) P-type diffusion layer 29 is formed. This gives p ⁺
The type silicon substrate 21 becomes the p ⁺ type silicon substrate 21a (FIGS. 4B and 5B).

Next, on the surface of the p-type diffusion layer 29, an impurity concentration of N _3,2 (for example, on the order of 10 ¹⁶ cm ⁻³ ) and a film thickness is formed by the same low-temperature epitaxial growth method as in the first embodiment. Is formed, and an n-type silicon epitaxial layer 23 of X _2,2 (for example, about 5 μm) is formed, and the formation of the silicon substrate of the second embodiment is completed. Here, X _1,2 = X _{1a, 2}
−X _2,2 [FIGS. 4 (c) and 5 (c)].

Formation of a silicon oxide film (not explicitly shown) of a required thickness on the surface of n-type silicon epitaxial layer 23 by thermal oxidation, n-type silicon epitaxial layer 2
The p-type guard ring diffusion region 24 is formed by etching the silicon oxide film using the photoresist film covering the region where the device is to be formed as a mask, and performing thermal diffusion and indentation of boron. At this time, the impurity concentration of the p-type guard ring diffusion region 24 is on the order of 10 ¹⁷ cm ⁻³ . By forming the p-type guard ring diffusion region 24, the n-type silicon epitaxial layer 2 which becomes an element formation region
3a is left, and the bottom surface of the p-type guard ring diffusion region 24 is connected to the remaining p-type diffusion layer 29a.

Again, thermal oxidation or the like is performed to
An insulating film 25 made of a silicon oxide film having a film thickness of about 30 nm is formed, and the silicon oxide film is etched using a photoresist film having an opening at a portion where a p ⁺ -type gate diffusion region is formed as a mask. After the resist film is removed and a silicon oxide film having a thickness of about 20 to 30 nm is formed in this opening by thermal oxidation, 50 keV, 7.
The boron ion implantation under the condition of 0 × 10 ¹⁴ cm ^{−2 and} the implantation of boron at about 1000 ° C. are performed.
For example a 10 ¹⁹ c m ^-3 units of the impurity concentration N _{4, 2,} for example 2
A p ⁺ -type gate diffusion region 26 having a junction depth (X _3,2 ) of about μm is formed. Thermal oxidation is performed again,
The thickness of the insulating film 25 is 1 immediately above the p ⁺ type gate diffusion region 26.
μm, and about 1.5 μm in other parts. In the same manner, an n ⁺ -type source diffusion region 27A and an n ⁺ -type drain diffusion region 27B are formed, an opening reaching the insulating film is formed, and these n ⁺ -type source diffusion regions 27A and 27B are formed.
A metal wiring 28A and a metal wiring 28B connected to the A and n ⁺ -type drain diffusion regions 27B, respectively, are formed (FIGS. 4D and 5D).

The second embodiment has the effects of the first embodiment, and the second embodiment has a silicon substrate compared to the first embodiment. Easy to form.

Also in the second embodiment,
The numerical values are not limited as long as the relationship of N _1,2 > N _2,2 > N _3,2 is satisfied. Although the second embodiment has been described by taking an n-channel JFET as an example, the second embodiment
Can be applied to a p-channel JFET.

[0037]

As described above, the JFET of the present invention is
Is a high-concentration one-conductivity-type silicon substrate, a low-concentration one-conductivity-type silicon layer laminated on the silicon substrate, and a lower-concentration opposite-conductivity-type silicon layer laminated on the one-conductivity-type silicon layer. It is provided on a silicon substrate composed of a silicon layer. Further, the silicon layer of the opposite conductivity type is formed by a low-temperature epitaxial growth method. Furthermore, the JFET of the present invention has a required impurity concentration, and has a one-conductivity-type guard ring diffusion region that reaches at least one-conductivity-type silicon layer from the surface of the opposite-conductivity-type silicon layer.

With such a structure and a manufacturing method, the JFET of the present invention reduces variation in electric characteristics , furthermore, secures the degree of freedom and accuracy of design related to pinch-off voltage and suppresses an increase in gate resistance. In addition, it becomes easy to reduce the variation in the thickness of the channel.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a JFET according to a first embodiment of the present invention and a diagram showing an outline of an impurity profile.

FIG. 2 is a schematic cross-sectional view of a main manufacturing process of the first embodiment.

FIG. 3 is a diagram showing an outline of an impurity profile in a main manufacturing process of the first embodiment.

FIG. 4 is a schematic cross-sectional view of a manufacturing step of a JFET according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an outline of an impurity profile in a manufacturing process according to the second embodiment.

FIG. 6 is a schematic cross-sectional view of a conventional JFET manufacturing process.

FIG. 7 is a diagram showing an outline of an impurity profile in a manufacturing process of the conventional JFET.

[Explanation of symbols]

11, 21, 21a, 31 p ⁺ type silicon substrate 12, 12a p-type silicon epitaxial layer 13, 13a, 23, 23a n-type silicon epitaxial layer 14, 24 p-type guard ring diffusion region 15, 25, 35 Insulation Films 16, 26, 36 p ⁺ -type gate diffusion regions 17A, 27A, 37A n ⁺ -type source diffusion regions 17B, 27B, 37B n ⁺ -type drain diffusion regions 18A, 18B, 28A, 28B, 38A, 38B
Metal wiring 29, 29a p-type diffusion layer 32, 32aa, 32ab p-type silicon layer 33, 33an n-type diffusion region

Claims (2)

(57) [Claims] A first conductivity type silicon epitaxial layer having a second impurity concentration lower than the first impurity concentration on a surface of a one conductivity type silicon substrate having a first impurity concentration; Forming a second conductivity type second silicon epitaxial layer having a third impurity concentration lower than the second impurity concentration on the surface of the first silicon epitaxial layer by a low-temperature epitaxial growth method. Forming a one-conductivity type guard ring diffusion region connected to the first silicon epitaxial layer in a region excluding an element formation region on the surface of the second silicon epitaxial layer. A predetermined region of the element formation region has a required distance from the surface of the first silicon epitaxial layer, and the guard ring diffusion region has Forming a one conductivity type gate diffusion region to be connected; and forming a reverse conductivity type source diffusion region and a drain diffusion region in a predetermined region excluding the gate diffusion region in the element formation region. A method for manufacturing a junction type field effect transistor, comprising: 2. A method according to claim 1, wherein the first conductivity type silicon substrate having a first impurity concentration has a second conductivity lower than the first impurity concentration.
Forming a one-conductivity-type diffused layer having an impurity concentration of: by introducing an opposite-conductivity-type impurity; and having a third impurity concentration lower than the second impurity concentration on a surface of the one-conductivity-type diffusion layer. Forming a silicon epitaxial layer of the opposite conductivity type by a low-temperature epitaxial growth method; and, in a region excluding an element forming region on the surface of the silicon epitaxial layer, a one conductivity type connected to the one conductivity type diffusion layer. A step of forming a guard ring diffusion region; and a step of forming a guard ring diffusion region in a predetermined region of the element formation region, having a required distance from the surface of the one conductivity type diffusion layer and being connected to the guard ring diffusion region. Forming a gate diffusion region, and forming a source diffusion region and a drain diffusion region of a reverse conductivity type in a predetermined region of the element formation region excluding the gate diffusion region. And a method of manufacturing a junction field-effect transistor.