JP2802143B2 - Bit synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of transmitting data serially between two devices, the frequency of a bit synchronization signal in a transmitting device and the frequency of a bit synchronization signal in a receiving device. If the data is different, it is applied to the bit synchronization circuit that outputs the received data in synchronization with the bit synchronization signal of the receiving device, eliminating the need to narrow the data width of one bit in particular, and causing the received signal to lose synchronization. In this case, the present invention relates to a bit synchronization circuit suitable for preventing output of erroneous data and recovering the above-mentioned loss of synchronization.

[Conventional technology]

In the prior art, as disclosed in Japanese Patent Application Laid-Open No. 63-100844, an excess or deficiency of data caused by a change in an upstream transmission station is absorbed by a FIFO memory, and information read from the FIFO memory is read. And detects the end flag (frame synchronization bit) included in the
The FIFO memory was reset.

[Problems to be solved by the invention]

In the related art described above, it is necessary to detect the end flag read from the FIFO memory. But,
The end flag is not information necessary as data on the read side. If the end flag is inserted as data at a fixed frame interval, it is necessary to increase the frequency of the bit synchronization signal by that amount, and the data width of one bit becomes narrow. There was a problem of becoming.

Further, in the above-described related art, there is a problem that, when synchronization is lost and data read timing from the FIFO memory is shifted, erroneous data is output.

The present invention has been made in view of the above-described problems of the related art, and does not reduce the data width of 1 bit, and when losing synchronization occurs, prevents erroneous data from being read from the FIFO memory, It is an object of the present invention to provide a bit synchronization circuit capable of recovering from the above-mentioned loss of synchronization.

[Means for solving the problem]

The bit synchronization circuit of the present invention stores the data serially transmitted from the partner device in the FIFO memory of the own device and reads out the data from the FIFO memory at a timing synchronized with the bit synchronization signal of the own device. And a synchronizing signal extracting circuit for forming and outputting a bit synchronizing signal synchronized with the data and a frame synchronizing signal synchronized with the frame of the data, and counting the bit synchronizing signal. The pseudo-frame synchronization signal generating circuit that outputs the pseudo-frame synchronization signal over the period until the counting is completed, and the above-mentioned frame synchronization signal and the pseudo-frame synchronization signal are compared. A memory and a reset signal generation circuit for outputting to the pseudo frame synchronization signal generation circuit. .

[Action]

According to the present invention, a frame synchronization signal formed from input data is compared with a pseudo frame synchronization signal formed from a bit synchronization signal. If they do not match, it is determined that synchronization has been lost, and the FIFO memory is reset.

That is, according to the present invention, since it is not necessary to store and read the end flag in the FIFO memory, it is not necessary to reduce the data width of one bit. Further, when an out-of-synchronization occurs, the FIFO memory is reset, so that erroneous data can be prevented from being read from the FIFO memory, and the out-of-synchronization can be automatically recovered.

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to examples shown in the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, which comprises a FIFO memory 1, a synchronization signal extraction circuit 2, a pseudo frame synchronization signal generation circuit 3, and a reset signal generation circuit 4. . The bit synchronization circuit of this embodiment converts the input data 5 transmitted at the transmission timing determined by the partner station into data 10 at a timing synchronized with the bit synchronization signal 11 of the own station, and outputs the data. That is, the FIFO memory 1 functions to adjust the excess / deficiency of input / output data due to the bit synchronization difference between the partner station and the own station.

FIG. 2 is a time chart showing an example of the operation of the embodiment shown in FIG. 1. The operation of the embodiment shown in FIG. 1 will be described below with reference to FIG. As shown in FIG. 1, the input data 5 is input to and stored in the FIFO memory 1 and is also input to the synchronization signal extraction circuit 2. The synchronization signal extraction circuit 2 includes a PLL circuit and the like, and extracts a bit synchronization signal 6 from input data. That is, in the example shown in FIG. 2, the input data 6 is composed of data a to h, and after the data h, a frame synchronization bit E indicating that the input data 5 is completed is added. The synchronizing signal extracting circuit 2 receives the input data 5, forms and outputs a bit synchronizing signal 6 synchronized with the data a to h, raises a frame synchronizing signal 7 in synchronism with the input data a, The frame synchronization signal 7 falls in synchronism with.

Bit synchronization signal 6 output from synchronization signal extraction circuit 2
Is input to the pseudo frame synchronization signal generating circuit 3 and the FIFO memory 1. Among these, the bit synchronization signal 6 input to the FIFO memory 1 is used as a clock of the input side port of the FIFO memory 1, thereby designating the timing of taking in the input data 5. The pseudo frame synchronization signal generating circuit 3 receives the input bit synchronization signal 6 and forms and outputs a pseudo frame synchronization signal 8. The pseudo frame synchronizing signal generating circuit 3 previously confirms the number of bits constituting one frame of the input data (8 bits in the example of FIG. 2), and synchronizes the pseudo frame synchronizing signal 8 with the first bit synchronizing signal. Is raised, and the pseudo frame synchronization signal 8 falls when the bit synchronization signal 6 is inputted for a predetermined number of bits.

The reset signal generation circuit 4 is composed of an exclusive OR circuit or the like, and compares the frame synchronization signal 7 output from the synchronization signal extraction circuit 2 with the pseudo frame synchronization signal 8 output from the pseudo frame synchronization signal generation circuit 3. However, when both match, it is determined that the circuit is normal and does not output the reset signal 9, and only when the two do not match is determined to be abnormal and outputs the reset signal 9. FIG. 2 shows an example in which the frame synchronization signal 7 and the pseudo frame synchronization signal 8 completely match, and the reset signal generation circuit 4 does not output the reset signal 9. In this case, as shown in the figure, the input data 5 (data a to h) stored in the FIFO memory 1 at the timing of the bit synchronization signal 6
The data is read as output data 10 at a timing synchronized with 11. That is, the reset signal generation circuit 4 detects whether or not the input data (frame) is out of synchronization.
And resets the FIFO memory 1 and the pseudo frame synchronization signal generating circuit 3.

FIGS. 3 and 4 show a comparison between the frame synchronization signal 7 output from the synchronization signal extraction circuit 2 and the pseudo frame synchronization signal 8 output from the pseudo frame synchronization signal generation circuit 3, and they are inconsistent. , Is determined to be out of synchronization, and the reset signal 9 is output.

FIG. 3 shows a case where the bit synchronizing signal 6 formed in the synchronizing signal extracting circuit 2 is missing (one bit), and as a result, the pseudo frame synchronizing signal 8 becomes longer.
In this case, the pseudo frame synchronization signal generation circuit 3 is reset by the reset signal 9 output from the reset signal generation circuit 4, and as a result, the pseudo frame synchronization signal 8 falls.

FIG. 4 shows a case where the bit synchronization signal 6 formed in the synchronization signal extraction circuit 2 is larger by one bit. As a result, the pseudo frame synchronization signal 8 falls not at the timing of the data h but at the timing of the data g. (When the pseudo frame synchronization signal 8 is shortened).

As shown in FIGS. 3 and 4, when the number of bit synchronization signals 6 in one frame is different from the specified value, comparing the frame synchronization signal 7 with the pseudo frame synchronization signal 8, the falling timings of both signals are compared. Will be different. In this embodiment,
The difference between the falling timings is detected by the reset signal generation circuit 4, and a reset signal 9 is output to the FIFO memory 1. The reset signal 9 is output until the input signal from the partner station is received again.
The FO memory 1 is held in a reset state. This prevents erroneous data from being output as the output data 10 from the FIFO memory 1.

3 and 4, when the next input data 5 is input from the partner station, the synchronization signal extraction circuit 2 outputs a reset signal 9 and resets the lit signal generation circuit 4.
As a result, the reset signal generation circuit 4 causes the reset signal 9 to fall. Therefore, the reset state of the FIFO memory 1 is released, and the storage of the next input data 5 is started.

〔The invention's effect〕

According to the present invention, it is possible to prevent erroneous data from being read from the FIFO memory when the out-of-synchronization occurs without reducing the data width of one bit, and to recover the out-of-synchronism. A synchronization circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a bit synchronization circuit according to the present invention, and FIGS. 2, 3, and 4 are time charts showing an operation example of the embodiment shown in FIG. 1 ... FIFO memory, 2 ... Synchronous signal extraction circuit, 3 ... Pseudo frame synchronization signal generation circuit, 4 ... Reset signal generation circuit.

Claims (1)

(57) [Claims] 1. A bit synchronization circuit for storing data serially transmitted from a partner device in a FIFO memory of the device and reading the data from the FIFO memory at a timing synchronized with a bit synchronization signal of the device. A synchronization signal extraction circuit that forms and outputs a bit synchronization signal synchronized with the data and a frame synchronization signal synchronized with the frame of the data, and counts the bit synchronization signal, and counts a predetermined number of bits from the start of counting. A pseudo-frame synchronization signal generating circuit that outputs a pseudo-frame synchronization signal over the period up to the end is compared with the above-described frame synchronization signal and the pseudo-frame synchronization signal. A reset signal generation circuit for outputting to the frame synchronization signal generation circuit. Period circuit.