JP2803555B2 - Fabrication method of ultra-fine tunnel barrier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a tunnel barrier and a single electron tunnel transistor.

[0002]

2. Description of the Related Art A tunnel element is an element utilizing the effect of transmitting (tunneling) a potential barrier that cannot be classically passed due to the wave property of electrons. When electrons can tunnel through a potential barrier, this barrier is particularly called a tunnel barrier.

In order to form a fine planar potential barrier, 1) a negative voltage is applied to a Schottky gate electrode provided on a semiconductor surface having a two-dimensional electron gas to deplete the two-dimensional electron gas below the gate. 2) a method of forming a potential barrier by injecting specific ions into a compound semiconductor using a focused ion beam device and changing the composition and defect concentration, and 3) a molecular beam A potential barrier is formed by a selective growth method on a processed substrate by utilizing the fact that the growth control in the direction perpendicular to the semiconductor substrate is performed with an accuracy of one atomic layer unit by the epitaxial growth method and the metal organic chemical vapor deposition method. There are methods.

In method 1, the distance from the substrate surface to the two-dimensional electron gas (usually 600 A (angstrom) or more)
It is possible to produce a fine structure up to the order of magnitude, and quantum dots with a diameter of about 1000 A have been produced (N.C. van der Vaart et a.
l. ), Physica B, No. 18,
9, 99, 1993).

In method 2, there is an example in which a potential barrier is prepared by depleting a two-dimensional electron gas using a focused ion beam apparatus (Fujisawa et al., 54th Annual Conference of the Japan Society of Applied Physics, 28pZX10, 1993) ). The size of the created potential barrier is limited by the beam diameter of the focused ion beam, and is currently 100
A barrier up to about 0A can be made.

However, when the methods 1 and 2 are used, it is difficult to produce a structure of 1000 A or less, and the method 3 is promising for producing a finer structure, and various methods have been proposed. ing. As a typical example, when epitaxially growing on a substrate crystal that has been subjected to grating processing in advance, utilizing the anisotropy of the growth rate,
There is a method in which a fine structure is formed according to the growth rate, and a quantum wire laser (JA Rubens et al. (JA) et al.
Lebens et al. ), Applied Physics L (Applied Physics L)
, 56, 2642, 1990).
Or 5 on the grating by metalorganic chemical vapor deposition.
Example of forming a quantum wire array having a crescent-shaped cross section with a width of 00A (E. Colas et al.
l. ), Applied Physics Letter (App)
ledPhysics Letter), Vol. 57,
914, 1990). There is also a method in which an opening is provided on a substrate covered with a silicon oxide film or the like, and a semiconductor is grown only in the opening by metal organic chemical vapor deposition. The application field of the device manufactured by the method 3 is aimed at a quantum dot laser or a quantum wire laser, and no device is manufactured using the tunnel effect. The lack of a tunnel barrier in Method 3 is due to the difficulty in controlling the width of the barrier so that electrons can tunnel.

[0007]

The degree of integration of MOS transistors and FETs, which are basic elements at present, is increasing at a rate of less than twice a year with the progress of fine processing technology.
However, when the transistor is miniaturized, the impurity concentration in the structure must be increased and the operating voltage must be reduced. However, when the impurity concentration is increased, avalanche destruction and tunneling occur, and when the operating voltage is reduced, the current cannot be cut off at the time of off due to leakage current. Due to such physical problems, integration has a limit. To date, technical limits have governed the degree of integration, but in the future such physical limitations are expected to govern the degree of integration.

[0008] On the contrary, by actively utilizing the tunnel phenomenon,
Attempts to construct devices have been actively made.
Fabrication of a fine tunnel barrier is indispensable for miniaturization of a tunnel element in the future.

In particular, for a single-electron transistor,
A fine tunnel barrier is an important factor that determines operating conditions. The operation of a single-electron transistor requires that the single-electron charging energy exceed the thermal perturbation energy. For this reason, method 1 or method 2 described in the prior art
The single-electron transistor manufactured by the company operates only in a very low temperature (1 K or less) environment. However, since the single-electron charging energy can be increased by reducing the capacitance of the tunnel junction, if the junction area of the tunnel junction is reduced as much as possible, it is possible to operate in a low-temperature environment (77 K) that can be easily created. It is possible. Further, when a potential barrier is created by the Schottky gate electrode in Method 1, the height of the barrier must be controlled by the gate voltage, and it is extremely difficult to fabricate a large number of elements at the same time. An example in which a single-electron transistor is formed by the method 3 has been described in the prior art, and no report has been made yet.

An object of the present invention is to provide a method for fabricating an ultrafine tunnel barrier and a single electron transistor in order to solve such problems.

[0011]

According to the present invention, a fine step is formed on a semiconductor semi-insulating substrate by low damage etching, and a semiconductor semi-insulating layer, The epitaxial growth of the doping layer and the semiconductor semi-insulating layer is performed in order, so that a monoatomic doping layer is not formed on the step barrier, and then the etching is performed to form a thin line in a direction intersecting the step with the epitaxial growth layer, thereby forming the step. A method of forming an ultra-fine tunnel barrier in a portion, wherein the fine step is
This is a method for producing an ultrafine tunnel barrier, characterized in that the wave functions of electrons from the upper and lower monoatomic doping layers do not overlap and the height is such that electron tunneling occurs.

In addition, a plurality of tunnel barriers are simultaneously formed by using a substrate subjected to low damage etching in a concave or convex shape in place of the stepped substrate, and furthermore, an electrostatic potential in a region surrounded by a plurality of tunnel junctions. Is provided in the vicinity of the region to control a single electron tunneling transistor.

[0013]

The conductive layer is formed by single atom doping.
The action of the steep potential caused by the positive ions of the single-atom dopant forms a single-mode two-dimensional electron gas whose spread in the direction perpendicular to the substrate is on the order of several nm (Taniguchi et al., H. Taniguchi et al. ), Japanese Journal of Applied Physics (Japanese Journal of Appl. Physics)
ied Physics), Vol. 29, p. 2321, 1
990). Further, by doping at a high concentration, a high electron concentration can be realized and the electrostatic shielding distance can be reduced. It has been reported that when the electron concentration is 1 × 10 ¹³ / cm ² , the length of the depletion layer from vacuum can be reduced to about 500 A (Taniguchi et al., H. Taniguchi et al.
l. ), Japanese Journal of Applied Physics (Japanese Journal of Applied Physics)
of Applied Physics), No. 29
Vol., P. 2321, 1990). When processed into a fine wire, an effective line width (the width of the conductive layer) faithful to the processed line width can be obtained. For example, if a thin line having an effective line width of 100 A is to be produced, a thin line having a width of about 1100 A may be produced.

The tunnel barrier is manufactured by providing a step on the substrate. Monoatomic doping is performed by molecular beam epitaxy (MBE) on a substrate provided with a vertical or near-inclination angle or a step having a reverse taper shape. MB
In E, the molecular beam flies from a direction almost perpendicular to the substrate, so that the wall surface of the step is shaded and doping does not occur.
A region where no two-dimensional electron gas exists is generated. By such modulation doping, the conduction band of the semiconductor becomes as shown in FIG. 1, and a potential barrier can be formed. By adjusting the depth of the step, the distance between two-dimensional electrons can be changed, and the tunnel probability can be controlled.

When a thin wire is formed in a direction intersecting the step,
The area of the tunnel junction can be reduced. It is obvious that the area can be minimized in the vertical case. According to the present invention, the distance d between two-dimensional electrons is 50A, and the area S is 20A.
A junction of about × 100 A can be manufactured, and the capacitance C of this junction can be estimated as C = 0.42 aF from C = εS / d. Here, ε used the dielectric constant of the gallium arsenide substrate. Electrostatic energy E the bonding one electron is changed when the tunnel because it is ^{E = e 2 / C, E} = 0.38eV next, which corresponds to the energy of about 400K in terms of temperature. Where e
Is the elementary charge of an electron. This means that operating in a low temperature environment (77K) that can be easily created leads to the realization of a single-electron transistor.

By using a gallium arsenide substrate as a semiconductor semi-insulating substrate and using silicon as a monoatomic doping material, valence electrons can be stably supplied even at a low temperature. This is because the activation energy when silicon is used as a dopant forms a shallow donor level of 5.8 meV.

[0017]

2 (a) to 2 (c) are views showing an embodiment of the first aspect of the present invention. As a semiconductor semi-insulating substrate (10
0) A gallium arsenide (GaAs) substrate having a plane orientation is used, and silicon is used as a dopant for monoatomic doping.

First, on a gallium arsenide semi-insulating substrate 20, 5
A vertical step of 0A is formed by low damage etching (FIG. 2A).

Next, using a MBE method, a non-doped gallium arsenide layer, a monoatomic silicon doping layer,
Epitaxial growth of a non-doped gallium arsenide layer is performed in order (FIG. 2B).

Next, the epitaxial growth layer is etched to form a thin line extending in the direction perpendicular to the step (FIG. 2).
(C)).

The method for forming the steps will be described in detail. First, a resist is applied to a substrate, and exposure is performed by an electron beam drawing apparatus. Anisotropic etching is performed using the pattern-transferred resist as a mask. Low damage etching enables anisotropic etching without damaging the substrate by using electron beam assisted etching or low energy ion etching.

The conditions for performing electron beam assisted etching are as follows: electrons in electron cyclotron resonance (ECR) plasma are accelerated at 60 eV, collected on a substrate biased to 50 V, and a partial pressure of 1 × 10 ⁻⁴ Torr. Irradiate chlorine near the substrate (H. Watanabe et al., Applied Physics Letter, Appl. Phys.
Lett. ), 63, 1516, 1993).
This allows an etch rate of 14 nm / min and low damage etching.

When using low energy ion etching, the following conditions were set. CCl ₂ F ₂ (carbon fluorinated chloride) and Ar (argon) are used as a source gas at a ratio of 1: 1 using low energy ECR plasma of 200 eV. The etching rate at this time was 10 nm / min.

The tunnel probability is determined by the height of the step thus formed. If the width of the potential barrier is too large, electron tunneling does not occur. Conversely, if the width is too small, the overlap of the electron wave functions becomes large, and a tunnel junction is not formed. When a metal oxide film is used for the potential barrier, the tunnel probability changes sensitively to a small change in the thickness of the oxide film because the potential barrier is high. On the other hand, when modulation doping is used for the potential barrier as in the present invention, the height of the barrier is low and the interval between the potential barriers can be increased. Therefore,
A desired tunnel probability can be obtained with good control. The large gap between the potential barriers has a feature that the capacitance of the tunnel junction can be reduced as described in the section of (action). In the present invention, the angle of the step, the controllability of the height, the coverage of the film near the side wall during MBE growth, and the like affect the tunnel probability instead of the conventional change in the thickness of the oxide film. Since the tunnel barrier is lower than the oxide film, the controllability of the tunnel probability is good even if the controllability of the thickness of the oxide film is worse.

Next, the epitaxial growth method will be described in detail. After the low damage etching, baking is sufficiently performed in a molecular beam epitaxy apparatus to clean the etched surface. Baking is performed in a high vacuum, for example, 1 × 1
At ^0-8 Torr, the GaAs substrate is heated to 650.degree.
The oxide film on the substrate surface is removed.

Next, as shown in FIG.
Non-doped gallium arsenide layer 23, having an electron concentration of 1 × 10
¹³ / cm ² monoatomic silicon doping layer 22, thickness 2
Crystal growth is performed in the order of the non-doped gallium arsenide layer 21 of 00A. When the non-doped gallium arsenide layer 21 is grown, it is necessary to prevent the silicon dopant from diffusing into this layer. If the substrate temperature is set to 430 ° C. or lower, the diffusion is relatively small, and steep doping is possible. is there. The MBE growth condition is such that the GaAs growth rate is 1.0 μm.
m / h, flux of silicon is 5.8 × 1 per minute
0 ¹² / cm ² (The temperature of the silicon cell at this time is 130
0 ° C). In the case of monoatomic layer doping, As
While irradiating the flux, the shutter of the silicon cell is opened for 10 minutes. Under these conditions, a density of 1.0 × 10
A carrier layer of ¹³ / cm ² and a spread of 3.1 nm in the growth direction is obtained.

Finally, the processing of fine lines is the same as the method of forming an etching pattern on a substrate. First,
A resist is applied to the substrate, and the pattern is transferred by exposure using an electron beam lithography system, and anisotropic etching is performed using the pattern as a mask. As the low damage etching, anisotropic etching can be performed without damaging the substrate by using the above-described electron beam assisted etching or low energy ion etching. The width of the thin line is about 1100 A, which is the size obtained by adding the depletion layer width (500 A) on both sides to the desired thin line width (100 A).

By the above procedure, a thin wire having an extremely fine tunnel junction 24 formed at a step as shown in FIG. 2C can be manufactured.

Next, a method for manufacturing a single electron transistor according to claim 2 will be described with reference to FIG.

First, on a gallium arsenide semi-insulating substrate 27,
A concave or convex vertical step 26 having a depth of 50A is formed by low damage etching (FIG. 3A).

Next, using the MBE method, a thickness of 50
A non-doped gallium arsenide layer 30 having an electron concentration of 1 × 1
Epitaxial growth of a mono-atom silicon doped layer 29 of 0 ¹³ / cm ^{2 and} a non-doped gallium arsenide layer 28 of 200 A thickness is performed in order (FIG. 3B). How to make steps,
The method of determining the height of the step and the method of epitaxial growth are the same as in the embodiment of FIG. Next, a thin line and a gate electrode are formed on the growth substrate by the above-described electron beam assisted etching or low energy ion etching by etching in a direction perpendicular to the step to form a single electron transistor (FIG. 3C). Gate electrode 31 and tunnel junctions 32, 33
Are separated by 1 μm. When viewed in plan, the gate electrode 31 and the thin line have a shape in which the vertical and horizontal bars of the letter "T" are slightly separated as shown in FIG. 3D.

With the above procedure, a single electron transistor as shown in FIG.

2 and 3, gallium arsenide is used as the semiconductor material and silicon is used as the dopant, but the semiconductor material is InP, AlGaAs, GaP, InP.
As, AlInAs, GaAsP or the like may be used, and the dopant may be Be, C, Se, or the like.

[0034]

The fabrication of an ultra-fine tunnel barrier is indispensable for the future miniaturization of tunnel elements. In particular, for a single-electron transistor, a fine tunnel barrier is an important factor that determines operating conditions, and operates in a low-temperature environment (77 K) that can be easily created by using the present invention.

[Brief description of the drawings]

FIG. 1 is a band diagram of an ultrafine tunnel barrier formed by modulation doping.

FIG. 2 is a diagram showing a procedure for manufacturing an ultrafine tunnel barrier of the present invention.

FIG. 3 is a diagram showing a procedure for manufacturing a single-electron transistor of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 01 potential barrier 02 Fermi surface 03 conduction band 19 step 24, 32, 33 tunnel junction 25 thin wire 26 concave step 31 gate electrode 20, 27 gallium arsenide substrate 21, 28, 23, 30 non-doped gallium arsenide layer 22, 29 monoatomic silicon Doped layer

Claims (3)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor semi-insulating substrate having fine steps formed by low damage etching on a semiconductor semi-insulating substrate; and a semiconductor semi-insulating layer, a single atom doping layer, and a semiconductor semi-insulating layer formed on the substrate by molecular beam epitaxy. Epitaxial growth is performed in order to prevent a monoatomic doping layer from being formed on the side wall of the step, and then etching is performed to form a thin line in the direction intersecting the step with the epitaxial growth layer, thereby forming an extremely fine tunnel barrier at the step. An ultra-fine tunnel, characterized in that the minute steps are so high that the wave functions of electrons from the upper and lower monoatomic doping layers do not overlap and that electron tunneling occurs. How to make barriers. 2. A plurality of tunnel barriers are simultaneously formed by using a substrate subjected to low damage etching in a concave or convex shape in place of the step substrate used in claim 1.
A method for manufacturing a single-electron tunnel transistor, comprising: providing a gate electrode for controlling an electrostatic potential in a region surrounded by a plurality of tunnel junctions in the vicinity of the region. 3. The method according to claim 1, wherein a gallium arsenide substrate is used as the semiconductor semi-insulating substrate, and silicon is used as a dopant for monoatomic doping.