JP2803676B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a multilayer wiring of a semiconductor device. A step of forming an insulating film having a contact hole on a silicon layer, and forming a rhenium layer or zirconium on the surface of the silicon layer in the contact hole with the object of forming a multilayer wiring with improved contact characteristics. Selectively forming a layer by a chemical vapor deposition method; and selectively forming a conductor layer on the rhenium layer or the zirconium layer by a chemical vapor deposition method, thereby forming the conductor layer in the contact hole. And an embedding step.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a multilayer wiring of a semiconductor device.

[Conventional technology]

In a semiconductor device, particularly ULSI, a multilayer wiring is, for example, a contact hole of an insulating layer formed on a silicon substrate.
In order to prevent interfacial solid-state reaction in Al-Si, so-called erosion, a Ti / TiN layer or Ti / TiW layer is formed on a silicon layer by PVD (sputter deposition, etc.), and then an Al wiring layer is formed by CVD. It is formed by a method of forming by a method or a method of selectively growing a W layer directly on the contact hole of the insulating layer by a CVD method to improve the adhesiveness, and then forming an Al wiring layer.

[Problems to be solved by the invention]

In the method of forming the Ti / TiN layer as a barrier layer on a silicon layer, silicidation is required, and Ti-
Junction is destroyed by abnormal reaction between Si,
Also, TiN has a high contact resistance, and as the size of the device becomes smaller, it adversely affects device characteristics.

Next, the W layer is selectively grown directly on the silicon layer by the CVD method, and then the Al layer is grown by the CVD method. The W layer acts as a barrier layer between the silicon layer and the Al layer, and the W layer forms a groove in the contact hole. Although there are advantages such as being useful for filling and flattening to some extent, the Si reduction method, which is a method of growing a thin film of W, has a low temperature, for example, about 300 ° C., although the degree of erosion against silicon increases as the growth temperature increases. The adhesion strength with the substrate is weakened.

Further, the H ₂ reduction reaction as a method for increasing the thickness of W is preferably performed at a high temperature, for example, about 500 ° C., and the SiH ₄ (silane) reduction method may be performed at a low temperature of about 300 ° C.
Formed in the layer.

Furthermore, the reactivity of WF ₆ and Si, which are generally used, and chemical reaction are high, and if they are directly reacted with the Si substrate, the junction is likely to be broken with great erosion.

SUMMARY OF THE INVENTION An object of the present invention is to form a multilayer wiring having a constant growth temperature, no erosion on a substrate, an improved adhesion strength, and improved contact characteristics.

[Means for solving the problem]

The above-mentioned problems can be solved by a method of manufacturing a semiconductor device according to the present invention, which will be described in detail below.

In one aspect of the present invention, a step of forming an insulating film having a contact hole on a silicon layer, and forming a rhenium layer or a zirconium layer on the surface of the silicon layer in the contact hole by chemical vapor deposition Selectively forming a conductive layer on the rhenium layer or zirconium layer by a chemical vapor deposition method, and filling the contact hole with the conductive layer. And a method of manufacturing a semiconductor device.

In another aspect, the present invention provides a method for selectively forming a rhenium layer or a zirconium layer on a semiconductor or a conductor by a chemical vapor deposition method, and forming a tungsten layer on the rhenium or zirconium layer. And a method for manufacturing a semiconductor device.

(Operation)

According to the present invention, Re, Zr and the like can be sufficiently grown even at a low temperature (about 300 ° C.), and can be formed on a semiconductor surface such as silicon and other conductive layers with good adhesion. Re, Zr used in the present invention
Alternatively, it is due to a common property such as Ta.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1A to 1B are process sectional views for explaining a first embodiment of the present invention.

As shown in FIG. 1A, a SiO ₂ film 2 is formed on a silicon substrate 1 to a thickness of about 5000 ° to open a contact hole 2a, and thereafter, as shown in FIG. 2B, a rhenium film is formed on the exposed silicon substrate 1. (Re) is grown to a thickness of about 500 ° by a selective CVD growth method to form a Re layer 3. The CVD growth is ReF ₆ , H ₂ , S
Each gas of iH ₄ was performed at a flow rate of 10 SCCM, 500 SCCM, and 5 SSCM for about 30 seconds at a growth temperature of 300 ° C. and a reaction chamber pressure of 0.05 Torr. At this time, the thickness of Re is reduced to several tens of atomic layers if the ideal clean surface is formed because Re ends without covering the Si surface without SiH ₄ (self-controlled deposition). Re precipitates and the reaction is apparently terminated. Therefore, substantial erosion is small. Further, reactivity, smaller than the WF ₆ is also a major factor.

Next, as shown in FIG. 1C, a W layer 4 having a thickness of 4000 ° was selectively grown on the Re layer 3 to form a source or drain electrode. This W layer 4 is grown by WF ₆ , H ₂ , and SiH ₄ gas at 5 SCC.
Flow at a flow rate of M, 500 SCCM, 5 SCCM, the same temperature as Re growth,
Pressure was applied and the growth rate was 200 nm / min.

In this embodiment, the Re layer 3 is adhered on the silicon substrate 1 at a lower temperature than W, with good adhesion, and silicon erosion is small. That is, the precipitation of Re with little erosion functions as a barrier against the chemical erosion of W on a thick film.

Next, a case of forming a gate lead-out electrode will be described as a second embodiment with reference to FIGS. 2A to 2D.

First, as shown in FIG. 2A, a gate oxide film (SiO ₂ ) 5 is formed on a silicon substrate 1 to a thickness of about 100 ° by a thermal oxidation method, and then a polycrystalline silicon (Poly Si) layer 6 is formed by a CVD method. It was formed to a thickness of about 400 mm.

Next, as shown in FIG. 2B, a Re layer 7 is
It was grown by CVD to a thickness of 00 mm. This CVD growth is based on ReF ₆ , H ₂ , Si
10 SCCM of each gas H _4, 200 SCCM, about 1 minute at a flow rate of 10 SCCM 3
The growth was performed at a growth temperature of 00 ° C. and a pressure of 0.1 Torr in the reaction chamber.

Next, as shown in FIG. 2C, a W layer 8 is
The thickness was formed by the CVD method. This W layer is grown by WF
₆ , H ₂ , and SiH ₄ gases were grown at a flow rate of 10 SCCM, 200 SCCM, and 10 SCCM for about 1 minute at a growth temperature of 300 ° C. and a reaction chamber pressure of 0.1 Torr.

Next, as shown in FIG. 2D, impurities were implanted and activation annealing was performed using a lamp. Annealing temperature is 900 ℃, about 1
Performed for 0 seconds. In this annealing, rhenium is silicidized at the same time to form a ReSiX layer 9 on the SiO ₂ film 5, and a gate electrode composed of the ReSix layer 9 and the W layer 8 is obtained on the silicon substrate. As in the first embodiment, the formation of the Re layer can prevent the erosion during the formation of W and prevent the oxide film breakdown voltage from deteriorating; a low-resistance gate electrode can be formed.

In FIG. 2B, a Re layer 7 is formed, and B ⁺ , P
After performing ion implantation such as ⁺ , the Re layer 7, the Poly Si layer 6, and the SiO ₂ 5 on the silicon substrate 1 are sequentially patterned as shown in FIG. 3A, and the Si ₃ N ₄ film is formed on the entire exposed surface. After forming a silicide, a Si ₃ N ₄ spacer 10 is formed on the side wall of the three layers by anisotropic etching, and then the W layer 8 is used by using the embodiment 1 or as shown in FIG. 3B. Direct selection CVD
It is formed on the Re layer 7 by a method.

The CVD growth conditions may be the same as those described with reference to FIG. 2C, and an annealing step may be performed.

〔The invention's effect〕

As described above, according to the present invention, when depositing Re or the like in the process temperature region of conventional W and CVD growth, self-controlling Si
No erosion due to termination of the reaction, and no junction (junction) destruction or gate oxide film destruction is observed. Further
Re and the like have excellent adhesion between W and Si, and do not peel off.

[Brief description of the drawings]

FIGS. 1A to 1C are process cross-sections for explaining a first embodiment of the present invention, and FIGS. 2A to 2D are process cross-sectional views for explaining a second embodiment of the present invention. FIGS. 3A and 3B are process cross-sectional views for explaining a modification of the second embodiment. 1 ...... silicon substrate, 2 ...... SiO ₂ film, 2a ...... contact hole, 3, 7 ...... Re layer, 4, 8 ...... W layer, 5 ...... SiO ₂ film, 6 ...... Poly Si layer, 9 … ReSix layer, 10… Si ₃ N ₄ spacer.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205 H01L 21/768 H01L 21/28-21/288 H01L 29/40-29/51

Claims (2)

(57) [Claims] 1. A step of forming an insulating film having a contact hole on a silicon layer, and selectively depositing a rhenium layer or a zirconium layer on the surface of the silicon layer in the contact hole by a chemical vapor deposition method. Forming a conductive layer selectively on the rhenium layer or zirconium layer by chemical vapor deposition, and filling the contact hole with the conductive layer. Device manufacturing method. 2. A method for selectively forming a rhenium layer or a zirconium layer on a semiconductor or a conductor by a chemical vapor deposition method, and a step of forming a tungsten layer on the rhenium or zirconium layer. A method for manufacturing a semiconductor device.