JP2803792B2 - Active matrix type liquid crystal display - Google Patents
Active matrix type liquid crystal displayInfo
- Publication number
- JP2803792B2 JP2803792B2 JP23055592A JP23055592A JP2803792B2 JP 2803792 B2 JP2803792 B2 JP 2803792B2 JP 23055592 A JP23055592 A JP 23055592A JP 23055592 A JP23055592 A JP 23055592A JP 2803792 B2 JP2803792 B2 JP 2803792B2
- Authority
- JP
- Japan
- Prior art keywords
- liquid crystal
- wiring
- active matrix
- data signal
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Description
【0001】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタを有
するアクティブマトリクス型液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display having thin film transistors.
【0002】[0002]
【従来の技術】図5にアクティブマトリクス型液晶表示
装置を構成するアクティブマトリクス基板の配線および
駆動回路の構成を示す。2. Description of the Related Art FIG. 1 shows the configuration of wiring and a drive circuit of an active matrix substrate constituting an active matrix type liquid crystal display device.
【0003】このアクティブマトリクス基板は絶縁性の
ベース基板113の上に複数の走査信号配線101と複
数のデーター信号配線102とが互いに直交して配設さ
れ、隣接する各走査信号配線101と各データ信号配線
102とが囲むそれぞれの領域には、絵素107のスイ
ッチング素子である薄膜トランジスタ105(ThinFi
lm Transistor、以下TFTと略称する。)が設けら
れている。また、絵素107と並列に付加容量106も
設けられており、データ信号はこの絵素107と付加容
量106とに書き込まれる。各絵素107および各付加
容量106のそれぞれのドレイン電極とは別の電極は走
査信号配線101に平行に配設される一本の付加容量配
線108に接続されている。これらの付加容量配線10
8はさらに一本の配線に集約され一つの共通電極111
に接続されている。この共通電極111はさらに対向基
板(図示せず)上の対向電極(図示せず)に接続されて
いる。全ての絵素107を包含する表示領域の周囲に
は、この表示領域を囲んで樹脂からなる所定の幅のシー
ル部材110が形成されており、このシール部材110
はベース基板113に対向配置される対向基板(図示せ
ず)とベース基板113との間に液晶を挟んで両基板を
接着している。In this active matrix substrate, a plurality of scanning signal wirings 101 and a plurality of data signal wirings 102 are arranged orthogonally to each other on an insulating base substrate 113. In each region surrounded by the signal wiring 102, a thin film transistor 105 (ThinFi) serving as a switching element of the picture element 107 is provided.
lm Transistor, hereinafter abbreviated as TFT. ) Is provided. An additional capacitor 106 is also provided in parallel with the picture element 107, and a data signal is written to the picture element 107 and the additional capacity 106. An electrode different from each drain electrode of each picture element 107 and each additional capacitance 106 is connected to one additional capacitance wiring 108 disposed in parallel with the scanning signal wiring 101. These additional capacitance lines 10
8 is further integrated into one line and one common electrode 111
It is connected to the. The common electrode 111 is further connected to a counter electrode (not shown) on a counter substrate (not shown). A seal member 110 of a predetermined width made of resin is formed around the display area including all the picture elements 107 so as to surround the display area.
Are bonded between a counter substrate (not shown) disposed opposite to the base substrate 113 and the base substrate 113 with a liquid crystal interposed therebetween.
【0004】走査信号線駆動回路104とデータ信号線
駆動回路103はそれぞれシール部材110が構成する
閉領域の外側に設けられる。これは、シール部材110
とそれぞれの駆動回路104、103とを重ねて形成す
ると駆動回路の歩留りが低下するためである。また、付
加容量配線108の共通電極111もシール部材110
の外側に形成され、対向基板上の対向電極(図示せず)
に接続される。The scanning signal line driving circuit 104 and the data signal line driving circuit 103 are provided outside the closed region formed by the seal member 110, respectively. This is the sealing member 110
This is because the yield of the driving circuits is reduced when the driving circuits 104 and 103 are formed so as to overlap with each other. Further, the common electrode 111 of the additional capacitance wiring 108 is also
Counter electrode (not shown) formed on the outside of the counter substrate
Connected to.
【0005】この様に走査信号線駆動回路104、デー
タ信号線駆動回路103、および付加容量配線108の
共通電極111はシール部材110の外側に形成される
ので、走査信号配線101と走査信号線駆動回路104
とを結ぶ配線、データ信号配線102とデータ信号線駆
動回路103とを結ぶ配線、および付加容量配線108
と付加容量配線108の共通電極111とを結ぶ配線は
それぞれシール部材110の直下を通る構造となってい
る。As described above, the scanning signal line driving circuit 104, the data signal line driving circuit 103, and the common electrode 111 of the additional capacitance wiring 108 are formed outside the seal member 110, so that the scanning signal line 101 and the scanning signal line driving Circuit 104
, A wiring connecting the data signal wiring 102 and the data signal line driving circuit 103, and an additional capacitance wiring 108.
The wiring connecting the common electrode 111 of the additional capacitance wiring 108 and the common electrode 111 has a structure that passes directly below the seal member 110.
【0006】[0006]
【発明が解決しようとする課題】ところで、シール部材
110の直下に配線を設ける構造のアクティブマトリク
ス基板では、その製造工程において配線の断線が多く発
生し、この構造のアクティブマトリクス基板を有する液
晶表示装置の製造の歩留りが低下するという問題があ
る。この断線の発生の原因を以下に述べる。By the way, in an active matrix substrate having a structure in which wiring is provided directly below the seal member 110, many disconnections occur in the manufacturing process, and a liquid crystal display device having an active matrix substrate having this structure is provided. However, there is a problem that the production yield of the semiconductor device is reduced. The cause of the disconnection will be described below.
【0007】液晶表示装置の製造工程において、アクテ
ィブマトリクス基板とその対向基板をシール部材で貼り
合わせる手順は一般的に次のように行われる。In the manufacturing process of a liquid crystal display device, a procedure for bonding an active matrix substrate and its counter substrate with a seal member is generally performed as follows.
【0008】まず、対向基板上にシール部材110用の
樹脂を印刷して所定のパターンを形成する。次にアクテ
ィブマトリクス基板と対向基板の水平方向の位置関係を
数μmの精度で位置合わせしつつ貼り合わせ、垂直方向
には両基板の間隔が5μmになるようにプレスする。こ
の場合樹脂中には所望の基板間隔に対応した径を持つフ
ァイバー等を混入させておく。そして、所望の位置にな
ったところで樹脂を加熱しUV光等の照射によりこの樹
脂を硬化させる。この垂直方向の位置決め時には約20
kgf/cm2という大きな圧力を必要とする。このためシ
ール部材の直下に形成した配線には大きな力が加わるこ
とになり、断線等の不良が発生する。First, a predetermined pattern is formed by printing a resin for the seal member 110 on the opposing substrate. Next, the active matrix substrate and the opposing substrate are bonded together while being positioned with a precision of several μm in the horizontal direction, and pressed so that the distance between the substrates in the vertical direction is 5 μm. In this case, a fiber or the like having a diameter corresponding to a desired substrate interval is mixed in the resin. When the desired position is reached, the resin is heated and the resin is cured by irradiation with UV light or the like. Approximately 20 for this vertical positioning
A large pressure of kgf / cm 2 is required. For this reason, a large force is applied to the wiring formed immediately below the seal member, and a defect such as disconnection occurs.
【0009】断線の起こり易さは、アクティブマトリク
ス基板の断面構造にもよる。The likelihood of disconnection depends on the cross-sectional structure of the active matrix substrate.
【0010】図6にアクティブマトリクス基板のTFT
105を含む部分の断面構成の一例を示す。FIG. 6 shows a TFT on an active matrix substrate.
5 shows an example of a cross-sectional configuration of a portion including the portion 105.
【0011】アクティブマトリクス基板は透明な絶縁性
のベース基板113の上に、TFT105の半導体部1
14、TFT105のソース電極115a、TFT10
5のドレイン電極115b、および付加容量の下部電極
116が形成されており、これらを覆うようにして基板
全体にゲート絶縁膜117が設けられている。このゲー
ト絶縁膜117の上にTFT105のゲート電極11
8、付加容量の上部電極119が形成されており、これ
らを覆って層間絶縁膜120が基板全面にわたって形成
されている。層間絶縁膜120の上にデータ信号配線1
21が形成されており、さらにこれを覆って第2の層間
絶縁膜122が基板全面にわたって形成されている。そ
して、第2の層間絶縁膜122の上に透明導電膜からな
る絵素電極123がパターン形成されている。この絵素
電極123はTFT105のドレイン電極115b部の
形成位置においてゲート絶縁膜117、第1の層間絶縁
膜、および第2の層間絶縁膜を貫いて形成されているコ
ンタクトホールを介してこのTFT105のドレイン電
極115bに接続されている。シール直下を通る配線は
抵抗が低いことが望ましいが、データ信号の遅延、なま
りを抑制するためにも更に低抵抗であることが要求さ
れ、上記のような断面構造の場合にはこの配線はデータ
信号配線と共にAlなどの低抵抗金属を用いて形成する
ことが一般的である。また、低抵抗化のためにある程度
膜厚を厚くすることが望ましいが、膜厚の厚いAlは平
坦化することが難しい。従って、この配線が形成された
部分は凹凸が激しく、配線の真上にあるシール部材11
0に加えられる力の影響を受け易いので断線が起こり易
くなる。シール部材110の直下を通る配線は表示部の
素子数にもよるが、一般的に数百ないし数千という単位
であり、この内の一本でも断線していると表示装置とし
ては致命的な欠陥となる。An active matrix substrate is formed on a transparent insulating base substrate 113 on a semiconductor portion 1 of a TFT 105.
14, the source electrode 115a of the TFT 105, the TFT 10
5, a drain electrode 115b and a lower electrode 116 of an additional capacitor are formed, and a gate insulating film 117 is provided on the entire substrate so as to cover them. The gate electrode 11 of the TFT 105 is formed on the gate insulating film 117.
8. An upper electrode 119 of additional capacitance is formed, and an interlayer insulating film 120 is formed over the entire surface of the substrate to cover them. Data signal wiring 1 on interlayer insulating film 120
21 is formed, and a second interlayer insulating film 122 is formed over the entire surface of the substrate 21 so as to cover it. Then, a pixel electrode 123 made of a transparent conductive film is pattern-formed on the second interlayer insulating film 122. The pixel electrode 123 is connected to the TFT 105 via a contact hole formed through the gate insulating film 117, the first interlayer insulating film, and the second interlayer insulating film at the position where the drain electrode 115b of the TFT 105 is formed. It is connected to the drain electrode 115b. It is desirable that the wiring passing directly below the seal has a low resistance, but further low resistance is required in order to suppress delay and rounding of data signals. It is common to use a low resistance metal such as Al together with the signal wiring. Further, it is desirable to increase the film thickness to some extent in order to reduce the resistance, but it is difficult to flatten Al having a large film thickness. Therefore, the portion where the wiring is formed is very uneven, and the sealing member 11 just above the wiring is formed.
The wire is easily affected by the force applied to 0, so that disconnection is likely to occur. The wiring passing directly below the seal member 110 depends on the number of elements of the display portion, but is generally in the unit of several hundred to several thousand. If any one of these wires is broken, it is fatal for a display device. It becomes a defect.
【0012】本発明は、このような従来技術の課題を解
決するためになされたものであり、アクティブマトリク
ス型の液晶表示装置において、アクティブマトリクス基
板のシール部材の直下に配設される配線の断線不良の発
生を抑制し、歩留りの高い製造が可能な構造のアクティ
ブマトリクス基板を有する液晶表示装置を提供すること
を目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and in an active matrix type liquid crystal display device, disconnection of a wiring disposed immediately below a seal member of an active matrix substrate. It is an object of the present invention to provide a liquid crystal display device having an active matrix substrate having a structure capable of suppressing the occurrence of defects and capable of manufacturing with high yield.
【0013】[0013]
【課題を解決するための手段】本発明のアクティブマト
リクス型液晶表示装置は、対向配置される一対の絶縁性
基板の間に液晶層が挟持され、該一対の絶縁性基板の一
方の液晶層側の面に絵素電極がマトリクス状に配設され
ているとともに、各絵素電極の周囲を通って複数の走査
信号配線と複数のデータ信号配線とが互いに交差して配
設され、さらに両信号配線の交差部の近傍に設けられた
スイッチング素子が絵素電極に接続されたアクティブマ
トリクス型液晶表示装置であって、該絵素電極がマトリ
クス状に設けられた表示領域の外側に、該表示領域を囲
み、かつ、該一対の絶縁性基板ではさんで設けられたシ
ール部材により該液晶が封止され、各走査信号配線と各
データ信号配線とがシール部材の外側に延出されている
とともに、各走査信号配線と各データ信号配線のそれぞ
れのシール部材と重なる部分が複数本の分岐線で構成さ
れている、そのことにより、上記目的が達成される。In the active matrix type liquid crystal display device according to the present invention, a liquid crystal layer is sandwiched between a pair of insulating substrates which are arranged to face each other, and one of the pair of insulating substrates is closer to the liquid crystal layer. Pixel electrodes are arranged in a matrix on the surface of each of the pixels, and a plurality of scanning signal wirings and a plurality of data signal wirings are arranged so as to cross each other around each of the pixel electrodes. A switching element provided in the vicinity of an intersection of wiring is an active matrix liquid crystal display device connected to a pixel electrode, wherein the display region is provided outside a display region in which the pixel electrode is provided in a matrix. , And the liquid crystal is sealed by a seal member provided between the pair of insulating substrates, and each scanning signal line and each data signal line extend outside the seal member. Each scan Each of the seal member and the overlapped portion of the No. wiring and the data signal lines is composed of a plurality of branch lines, by the above-described object is achieved.
【0014】また、前記シール部材と重なる各走査信号
配線部分と各データ信号配線部分とが厚み300nm以上
で形成されていてもよい。Further, each of the scanning signal wiring portions and each of the data signal wiring portions overlapping the seal member may be formed with a thickness of 300 nm or more.
【0015】また、前記分岐線の少なくとも一本が走査
信号配線と同一面上に形成され、他の分岐線の少なくと
も一本がデータ信号配線と同一面上に形成されていても
よい。Further, at least one of the branch lines may be formed on the same plane as the scanning signal wiring, and at least one of the other branch lines may be formed on the same plane as the data signal wiring.
【0016】また、前記走査信号配線および/または前
記データ信号配線へ信号を与える駆動回路が同一基板上
に設けられていてもよい。Further, a driving circuit for supplying a signal to the scanning signal wiring and / or the data signal wiring may be provided on the same substrate.
【0017】[0017]
【作用】本発明によれば、アクティブマトリクス型液晶
表示装置の各走査信号配線と各データ信号配線とが液晶
のシール部材の外側に延出されているとともに、各走査
信号配線と各データ信号配線のそれぞれのシール部材と
重なる部分を挟む区間が複数本の分岐線で構成されてい
る。よって、一本の分岐線が断線しても残りの分岐線に
より導通が可能となる。According to the present invention, each scanning signal wiring and each data signal wiring of the active matrix type liquid crystal display device extend outside the liquid crystal sealing member, and each scanning signal wiring and each data signal wiring are provided. A section sandwiching a portion overlapping each of the seal members is constituted by a plurality of branch lines. Therefore, even if one branch line is broken, conduction is enabled by the remaining branch lines.
【0018】[0018]
【実施例】以下、本発明の実施例を説明する。Embodiments of the present invention will be described below.
【0019】[第1の実施例]図1に本発明によるアク
ティブマトリクス型液晶表示装置を構成するアクティブ
マトリクス基板の回路構成の一部を示す。[First Embodiment] FIG. 1 shows a part of a circuit configuration of an active matrix substrate constituting an active matrix type liquid crystal display device according to the present invention.
【0020】絶縁性のベース基板20の上に複数の走査
信号配線1と複数のデーター信号配線2とが互いに直交
して配設され、隣接する各走査信号配線1と各データ信
号配線2とが囲むそれぞれの領域には、絵素7のスイッ
チング素子である薄膜トランジスタ5(Thin Film
Transistor、以下TFTと略称する。)が設けられて
いる。この薄膜トランジスタ5はその領域を構成する一
方の走査信号配線1とデータ信号配線2とに接続されて
いる。また、各絵素7にはそれぞれの絵素7と並列に付
加容量6も設けられており、TFT5がオンの時、デー
タ信号はこの絵素7と付加容量6とに書き込まれる。各
絵素7および各付加容量6のそれぞれのドレイン電極と
は別の電極は走査信号配線1に平行に配設される一本の
付加容量配線8に接続されている。これらの付加容量配
線8はさらに一本の配線に集約され一つの共通電極11
に接続されている。この共通電極11はさらに対向基板
(図示せず)上の対向電極(図示せず)に接続されてい
る。A plurality of scanning signal wirings 1 and a plurality of data signal wirings 2 are arranged on an insulating base substrate 20 at right angles to each other, and adjacent scanning signal wirings 1 and data signal wirings 2 are connected to each other. In each of the surrounding areas, a thin film transistor 5 (Thin Film) which is a switching element of the picture element 7 is provided.
Transistor, hereinafter abbreviated as TFT. ) Is provided. The thin film transistor 5 is connected to one of the scanning signal wirings 1 and the data signal wirings 2 constituting the region. Each picture element 7 is also provided with an additional capacitor 6 in parallel with each picture element 7. When the TFT 5 is turned on, a data signal is written into the picture element 7 and the additional capacity 6. An electrode different from the drain electrode of each picture element 7 and each additional capacitance 6 is connected to one additional capacitance wiring 8 arranged in parallel with the scanning signal wiring 1. These additional capacitance lines 8 are further integrated into one line to form one common electrode 11.
It is connected to the. The common electrode 11 is further connected to a counter electrode (not shown) on a counter substrate (not shown).
【0021】全ての絵素7を包含する表示領域の周囲に
は、この表示領域を囲んで樹脂からなる所定の幅のシー
ル部材10が形成されており、このシール部材10はベ
ース基板20に対向配置される対向基板(図示せず)と
ベース基板20との間に液晶(図示せず)を挟んで、両
基板を接着している。A seal member 10 of a predetermined width made of resin is formed around the display area including all the picture elements 7 so as to surround the display area, and the seal member 10 faces the base substrate 20. A liquid crystal (not shown) is interposed between a counter substrate (not shown) and a base substrate 20 which are arranged, and the two substrates are bonded to each other.
【0022】シール部材10の外側、つまり表示領域の
外側には走査信号線駆動回路4とデータ信号線駆動回路
3および付加容量配線8の共通電極11が設けられてお
り、走査信号配線1と走査信号線駆動回路4とを結ぶ配
線、データ信号配線2とデータ信号線駆動回路3とを結
ぶ配線、および付加容量配線8と付加容量配線8の共通
電極11とを結ぶ配線はそれぞれシール部材10の直下
を通る。シール部材10の直下を通過する配線はデータ
信号配線2と同じ低抵抗金属を用いて形成されるが、こ
の区間の配線のそれぞれには、この配線の分岐線12が
設けられている。The scanning signal line driving circuit 4, the data signal line driving circuit 3, and the common electrode 11 of the additional capacitance line 8 are provided outside the seal member 10, that is, outside the display area. The wiring connecting the signal line driving circuit 4, the wiring connecting the data signal wiring 2 and the data signal line driving circuit 3, and the wiring connecting the additional capacitance wiring 8 and the common electrode 11 of the additional capacitance wiring 8 are each formed of the sealing member 10. Pass directly below. The wiring passing directly below the seal member 10 is formed using the same low-resistance metal as the data signal wiring 2, and each of the wirings in this section is provided with a branch line 12 of this wiring.
【0023】図2はこのシール部材10の直下を通る配
線とその分岐線12の構造を詳細に示している。配線の
分岐線12は配線に平行に走り、分岐線12が配線から
分岐する二箇所の分岐点はそれぞれシール部材10の内
側(表示領域側)と外側に設けられている。このような
構造のため、配線とその分岐線12の内のいずれかが断
線しても残りの道筋の配線あるいは分岐線12が断線し
なければ、表示装置としては不良とならない。FIG. 2 shows in detail the structure of the wiring passing directly below the seal member 10 and the branch line 12 thereof. The branch line 12 of the wiring runs parallel to the wiring, and two branch points where the branch line 12 branches from the wiring are provided inside (on the display area side) and outside the seal member 10, respectively. Due to such a structure, even if one of the wiring and the branch line 12 is broken, if the wiring of the remaining route or the branch line 12 is not broken, the display device will not be defective.
【0024】従ってこの配線および分岐線12には低抵
抗化のために膜厚の厚い配線を用いても良好な歩留りが
得られることが期待でき、データ信号配線2と同じ低抵
抗金属を用いて300nm以上の厚みのものを用いること
も可能である。Therefore, it can be expected that a good yield can be obtained even if a thick wiring is used for the wiring and the branch line 12 in order to reduce the resistance, and the same low resistance metal as the data signal wiring 2 is used. It is also possible to use one having a thickness of 300 nm or more.
【0025】本実施例では一つの配線に対して一本だけ
の分岐線12を設ける構造としたが一つの配線に対して
複数本の分岐線12を設けても良い。In this embodiment, only one branch line 12 is provided for one wiring, but a plurality of branch lines 12 may be provided for one wiring.
【0026】[第2の実施例]第2の実施例において
は、図3に示すようにシール部材10直下の区間にある
配線とこの配線に平行に走る分岐線12の間に、配線の
走る方向に垂直に複数の分岐路13を設け、これらの分
岐路13によって配線と分岐線12をつないでいる。従
って、第1の実施例のようにシール部材10直下の配線
の分岐線12が配線に平行に走る道筋だけの構造である
のに比べて迂回路が増えるので、断線不良を回避できる
確率が高くなっている。[Second Embodiment] In the second embodiment, as shown in FIG. 3, a wiring runs between a wiring in a section directly below the seal member 10 and a branch line 12 running parallel to the wiring. A plurality of branch paths 13 are provided perpendicular to the direction, and the wiring and the branch line 12 are connected by these branch paths 13. Therefore, the number of detours is increased as compared with the case where the branch line 12 of the wiring immediately below the seal member 10 is a structure having only a path running parallel to the wiring as in the first embodiment. Has become.
【0027】[第3の実施例]図4に本発明の第3の実
施例によるシール部材10直下の配線構造を示す。[Third Embodiment] FIG. 4 shows a wiring structure immediately below a seal member 10 according to a third embodiment of the present invention.
【0028】第3の実施例においては、図4(a)に示
すように走査信号配線1と同じ層において形成される配
線に、この配線のシール部材10の外側と内側の地点に
設けられたコンタクトホール14を介してデータ信号配
線2と同じ層で形成された分岐線12を並列に接続して
いる。この実施例においては、配線に走査信号配線1と
同じ層のものを用い、分岐線にデータ信号配線2と同じ
層のものを用いたが、配線にデータ信号配線2と同じ層
のものを用い、分岐線に走査信号配線1と同じ層のもの
を用いてもよい。図4(b)はコンタクトホール14を
シール部材10の外側と内側だけでなく、シール部材1
0の直下の区間にも設ける場合を示している。第3の実
施例の(b)の場合も第1の実施例に比べてシール部材
10直下の配線の迂回路が増える構造であるので、断線
不良を回避できる確立が高くなっている。In the third embodiment, as shown in FIG. 4A, wirings formed in the same layer as the scanning signal wiring 1 are provided at points outside and inside the seal member 10 of the wiring. The branch lines 12 formed in the same layer as the data signal wiring 2 are connected in parallel via the contact holes 14. In this embodiment, the wiring has the same layer as the scanning signal wiring 1 and the branch line has the same layer as the data signal wiring 2, but the wiring has the same layer as the data signal wiring 2. Alternatively, a branch line having the same layer as the scanning signal wiring 1 may be used. FIG. 4B shows that the contact hole 14 is formed not only on the outside and inside of the seal member 10 but also on the seal member 1.
A case is also shown in which a section is provided immediately below 0. Also in the case of (b) of the third embodiment, since the structure is such that the number of detours of the wiring directly below the seal member 10 is increased as compared with the first embodiment, the probability of avoiding a disconnection failure is high.
【0029】また、第3の実施例においてはシール部材
10直下の配線の一方を走査信号線1と同じ層において
形成するが、この走査信号線1はSiを用いて形成され
ることが多く、Siは金属に比べて耐熱性が高く、より
高温のプロセスを用いることができるため、その断差を
平坦化し易い。従って、第3の実施例においてSiを用
いて形成される配線はその平坦化が容易に行え、シール
部材10に圧力を加えて基板を接着させる際に配線に加
わる不均一な力の発生を抑制することができ、上記の構
造と相まってシール部形成時の断線の発生をさらに抑さ
えることが期待できる。In the third embodiment, one of the wirings immediately below the seal member 10 is formed in the same layer as the scanning signal line 1, but this scanning signal line 1 is often formed using Si. Since Si has higher heat resistance than a metal and can use a higher temperature process, it is easy to flatten the difference. Therefore, the wiring formed by using Si in the third embodiment can be easily flattened, and the generation of uneven force applied to the wiring when applying pressure to the sealing member 10 and bonding the substrate is suppressed. It can be expected that the occurrence of disconnection at the time of forming the seal portion can be further suppressed in combination with the above structure.
【0030】[0030]
【発明の効果】以上、詳述したように本発明のアクティ
ブマトリクス基板の構成によれば、シール樹脂の直下に
配設される配線のそれぞれに複路が設けられるので、各
配線とその複路のいずれかが断線しても他方が断線しな
ければ不良とはならないので、製造工程中における断線
不良の発生を抑制できる。従って、本発明のアクティブ
マトリクス基板の構成によれば断線不良の少ない液晶表
示装置を歩留り高く製造できる。As described above in detail, according to the structure of the active matrix substrate of the present invention, since each of the wirings disposed immediately below the sealing resin is provided with multiple paths, each wiring and its multiple paths are provided. Even if one of them is disconnected, it is not a failure unless the other is disconnected, so that the occurrence of disconnection failure during the manufacturing process can be suppressed. Therefore, according to the configuration of the active matrix substrate of the present invention, a liquid crystal display device with few disconnection defects can be manufactured with high yield.
【図1】本発明による液晶表示装置のアクティブマトリ
クス基板の配線及び回路構成を示す図。FIG. 1 is a diagram showing wiring and a circuit configuration of an active matrix substrate of a liquid crystal display device according to the present invention.
【図2】本発明の第1の実施例によるアクティブマトリ
クス基板のシール部材直下の配線とその分岐線を示す
図。FIG. 2 is a diagram showing a wiring immediately below a seal member of the active matrix substrate and a branch line thereof according to the first embodiment of the present invention.
【図3】本発明の第2の実施例によるアクティブマトリ
クス基板のシール部材直下の配線とその分岐線を示す
図。FIG. 3 is a view showing a wiring immediately below a seal member and a branch line thereof on an active matrix substrate according to a second embodiment of the present invention.
【図4】本発明の第3の実施例によるアクティブマトリ
クス基板のシール部材直下の配線とその分岐線を示す
図。(a)はコンタクトホール14をシール部材10の
両側にのみ設ける場合を示し、(b)はコンタクトホー
ル14をシール部材10の直下の区間にも設ける場合を
示す。FIG. 4 is a view showing a wiring immediately below a seal member of an active matrix substrate and a branch line thereof according to a third embodiment of the present invention. (A) shows a case where the contact holes 14 are provided only on both sides of the seal member 10, and (b) shows a case where the contact holes 14 are also provided in a section directly below the seal member 10.
【図5】従来例によるアクティブマトリクス基板の配線
及び駆動回路構成を示す図。FIG. 5 is a diagram showing a wiring and drive circuit configuration of an active matrix substrate according to a conventional example.
【図6】アクティブマトリクス基板のTFTを含む部分
の断面図。FIG. 6 is a cross-sectional view of a portion including a TFT of an active matrix substrate.
1 走査信号配線 2 データ信号配線 3 データ信号線駆動回路 4 走査信号線駆動回路 5 薄膜トランジスタ(TFT) 6 付加容量 7 絵素 8 付加容量配線 10 シール部材 11 共通電極 12 配線の分岐線 13 分岐線の分岐路 14 コンタクトホール 20 ベース基板 REFERENCE SIGNS LIST 1 scanning signal wiring 2 data signal wiring 3 data signal line driving circuit 4 scanning signal line driving circuit 5 thin film transistor (TFT) 6 additional capacitance 7 picture element 8 additional capacitance wiring 10 sealing member 11 common electrode 12 wiring branch line 13 branch line Branch 14 Contact hole 20 Base substrate
フロントページの続き (72)発明者 吉村 洋二 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (72)発明者 久保 真澄 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (58)調査した分野(Int.Cl.6,DB名) G02F 1/1345 G02F 1/1339Continued on the front page (72) Inventor Yoji Yoshimura 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (72) Inventor Masumi 22-22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (58 ) Surveyed field (Int.Cl. 6 , DB name) G02F 1/1345 G02F 1/1339
Claims (4)
晶層が挟持され、 該一対の絶縁性基板の一方の液晶層側の面に絵素電極が
マトリクス状に配設されているとともに、各絵素電極の
周囲を通って複数の走査信号配線と複数のデータ信号配
線とが互いに交差して配設され、さらに両信号配線の交
差部の近傍に設けられたスイッチング素子が絵素電極に
接続されたアクティブマトリクス型液晶表示装置であっ
て、 該絵素電極がマトリクス状に設けられた表示領域の外側
に、該表示領域を囲み、かつ、該一対の絶縁性基板では
さんで設けられたシール部材により該液晶が封止され、
各走査信号配線と各データ信号配線とがシール部材の外
側に延出されているとともに、各走査信号配線と各デー
タ信号配線のそれぞれのシール部材と重なる部分が複数
本の分岐線で構成されているアクティブマトリクス型液
晶表示装置。1. A liquid crystal layer is sandwiched between a pair of insulating substrates arranged opposite to each other, and picture element electrodes are arranged in a matrix on a surface of one of the pair of insulating substrates on a liquid crystal layer side. In addition, a plurality of scanning signal wirings and a plurality of data signal wirings are provided so as to cross each other through the periphery of each picture element electrode, and a switching element provided near an intersection of the two signal wirings is a picture element. An active matrix liquid crystal display device connected to electrodes, wherein the pixel electrodes surround the display region outside a display region provided in a matrix, and are provided between the pair of insulating substrates. The liquid crystal is sealed by the provided sealing member,
Each scanning signal line and each data signal line extend outside the seal member, and a portion of each scan signal line and each data signal line overlapping with each seal member is constituted by a plurality of branch lines. Active matrix type liquid crystal display device.
分と各データ信号配線部分とが厚み300nm以上で形成
されている請求項1に記載のアクティブマトリクス型液
晶表示装置。2. The active matrix type liquid crystal display device according to claim 1, wherein each scanning signal wiring portion and each data signal wiring portion overlapping the seal member are formed with a thickness of 300 nm or more.
線と同一面上に形成され、他の分岐線の少なくとも一本
がデータ信号配線と同一面上に形成されている請求項1
または2に記載のアクティブマトリクス型液晶表示装
置。3. The semiconductor device according to claim 1, wherein at least one of the branch lines is formed on the same plane as the scanning signal wiring, and at least one of the other branch lines is formed on the same plane as the data signal wiring.
Or an active matrix liquid crystal display device according to 2.
タ信号配線へ信号を与える駆動回路が同一基板上に設け
られている請求項1、2または3に記載のアクティブマ
トリクス型液晶表示装置。4. The active matrix type liquid crystal display device according to claim 1, wherein a driving circuit for supplying a signal to said scanning signal wiring and / or said data signal wiring is provided on the same substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23055592A JP2803792B2 (en) | 1992-08-28 | 1992-08-28 | Active matrix type liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23055592A JP2803792B2 (en) | 1992-08-28 | 1992-08-28 | Active matrix type liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0682815A JPH0682815A (en) | 1994-03-25 |
| JP2803792B2 true JP2803792B2 (en) | 1998-09-24 |
Family
ID=16909596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23055592A Expired - Fee Related JP2803792B2 (en) | 1992-08-28 | 1992-08-28 | Active matrix type liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2803792B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3737176B2 (en) | 1995-12-21 | 2006-01-18 | 株式会社半導体エネルギー研究所 | Liquid crystal display |
| JP2001222017A (en) | 1999-05-24 | 2001-08-17 | Fujitsu Ltd | Liquid crystal display device and method of manufacturing the same |
| JP4587063B2 (en) * | 2004-03-18 | 2010-11-24 | 奇美電子股▲ふん▼有限公司 | Display device |
| KR101404542B1 (en) * | 2006-05-25 | 2014-06-09 | 삼성디스플레이 주식회사 | Liquid crystal display |
| JP5062677B2 (en) * | 2007-09-18 | 2012-10-31 | 株式会社ジャパンディスプレイウェスト | Display device |
| JP5194162B2 (en) * | 2011-11-11 | 2013-05-08 | 株式会社半導体エネルギー研究所 | Liquid crystal display |
| JP2014021472A (en) * | 2012-07-24 | 2014-02-03 | Mitsubishi Electric Corp | Display panel and display device |
| CN103399434B (en) * | 2013-08-01 | 2015-09-16 | 深圳市华星光电技术有限公司 | Display panel and Fanout line structure thereof |
| JP6401923B2 (en) | 2014-03-20 | 2018-10-10 | 株式会社ジャパンディスプレイ | Liquid crystal display |
-
1992
- 1992-08-28 JP JP23055592A patent/JP2803792B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0682815A (en) | 1994-03-25 |
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